From: Melissa Wen <mwen@igalia.com>
To: "Timur Kristóf" <timur.kristof@gmail.com>,
amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com,
"Alex Hung" <alex.hung@amd.com>,
"Harry Wentland" <Harry.Wentland@amd.com>,
"Roman Li" <Roman.Li@amd.com>, "Leo Li" <sunpeng.li@amd.com>,
"David Airlie" <airlied@gmail.com>,
"Mario Limonciello" <mario.limonciello@amd.com>,
"Ivan Lipski" <ivan.lipski@amd.com>
Subject: Re: [PATCH 10/14] drm/amd/pm: Delete dummy get_dal_power_level implementations
Date: Thu, 30 Apr 2026 15:42:29 -0300 [thread overview]
Message-ID: <f11dd353-eb7f-4ac7-abbd-1812fd2de615@igalia.com> (raw)
In-Reply-To: <20260423191519.73127-11-timur.kristof@gmail.com>
On 23/04/2026 16:15, Timur Kristóf wrote:
> These implementations did not actually return
> the DAL power level, so they were effectively
> a no-op.
Nice catch!
Reviewed-by: Melissa Wen <mwen@igalia.com>
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 7 -------
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 15 ---------------
> .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 16 ----------------
> .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 17 -----------------
> 4 files changed, 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 8de8d66df95f4..5be6f82ecc6f5 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -963,12 +963,6 @@ static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time
> return 0;
> }
>
> -static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
> - struct amd_pp_simple_clock_info *info)
> -{
> - return -EINVAL;
> -}
> -
> static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
> enum pp_clock_type type, uint32_t mask)
> {
> @@ -1664,7 +1658,6 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> .store_cc6_data = smu10_store_cc6_data,
> .force_clock_level = smu10_force_clock_level,
> .emit_clock_levels = smu10_emit_clock_levels,
> - .get_dal_power_level = smu10_get_dal_power_level,
> .get_performance_level = smu10_get_performance_level,
> .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
> .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 1b8a57d987597..12f47ec87997d 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4387,20 +4387,6 @@ static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
> return AMD_FAN_CTRL_AUTO;
> }
>
> -static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
> - struct amd_pp_simple_clock_info *info)
> -{
> - struct phm_ppt_v2_information *table_info =
> - (struct phm_ppt_v2_information *)hwmgr->pptable;
> - struct phm_clock_and_voltage_limits *max_limits =
> - &table_info->max_clock_voltage_on_ac;
> -
> - info->engine_max_clock = max_limits->sclk;
> - info->memory_max_clock = max_limits->mclk;
> -
> - return 0;
> -}
> -
> static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
> struct pp_clock_levels_with_latency *clocks)
> {
> @@ -5645,7 +5631,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
> .set_fan_control_mode = vega10_set_fan_control_mode,
> .get_fan_control_mode = vega10_get_fan_control_mode,
> .read_sensor = vega10_read_sensor,
> - .get_dal_power_level = vega10_get_dal_power_level,
> .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
> .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
> .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> index 5a987a535e73e..6f2bb8fe0317e 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1822,21 +1822,6 @@ static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
> return AMD_FAN_CTRL_AUTO;
> }
>
> -static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
> - struct amd_pp_simple_clock_info *info)
> -{
> -#if 0
> - struct phm_ppt_v2_information *table_info =
> - (struct phm_ppt_v2_information *)hwmgr->pptable;
> - struct phm_clock_and_voltage_limits *max_limits =
> - &table_info->max_clock_voltage_on_ac;
> -
> - info->engine_max_clock = max_limits->sclk;
> - info->memory_max_clock = max_limits->mclk;
> -#endif
> - return 0;
> -}
> -
> static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
> uint32_t *clock,
> PPCLK_e clock_select,
> @@ -2963,7 +2948,6 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
> .set_fan_control_mode = vega12_set_fan_control_mode,
> .get_fan_control_mode = vega12_get_fan_control_mode,
> .read_sensor = vega12_read_sensor,
> - .get_dal_power_level = vega12_get_dal_power_level,
> .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
> .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
> .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> index 5193b7d0e11be..2a06d3e0253fb 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> @@ -2796,22 +2796,6 @@ static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
> }
> }
>
> -static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
> - struct amd_pp_simple_clock_info *info)
> -{
> -#if 0
> - struct phm_ppt_v2_information *table_info =
> - (struct phm_ppt_v2_information *)hwmgr->pptable;
> - struct phm_clock_and_voltage_limits *max_limits =
> - &table_info->max_clock_voltage_on_ac;
> -
> - info->engine_max_clock = max_limits->sclk;
> - info->memory_max_clock = max_limits->mclk;
> -#endif
> - return 0;
> -}
> -
> -
> static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
> struct pp_clock_levels_with_latency *clocks)
> {
> @@ -4446,7 +4430,6 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
> /* export to DAL */
> .get_sclk = vega20_dpm_get_sclk,
> .get_mclk = vega20_dpm_get_mclk,
> - .get_dal_power_level = vega20_get_dal_power_level,
> .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
> .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
> .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
next prev parent reply other threads:[~2026-04-30 18:42 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-23 19:15 [PATCH 00/14] drm/amd: Delete defunct DAL power level code Timur Kristóf
2026-04-23 19:15 ` [PATCH 01/14] drm/amd/display: Delete unimplemented dm_pp_apply_power_level_change_request() Timur Kristóf
2026-04-24 14:19 ` Melissa Wen
2026-04-24 16:27 ` Timur Kristóf
2026-04-29 20:02 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 02/14] drm/amd/display: Delete dce_get_required_clocks_state() Timur Kristóf
2026-04-29 20:03 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 03/14] drm/amd/display: Remove min/max clock levels from clk_mgr Timur Kristóf
2026-04-24 14:21 ` Melissa Wen
2026-04-24 16:28 ` Timur Kristóf
2026-04-29 20:05 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 04/14] drm/amd/display: Delete max_clocks_state from dm_pp_static_clock_info Timur Kristóf
2026-04-29 20:06 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 05/14] drm/amd/display: Set max supported display clock without max_clks_by_state Timur Kristóf
2026-04-29 20:24 ` Melissa Wen
2026-04-30 12:28 ` Timur Kristóf
2026-04-30 18:06 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 06/14] drm/amd/display: Delete max_clks_by_state from DCE clock manager Timur Kristóf
2026-04-29 20:29 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 07/14] drm/amd/display: Delete disp_clk_voltage from integrated info Timur Kristóf
2026-04-29 20:35 ` Melissa Wen
2026-04-30 12:30 ` Timur Kristóf
2026-04-23 19:15 ` [PATCH 08/14] drm/amd/display: Delete dm_pp_clocks_state Timur Kristóf
2026-04-29 20:37 ` Melissa Wen
2026-04-30 12:31 ` Timur Kristóf
2026-04-23 19:15 ` [PATCH 09/14] drm/amd/pm: Delete unused get_display_power_level() function Timur Kristóf
2026-04-30 17:56 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 10/14] drm/amd/pm: Delete dummy get_dal_power_level implementations Timur Kristóf
2026-04-30 18:42 ` Melissa Wen [this message]
2026-04-23 19:15 ` [PATCH 11/14] drm/amd/pm: Delete non-functional SMU8 get_dal_power_level implementation Timur Kristóf
2026-04-30 18:53 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 12/14] drm/amd/pm: Delete vddc_dep_on_dal_pwrl Timur Kristóf
2026-04-30 19:03 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 13/14] drm/amd/pm: Delete get_dal_power_level Timur Kristóf
2026-04-30 19:03 ` Melissa Wen
2026-04-23 19:15 ` [PATCH 14/14] drm/amd/pm: Delete PP_DAL_POWERLEVEL Timur Kristóf
2026-04-30 19:04 ` Melissa Wen
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