Re: [PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>]

On Thu, Jul 05, 2018 at 05:09:29PM +0800, Evan Quan wrote:
> For v2_0 rlc, rlc save restore list also needs to be initialized.
> However, there is no reg_list_format_direct_reg_list_length
> member(v2_1 spefic) for it.
> 
> Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d895afa6c69..8d870d4f8414 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -42,6 +42,7 @@
>  #define GFX9_MEC_HPD_SIZE 2048
>  #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
>  #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
> +#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
>  
>  #define mmPWR_MISC_CNTL_STATUS					0x0183
>  #define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
> @@ -1927,7 +1928,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
>  	/* setup unique_indirect_regs array and indirect_start_offsets array */
>  	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
>  	gfx_v9_1_parse_ind_reg_list(register_list_format,
> -				    adev->gfx.rlc.reg_list_format_direct_reg_list_length,
> +				    GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
>  				    adev->gfx.rlc.reg_list_format_size_bytes >> 2,
>  				    unique_indirect_regs,
>  				    unique_indirect_reg_count,
> @@ -1952,7 +1953,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
>  		adev->gfx.rlc.reg_list_format_start);
>  
>  	/* direct register portion */
> -	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
> +	for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)

This definition is actually defined on register_list_format.h in the ucode.
So we would better to put it in firmware header.

Thanks,
Ray

>  		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
>  			register_list_format[i]);
>  
> -- 
> 2.18.0
> 
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