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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Charlene Liu <Charlene.Liu@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Rodrigo.Siqueira@amd.com,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Bhawanpreet.Lakha@amd.com
Subject: [PATCH 14/19] drm/amd/display: guard DPPHY_Internal_ctrl
Date: Mon, 16 Mar 2020 09:49:15 -0400	[thread overview]
Message-ID: <20200316134920.2526155-15-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200316134920.2526155-1-Rodrigo.Siqueira@amd.com>

From: Charlene Liu <Charlene.Liu@amd.com>

[why]
this register not exist in some asic, based on request remove this from
dc.

[how]
add guard for sanization.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index eb13589b9a81..762109174fb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -62,11 +62,11 @@
 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
 	SRI(DP_SEC_CNTL1, DP, id), \
 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
 
 
 #define LE_DCN10_REG_LIST(id)\
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 	LE_DCN_COMMON_REG_LIST(id)
 
 struct dcn10_link_enc_aux_registers {
-- 
2.25.1

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  parent reply	other threads:[~2020-03-16 13:50 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 13:49 [PATCH 00/19] DC Patches March 16th, 2020 Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 01/19] drm/amd/display: update connector->display_info after read edid Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 02/19] drm/amd/display: Fix test pattern color space inconsistency for Linux Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 03/19] drm/amd/display: Remove redundant hdcp display state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 04/19] drm/amd/display: workaround for HDMI hotplug in DPMSOFF state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 05/19] drm/amd/display: fix split threshold w/a to work with mpo Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 06/19] drm/amd/display: Pass triplebuffer surface flip flags down to plane state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 07/19] drm/amd/display: Explicitly disable triplebuffer flips Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 08/19] drm/amd/display: Remove PSR dependency on swizzle mode Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 09/19] drm/amd/display: Set disable_dmcu flag properly per asic Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 10/19] drm/amd/display: Fallback to dmcub for psr when dmcu is disabled Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 11/19] drm/amd/display: remove magic numbers in hdcp_ddc Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 12/19] drm/amd/display: Program self refresh control register on boot Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 13/19] drm/amd/display: differentiate vsc sdp colorimetry use criteria between MST and SST Rodrigo Siqueira
2020-03-16 13:49 ` Rodrigo Siqueira [this message]
2020-03-16 13:49 ` [PATCH 15/19] drm/amd/display: combine watermark change and clock change for update clocks Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 16/19] drm/amd/display: Remove connect DIG FE to its BE during timing programming Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 17/19] drm/amd/display: DPP DTO isn't update properly Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 18/19] drm/amd/display: Allocate scratch space for DMUB CW7 Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 19/19] drm/amd/display: add on demand pipe merge logic for dcn2+ Rodrigo Siqueira

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