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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Aric Cyr <Aric.Cyr@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Rodrigo.Siqueira@amd.com, Nikola Cornij <nikola.cornij@amd.com>,
	Bhawanpreet.Lakha@amd.com
Subject: [PATCH 16/19] drm/amd/display: Remove connect DIG FE to its BE during timing programming
Date: Mon, 16 Mar 2020 09:49:17 -0400	[thread overview]
Message-ID: <20200316134920.2526155-17-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200316134920.2526155-1-Rodrigo.Siqueira@amd.com>

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
Causes regression with MST DSC displays not lighting up after DPMS

[how]
Revert commit 3ee07fdc908c40f570f8ce25f12b5ad6463b87ad
"dc: Program DSC during timing programming"

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      | 11 +++--------
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  7 -------
 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h    |  1 -
 4 files changed, 4 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fb603bd46fac..67cfff1586e9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3069,14 +3069,9 @@ void core_link_enable_stream(
 
 		if (pipe_ctx->stream->timing.flags.DSC) {
 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-					dc_is_virtual_signal(pipe_ctx->stream->signal)) {
-				/* Here we only need to enable DSC on RX. DSC HW programming
-				 * was done earlier, as part of timing programming.
-				 */
-				dp_set_dsc_on_rx(pipe_ctx, true);
-			}
+					dc_is_virtual_signal(pipe_ctx->stream->signal))
+				dp_set_dsc_enable(pipe_ctx, true);
 		}
-
 		dc->hwss.enable_stream(pipe_ctx);
 
 		/* Set DPS PPS SDP (AKA "info frames") */
@@ -3103,7 +3098,7 @@ void core_link_enable_stream(
 	} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
 				dc_is_virtual_signal(pipe_ctx->stream->signal))
-			dp_set_dsc_on_rx(pipe_ctx, true);
+			dp_set_dsc_enable(pipe_ctx, true);
 
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index ac2103dec9e7..51e0ee6e7695 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -394,7 +394,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
 	DC_LOG_DSC("\tslice_width %d", config->slice_width);
 }
 
-bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 {
 	struct dc *dc = pipe_ctx->stream->ctx->dc;
 	struct dc_stream_state *stream = pipe_ctx->stream;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 69eb7b3697d2..233318260da4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -623,13 +623,6 @@ enum dc_status dcn20_enable_stream_timing(
 
 	/* TODO check if timing_changed, disable stream if timing changed */
 
-	/* Have to setup DSC here to make sure the bandwidth sent to DIG BE won't be bigger than
-	 * what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag will be automatically
-	 * set at a later time when the video is enabled (DP_VID_STREAM_EN = 1).
-	 */
-	if (pipe_ctx->stream->timing.flags.DSC)
-		dp_set_dsc_on_stream(pipe_ctx, true);
-
 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 		opp_cnt++;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 64f401e4db54..e94e5fbf2aa2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -85,7 +85,6 @@ void dp_set_fec_enable(struct dc_link *link, bool enable);
 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
-bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
 
 #endif /* __DC_LINK_DP_H__ */
-- 
2.25.1

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  parent reply	other threads:[~2020-03-16 13:50 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 13:49 [PATCH 00/19] DC Patches March 16th, 2020 Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 01/19] drm/amd/display: update connector->display_info after read edid Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 02/19] drm/amd/display: Fix test pattern color space inconsistency for Linux Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 03/19] drm/amd/display: Remove redundant hdcp display state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 04/19] drm/amd/display: workaround for HDMI hotplug in DPMSOFF state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 05/19] drm/amd/display: fix split threshold w/a to work with mpo Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 06/19] drm/amd/display: Pass triplebuffer surface flip flags down to plane state Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 07/19] drm/amd/display: Explicitly disable triplebuffer flips Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 08/19] drm/amd/display: Remove PSR dependency on swizzle mode Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 09/19] drm/amd/display: Set disable_dmcu flag properly per asic Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 10/19] drm/amd/display: Fallback to dmcub for psr when dmcu is disabled Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 11/19] drm/amd/display: remove magic numbers in hdcp_ddc Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 12/19] drm/amd/display: Program self refresh control register on boot Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 13/19] drm/amd/display: differentiate vsc sdp colorimetry use criteria between MST and SST Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 14/19] drm/amd/display: guard DPPHY_Internal_ctrl Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 15/19] drm/amd/display: combine watermark change and clock change for update clocks Rodrigo Siqueira
2020-03-16 13:49 ` Rodrigo Siqueira [this message]
2020-03-16 13:49 ` [PATCH 17/19] drm/amd/display: DPP DTO isn't update properly Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 18/19] drm/amd/display: Allocate scratch space for DMUB CW7 Rodrigo Siqueira
2020-03-16 13:49 ` [PATCH 19/19] drm/amd/display: add on demand pipe merge logic for dcn2+ Rodrigo Siqueira

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