* [PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 03/45] drm/amdgpu: add uapi to define van gogh series Alex Deucher
` (42 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds van gogh to amd_asic_type enum and amdgpu_asic_name[].
v2: add missing comma
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fc216cac345..ecaa35ada79c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -114,6 +114,7 @@ const char *amdgpu_asic_name[] = {
"NAVI12",
"SIENNA_CICHLID",
"NAVY_FLOUNDER",
+ "VANGOGH",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 8712e14991ed..6d01cf04b77f 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -56,6 +56,7 @@ enum amd_asic_type {
CHIP_NAVI12, /* 27 */
CHIP_SIENNA_CICHLID, /* 28 */
CHIP_NAVY_FLOUNDER, /* 29 */
+ CHIP_VANGOGH, /* 30 */
CHIP_LAST,
};
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 03/45] drm/amdgpu: add uapi to define van gogh series
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
2020-09-25 20:09 ` [PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2) Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting Alex Deucher
` (41 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add a flag to define van gogh series.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d3dadf10b13d..8d416188ddb3 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1086,6 +1086,7 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
+#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
/*
* Definition of free sync enter and exit signals
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
2020-09-25 20:09 ` [PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2) Alex Deucher
2020-09-25 20:09 ` [PATCH 03/45] drm/amdgpu: add uapi to define van gogh series Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
` (40 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds van gogh support for gpu_info firmware and ip block setting.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ecaa35ada79c..191d86c6c551 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,7 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1703,6 +1704,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1877,7 +1881,11 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
- adev->family = AMDGPU_FAMILY_NV;
+ case CHIP_VANGOGH:
+ if (adev->asic_type == CHIP_VANGOGH)
+ adev->family = AMDGPU_FAMILY_VGH;
+ else
+ adev->family = AMDGPU_FAMILY_NV;
r = nv_set_ip_blocks(adev);
if (r)
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (2 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-28 20:48 ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
` (39 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
.../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
4 files changed, 1569 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 39976c7b100c..7866e4666a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index aeef50a6a54b..8a3bf476b18f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
+int vangogh_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
new file mode 100644
index 000000000000..4c6c3b415e7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vangogh_ip_offset.h"
+
+int vangogh_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
new file mode 100644
index 000000000000..2875574b060e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
@@ -0,0 +1,1516 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_IP_OFFSET_H__
+#define __VANGOGH_IP_OFFSET_H__
+
+#define MAX_INSTANCE 8
+#define MAX_SEGMENT 6
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+ { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+ { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+ { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+ { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
+ { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
+ { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
+ { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0 0x02403800
+#define ACP_BASE__INST0_SEG1 0x00480000
+#define ACP_BASE__INST0_SEG2 0
+#define ACP_BASE__INST0_SEG3 0
+#define ACP_BASE__INST0_SEG4 0
+#define ACP_BASE__INST0_SEG5 0
+
+#define ACP_BASE__INST1_SEG0 0
+#define ACP_BASE__INST1_SEG1 0
+#define ACP_BASE__INST1_SEG2 0
+#define ACP_BASE__INST1_SEG3 0
+#define ACP_BASE__INST1_SEG4 0
+#define ACP_BASE__INST1_SEG5 0
+
+#define ACP_BASE__INST2_SEG0 0
+#define ACP_BASE__INST2_SEG1 0
+#define ACP_BASE__INST2_SEG2 0
+#define ACP_BASE__INST2_SEG3 0
+#define ACP_BASE__INST2_SEG4 0
+#define ACP_BASE__INST2_SEG5 0
+
+#define ACP_BASE__INST3_SEG0 0
+#define ACP_BASE__INST3_SEG1 0
+#define ACP_BASE__INST3_SEG2 0
+#define ACP_BASE__INST3_SEG3 0
+#define ACP_BASE__INST3_SEG4 0
+#define ACP_BASE__INST3_SEG5 0
+
+#define ACP_BASE__INST4_SEG0 0
+#define ACP_BASE__INST4_SEG1 0
+#define ACP_BASE__INST4_SEG2 0
+#define ACP_BASE__INST4_SEG3 0
+#define ACP_BASE__INST4_SEG4 0
+#define ACP_BASE__INST4_SEG5 0
+
+#define ACP_BASE__INST5_SEG0 0
+#define ACP_BASE__INST5_SEG1 0
+#define ACP_BASE__INST5_SEG2 0
+#define ACP_BASE__INST5_SEG3 0
+#define ACP_BASE__INST5_SEG4 0
+#define ACP_BASE__INST5_SEG5 0
+
+#define ACP_BASE__INST6_SEG0 0
+#define ACP_BASE__INST6_SEG1 0
+#define ACP_BASE__INST6_SEG2 0
+#define ACP_BASE__INST6_SEG3 0
+#define ACP_BASE__INST6_SEG4 0
+#define ACP_BASE__INST6_SEG5 0
+
+#define ACP_BASE__INST7_SEG0 0
+#define ACP_BASE__INST7_SEG1 0
+#define ACP_BASE__INST7_SEG2 0
+#define ACP_BASE__INST7_SEG3 0
+#define ACP_BASE__INST7_SEG4 0
+#define ACP_BASE__INST7_SEG5 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C00
+#define ATHUB_BASE__INST0_SEG1 0x00013300
+#define ATHUB_BASE__INST0_SEG2 0x02408C00
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+#define ATHUB_BASE__INST0_SEG5 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+#define ATHUB_BASE__INST1_SEG5 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+#define ATHUB_BASE__INST2_SEG5 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+#define ATHUB_BASE__INST3_SEG5 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+#define ATHUB_BASE__INST4_SEG5 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+#define ATHUB_BASE__INST5_SEG5 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+#define ATHUB_BASE__INST6_SEG5 0
+
+#define ATHUB_BASE__INST7_SEG0 0
+#define ATHUB_BASE__INST7_SEG1 0
+#define ATHUB_BASE__INST7_SEG2 0
+#define ATHUB_BASE__INST7_SEG3 0
+#define ATHUB_BASE__INST7_SEG4 0
+#define ATHUB_BASE__INST7_SEG5 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+#define CLK_BASE__INST0_SEG5 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+#define CLK_BASE__INST1_SEG5 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+#define CLK_BASE__INST2_SEG5 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+#define CLK_BASE__INST3_SEG5 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+#define CLK_BASE__INST4_SEG5 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+#define CLK_BASE__INST5_SEG5 0
+
+#define CLK_BASE__INST6_SEG0 0x0001B400
+#define CLK_BASE__INST6_SEG1 0x0242E000
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+#define CLK_BASE__INST6_SEG5 0
+
+#define CLK_BASE__INST7_SEG0 0x00017E00
+#define CLK_BASE__INST7_SEG1 0x0240BC00
+#define CLK_BASE__INST7_SEG2 0
+#define CLK_BASE__INST7_SEG3 0
+#define CLK_BASE__INST7_SEG4 0
+#define CLK_BASE__INST7_SEG5 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+#define DF_BASE__INST0_SEG5 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+#define DF_BASE__INST1_SEG5 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+#define DF_BASE__INST2_SEG5 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+#define DF_BASE__INST3_SEG5 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+#define DF_BASE__INST4_SEG5 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+#define DF_BASE__INST5_SEG5 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+#define DF_BASE__INST6_SEG5 0
+
+#define DF_BASE__INST7_SEG0 0
+#define DF_BASE__INST7_SEG1 0
+#define DF_BASE__INST7_SEG2 0
+#define DF_BASE__INST7_SEG3 0
+#define DF_BASE__INST7_SEG4 0
+#define DF_BASE__INST7_SEG5 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0x00009000
+#define DCN_BASE__INST0_SEG4 0x02403C00
+#define DCN_BASE__INST0_SEG5 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+#define DCN_BASE__INST1_SEG5 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+#define DCN_BASE__INST2_SEG5 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+#define DCN_BASE__INST3_SEG5 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+#define DCN_BASE__INST4_SEG5 0
+
+#define DCN_BASE__INST5_SEG0 0
+#define DCN_BASE__INST5_SEG1 0
+#define DCN_BASE__INST5_SEG2 0
+#define DCN_BASE__INST5_SEG3 0
+#define DCN_BASE__INST5_SEG4 0
+#define DCN_BASE__INST5_SEG5 0
+
+#define DCN_BASE__INST6_SEG0 0
+#define DCN_BASE__INST6_SEG1 0
+#define DCN_BASE__INST6_SEG2 0
+#define DCN_BASE__INST6_SEG3 0
+#define DCN_BASE__INST6_SEG4 0
+#define DCN_BASE__INST6_SEG5 0
+
+#define DCN_BASE__INST7_SEG0 0
+#define DCN_BASE__INST7_SEG1 0
+#define DCN_BASE__INST7_SEG2 0
+#define DCN_BASE__INST7_SEG3 0
+#define DCN_BASE__INST7_SEG4 0
+#define DCN_BASE__INST7_SEG5 0
+
+#define DPCS_BASE__INST0_SEG0 0x00000012
+#define DPCS_BASE__INST0_SEG1 0x000000C0
+#define DPCS_BASE__INST0_SEG2 0x000034C0
+#define DPCS_BASE__INST0_SEG3 0x00009000
+#define DPCS_BASE__INST0_SEG4 0x02403C00
+#define DPCS_BASE__INST0_SEG5 0
+
+#define DPCS_BASE__INST1_SEG0 0
+#define DPCS_BASE__INST1_SEG1 0
+#define DPCS_BASE__INST1_SEG2 0
+#define DPCS_BASE__INST1_SEG3 0
+#define DPCS_BASE__INST1_SEG4 0
+#define DPCS_BASE__INST1_SEG5 0
+
+#define DPCS_BASE__INST2_SEG0 0
+#define DPCS_BASE__INST2_SEG1 0
+#define DPCS_BASE__INST2_SEG2 0
+#define DPCS_BASE__INST2_SEG3 0
+#define DPCS_BASE__INST2_SEG4 0
+#define DPCS_BASE__INST2_SEG5 0
+
+#define DPCS_BASE__INST3_SEG0 0
+#define DPCS_BASE__INST3_SEG1 0
+#define DPCS_BASE__INST3_SEG2 0
+#define DPCS_BASE__INST3_SEG3 0
+#define DPCS_BASE__INST3_SEG4 0
+#define DPCS_BASE__INST3_SEG5 0
+
+#define DPCS_BASE__INST4_SEG0 0
+#define DPCS_BASE__INST4_SEG1 0
+#define DPCS_BASE__INST4_SEG2 0
+#define DPCS_BASE__INST4_SEG3 0
+#define DPCS_BASE__INST4_SEG4 0
+#define DPCS_BASE__INST4_SEG5 0
+
+#define DPCS_BASE__INST5_SEG0 0
+#define DPCS_BASE__INST5_SEG1 0
+#define DPCS_BASE__INST5_SEG2 0
+#define DPCS_BASE__INST5_SEG3 0
+#define DPCS_BASE__INST5_SEG4 0
+#define DPCS_BASE__INST5_SEG5 0
+
+#define DPCS_BASE__INST6_SEG0 0
+#define DPCS_BASE__INST6_SEG1 0
+#define DPCS_BASE__INST6_SEG2 0
+#define DPCS_BASE__INST6_SEG3 0
+#define DPCS_BASE__INST6_SEG4 0
+#define DPCS_BASE__INST6_SEG5 0
+
+#define DPCS_BASE__INST7_SEG0 0
+#define DPCS_BASE__INST7_SEG1 0
+#define DPCS_BASE__INST7_SEG2 0
+#define DPCS_BASE__INST7_SEG3 0
+#define DPCS_BASE__INST7_SEG4 0
+#define DPCS_BASE__INST7_SEG5 0
+
+#define FCH_BASE__INST0_SEG0 0x0240C000
+#define FCH_BASE__INST0_SEG1 0x00B40000
+#define FCH_BASE__INST0_SEG2 0x11000000
+#define FCH_BASE__INST0_SEG3 0
+#define FCH_BASE__INST0_SEG4 0
+#define FCH_BASE__INST0_SEG5 0
+
+#define FCH_BASE__INST1_SEG0 0
+#define FCH_BASE__INST1_SEG1 0
+#define FCH_BASE__INST1_SEG2 0
+#define FCH_BASE__INST1_SEG3 0
+#define FCH_BASE__INST1_SEG4 0
+#define FCH_BASE__INST1_SEG5 0
+
+#define FCH_BASE__INST2_SEG0 0
+#define FCH_BASE__INST2_SEG1 0
+#define FCH_BASE__INST2_SEG2 0
+#define FCH_BASE__INST2_SEG3 0
+#define FCH_BASE__INST2_SEG4 0
+#define FCH_BASE__INST2_SEG5 0
+
+#define FCH_BASE__INST3_SEG0 0
+#define FCH_BASE__INST3_SEG1 0
+#define FCH_BASE__INST3_SEG2 0
+#define FCH_BASE__INST3_SEG3 0
+#define FCH_BASE__INST3_SEG4 0
+#define FCH_BASE__INST3_SEG5 0
+
+#define FCH_BASE__INST4_SEG0 0
+#define FCH_BASE__INST4_SEG1 0
+#define FCH_BASE__INST4_SEG2 0
+#define FCH_BASE__INST4_SEG3 0
+#define FCH_BASE__INST4_SEG4 0
+#define FCH_BASE__INST4_SEG5 0
+
+#define FCH_BASE__INST5_SEG0 0
+#define FCH_BASE__INST5_SEG1 0
+#define FCH_BASE__INST5_SEG2 0
+#define FCH_BASE__INST5_SEG3 0
+#define FCH_BASE__INST5_SEG4 0
+#define FCH_BASE__INST5_SEG5 0
+
+#define FCH_BASE__INST6_SEG0 0
+#define FCH_BASE__INST6_SEG1 0
+#define FCH_BASE__INST6_SEG2 0
+#define FCH_BASE__INST6_SEG3 0
+#define FCH_BASE__INST6_SEG4 0
+#define FCH_BASE__INST6_SEG5 0
+
+#define FCH_BASE__INST7_SEG0 0
+#define FCH_BASE__INST7_SEG1 0
+#define FCH_BASE__INST7_SEG2 0
+#define FCH_BASE__INST7_SEG3 0
+#define FCH_BASE__INST7_SEG4 0
+#define FCH_BASE__INST7_SEG5 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+#define FUSE_BASE__INST0_SEG5 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+#define FUSE_BASE__INST1_SEG5 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+#define FUSE_BASE__INST2_SEG5 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+#define FUSE_BASE__INST3_SEG5 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+#define FUSE_BASE__INST4_SEG5 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+#define FUSE_BASE__INST5_SEG5 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+#define FUSE_BASE__INST6_SEG5 0
+
+#define FUSE_BASE__INST7_SEG0 0
+#define FUSE_BASE__INST7_SEG1 0
+#define FUSE_BASE__INST7_SEG2 0
+#define FUSE_BASE__INST7_SEG3 0
+#define FUSE_BASE__INST7_SEG4 0
+#define FUSE_BASE__INST7_SEG5 0
+
+#define GC_BASE__INST0_SEG0 0x00001260
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x02402C00
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+#define GC_BASE__INST0_SEG5 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+#define GC_BASE__INST1_SEG5 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+#define GC_BASE__INST2_SEG5 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+#define GC_BASE__INST3_SEG5 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+#define GC_BASE__INST4_SEG5 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+#define GC_BASE__INST5_SEG5 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+#define GC_BASE__INST6_SEG5 0
+
+#define GC_BASE__INST7_SEG0 0
+#define GC_BASE__INST7_SEG1 0
+#define GC_BASE__INST7_SEG2 0
+#define GC_BASE__INST7_SEG3 0
+#define GC_BASE__INST7_SEG4 0
+#define GC_BASE__INST7_SEG5 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+#define HDP_BASE__INST0_SEG5 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+#define HDP_BASE__INST1_SEG5 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+#define HDP_BASE__INST2_SEG5 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+#define HDP_BASE__INST3_SEG5 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+#define HDP_BASE__INST4_SEG5 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+#define HDP_BASE__INST5_SEG5 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+#define HDP_BASE__INST6_SEG5 0
+
+#define HDP_BASE__INST7_SEG0 0
+#define HDP_BASE__INST7_SEG1 0
+#define HDP_BASE__INST7_SEG2 0
+#define HDP_BASE__INST7_SEG3 0
+#define HDP_BASE__INST7_SEG4 0
+#define HDP_BASE__INST7_SEG5 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0x0240B000
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+#define ISP_BASE__INST0_SEG5 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+#define ISP_BASE__INST1_SEG5 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+#define ISP_BASE__INST2_SEG5 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+#define ISP_BASE__INST3_SEG5 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+#define ISP_BASE__INST4_SEG5 0
+
+#define ISP_BASE__INST5_SEG0 0
+#define ISP_BASE__INST5_SEG1 0
+#define ISP_BASE__INST5_SEG2 0
+#define ISP_BASE__INST5_SEG3 0
+#define ISP_BASE__INST5_SEG4 0
+#define ISP_BASE__INST5_SEG5 0
+
+#define ISP_BASE__INST6_SEG0 0
+#define ISP_BASE__INST6_SEG1 0
+#define ISP_BASE__INST6_SEG2 0
+#define ISP_BASE__INST6_SEG3 0
+#define ISP_BASE__INST6_SEG4 0
+#define ISP_BASE__INST6_SEG5 0
+
+#define ISP_BASE__INST7_SEG0 0
+#define ISP_BASE__INST7_SEG1 0
+#define ISP_BASE__INST7_SEG2 0
+#define ISP_BASE__INST7_SEG3 0
+#define ISP_BASE__INST7_SEG4 0
+#define ISP_BASE__INST7_SEG5 0
+
+#define MMHUB_BASE__INST0_SEG0 0x00013200
+#define MMHUB_BASE__INST0_SEG1 0x0001A000
+#define MMHUB_BASE__INST0_SEG2 0x02408800
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+#define MMHUB_BASE__INST0_SEG5 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+#define MMHUB_BASE__INST1_SEG5 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+#define MMHUB_BASE__INST2_SEG5 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+#define MMHUB_BASE__INST3_SEG5 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+#define MMHUB_BASE__INST4_SEG5 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+#define MMHUB_BASE__INST5_SEG5 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+#define MMHUB_BASE__INST6_SEG5 0
+
+#define MMHUB_BASE__INST7_SEG0 0
+#define MMHUB_BASE__INST7_SEG1 0
+#define MMHUB_BASE__INST7_SEG2 0
+#define MMHUB_BASE__INST7_SEG3 0
+#define MMHUB_BASE__INST7_SEG4 0
+#define MMHUB_BASE__INST7_SEG5 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x0243FC00
+#define MP0_BASE__INST0_SEG2 0x00DC0000
+#define MP0_BASE__INST0_SEG3 0x00E00000
+#define MP0_BASE__INST0_SEG4 0x00E40000
+#define MP0_BASE__INST0_SEG5 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+#define MP0_BASE__INST1_SEG5 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+#define MP0_BASE__INST2_SEG5 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+#define MP0_BASE__INST3_SEG5 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+#define MP0_BASE__INST4_SEG5 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+#define MP0_BASE__INST5_SEG5 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+#define MP0_BASE__INST6_SEG5 0
+
+#define MP0_BASE__INST7_SEG0 0
+#define MP0_BASE__INST7_SEG1 0
+#define MP0_BASE__INST7_SEG2 0
+#define MP0_BASE__INST7_SEG3 0
+#define MP0_BASE__INST7_SEG4 0
+#define MP0_BASE__INST7_SEG5 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x0243FC00
+#define MP1_BASE__INST0_SEG2 0x00DC0000
+#define MP1_BASE__INST0_SEG3 0x00E00000
+#define MP1_BASE__INST0_SEG4 0x00E40000
+#define MP1_BASE__INST0_SEG5 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+#define MP1_BASE__INST1_SEG5 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+#define MP1_BASE__INST2_SEG5 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+#define MP1_BASE__INST3_SEG5 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+#define MP1_BASE__INST4_SEG5 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+#define MP1_BASE__INST5_SEG5 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+#define MP1_BASE__INST6_SEG5 0
+
+#define MP1_BASE__INST7_SEG0 0
+#define MP1_BASE__INST7_SEG1 0
+#define MP1_BASE__INST7_SEG2 0
+#define MP1_BASE__INST7_SEG3 0
+#define MP1_BASE__INST7_SEG4 0
+#define MP1_BASE__INST7_SEG5 0
+
+#define MP2_BASE__INST0_SEG0 0x00016400
+#define MP2_BASE__INST0_SEG1 0x02400800
+#define MP2_BASE__INST0_SEG2 0x00F40000
+#define MP2_BASE__INST0_SEG3 0x00F80000
+#define MP2_BASE__INST0_SEG4 0x00FC0000
+#define MP2_BASE__INST0_SEG5 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+#define MP2_BASE__INST1_SEG5 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+#define MP2_BASE__INST2_SEG5 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+#define MP2_BASE__INST3_SEG5 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+#define MP2_BASE__INST4_SEG5 0
+
+#define MP2_BASE__INST5_SEG0 0
+#define MP2_BASE__INST5_SEG1 0
+#define MP2_BASE__INST5_SEG2 0
+#define MP2_BASE__INST5_SEG3 0
+#define MP2_BASE__INST5_SEG4 0
+#define MP2_BASE__INST5_SEG5 0
+
+#define MP2_BASE__INST6_SEG0 0
+#define MP2_BASE__INST6_SEG1 0
+#define MP2_BASE__INST6_SEG2 0
+#define MP2_BASE__INST6_SEG3 0
+#define MP2_BASE__INST6_SEG4 0
+#define MP2_BASE__INST6_SEG5 0
+
+#define MP2_BASE__INST7_SEG0 0
+#define MP2_BASE__INST7_SEG1 0
+#define MP2_BASE__INST7_SEG2 0
+#define MP2_BASE__INST7_SEG3 0
+#define MP2_BASE__INST7_SEG4 0
+#define MP2_BASE__INST7_SEG5 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+#define NBIO_BASE__INST0_SEG5 0x04040000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+#define NBIO_BASE__INST1_SEG5 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+#define NBIO_BASE__INST2_SEG5 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+#define NBIO_BASE__INST3_SEG5 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+#define NBIO_BASE__INST4_SEG5 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+#define NBIO_BASE__INST5_SEG5 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+#define NBIO_BASE__INST6_SEG5 0
+
+#define NBIO_BASE__INST7_SEG0 0
+#define NBIO_BASE__INST7_SEG1 0
+#define NBIO_BASE__INST7_SEG2 0
+#define NBIO_BASE__INST7_SEG3 0
+#define NBIO_BASE__INST7_SEG4 0
+#define NBIO_BASE__INST7_SEG5 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+#define OSSSYS_BASE__INST0_SEG5 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+#define OSSSYS_BASE__INST1_SEG5 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+#define OSSSYS_BASE__INST2_SEG5 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+#define OSSSYS_BASE__INST3_SEG5 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+#define OSSSYS_BASE__INST4_SEG5 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+#define OSSSYS_BASE__INST5_SEG5 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+#define OSSSYS_BASE__INST6_SEG5 0
+
+#define OSSSYS_BASE__INST7_SEG0 0
+#define OSSSYS_BASE__INST7_SEG1 0
+#define OSSSYS_BASE__INST7_SEG2 0
+#define OSSSYS_BASE__INST7_SEG3 0
+#define OSSSYS_BASE__INST7_SEG4 0
+#define OSSSYS_BASE__INST7_SEG5 0
+
+#define PCIE0_BASE__INST0_SEG0 0x00000000
+#define PCIE0_BASE__INST0_SEG1 0x00000014
+#define PCIE0_BASE__INST0_SEG2 0x00000D20
+#define PCIE0_BASE__INST0_SEG3 0x00010400
+#define PCIE0_BASE__INST0_SEG4 0x0241B000
+#define PCIE0_BASE__INST0_SEG5 0x04040000
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+#define PCIE0_BASE__INST1_SEG5 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+#define PCIE0_BASE__INST2_SEG5 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+#define PCIE0_BASE__INST3_SEG5 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+#define PCIE0_BASE__INST4_SEG5 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+#define PCIE0_BASE__INST5_SEG5 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+#define PCIE0_BASE__INST6_SEG5 0
+
+#define PCIE0_BASE__INST7_SEG0 0
+#define PCIE0_BASE__INST7_SEG1 0
+#define PCIE0_BASE__INST7_SEG2 0
+#define PCIE0_BASE__INST7_SEG3 0
+#define PCIE0_BASE__INST7_SEG4 0
+#define PCIE0_BASE__INST7_SEG5 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x02401000
+#define SMUIO_BASE__INST0_SEG3 0x00440000
+#define SMUIO_BASE__INST0_SEG4 0
+#define SMUIO_BASE__INST0_SEG5 0
+
+#define SMUIO_BASE__INST1_SEG0 0x0001BC00
+#define SMUIO_BASE__INST1_SEG1 0x0242D400
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+#define SMUIO_BASE__INST1_SEG5 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+#define SMUIO_BASE__INST2_SEG5 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+#define SMUIO_BASE__INST3_SEG5 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+#define SMUIO_BASE__INST4_SEG5 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+#define SMUIO_BASE__INST5_SEG5 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+#define SMUIO_BASE__INST6_SEG5 0
+
+#define SMUIO_BASE__INST7_SEG0 0
+#define SMUIO_BASE__INST7_SEG1 0
+#define SMUIO_BASE__INST7_SEG2 0
+#define SMUIO_BASE__INST7_SEG3 0
+#define SMUIO_BASE__INST7_SEG4 0
+#define SMUIO_BASE__INST7_SEG5 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+#define THM_BASE__INST0_SEG5 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+#define THM_BASE__INST1_SEG5 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+#define THM_BASE__INST2_SEG5 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+#define THM_BASE__INST3_SEG5 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+#define THM_BASE__INST4_SEG5 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+#define THM_BASE__INST5_SEG5 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+#define THM_BASE__INST6_SEG5 0
+
+#define THM_BASE__INST7_SEG0 0
+#define THM_BASE__INST7_SEG1 0
+#define THM_BASE__INST7_SEG2 0
+#define THM_BASE__INST7_SEG3 0
+#define THM_BASE__INST7_SEG4 0
+#define THM_BASE__INST7_SEG5 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x02425800
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+#define UMC_BASE__INST0_SEG5 0
+
+#define UMC_BASE__INST1_SEG0 0x00054000
+#define UMC_BASE__INST1_SEG1 0x02425C00
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+#define UMC_BASE__INST1_SEG5 0
+
+#define UMC_BASE__INST2_SEG0 0x00094000
+#define UMC_BASE__INST2_SEG1 0x02426000
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+#define UMC_BASE__INST2_SEG5 0
+
+#define UMC_BASE__INST3_SEG0 0x000D4000
+#define UMC_BASE__INST3_SEG1 0x02426400
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+#define UMC_BASE__INST3_SEG5 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+#define UMC_BASE__INST4_SEG5 0
+
+#define UMC_BASE__INST5_SEG0 0
+#define UMC_BASE__INST5_SEG1 0
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+#define UMC_BASE__INST5_SEG5 0
+
+#define UMC_BASE__INST6_SEG0 0
+#define UMC_BASE__INST6_SEG1 0
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+#define UMC_BASE__INST6_SEG5 0
+
+#define UMC_BASE__INST7_SEG0 0
+#define UMC_BASE__INST7_SEG1 0
+#define UMC_BASE__INST7_SEG2 0
+#define UMC_BASE__INST7_SEG3 0
+#define UMC_BASE__INST7_SEG4 0
+#define UMC_BASE__INST7_SEG5 0
+
+#define USB_BASE__INST0_SEG0 0x0242A800
+#define USB_BASE__INST0_SEG1 0x05B00000
+#define USB_BASE__INST0_SEG2 0
+#define USB_BASE__INST0_SEG3 0
+#define USB_BASE__INST0_SEG4 0
+#define USB_BASE__INST0_SEG5 0
+
+#define USB_BASE__INST1_SEG0 0x0242AC00
+#define USB_BASE__INST1_SEG1 0x05B80000
+#define USB_BASE__INST1_SEG2 0
+#define USB_BASE__INST1_SEG3 0
+#define USB_BASE__INST1_SEG4 0
+#define USB_BASE__INST1_SEG5 0
+
+#define USB_BASE__INST2_SEG0 0x0242B000
+#define USB_BASE__INST2_SEG1 0x05C00000
+#define USB_BASE__INST2_SEG2 0
+#define USB_BASE__INST2_SEG3 0
+#define USB_BASE__INST2_SEG4 0
+#define USB_BASE__INST2_SEG5 0
+
+#define USB_BASE__INST3_SEG0 0
+#define USB_BASE__INST3_SEG1 0
+#define USB_BASE__INST3_SEG2 0
+#define USB_BASE__INST3_SEG3 0
+#define USB_BASE__INST3_SEG4 0
+#define USB_BASE__INST3_SEG5 0
+
+#define USB_BASE__INST4_SEG0 0
+#define USB_BASE__INST4_SEG1 0
+#define USB_BASE__INST4_SEG2 0
+#define USB_BASE__INST4_SEG3 0
+#define USB_BASE__INST4_SEG4 0
+#define USB_BASE__INST4_SEG5 0
+
+#define USB_BASE__INST5_SEG0 0
+#define USB_BASE__INST5_SEG1 0
+#define USB_BASE__INST5_SEG2 0
+#define USB_BASE__INST5_SEG3 0
+#define USB_BASE__INST5_SEG4 0
+#define USB_BASE__INST5_SEG5 0
+
+#define USB_BASE__INST6_SEG0 0
+#define USB_BASE__INST6_SEG1 0
+#define USB_BASE__INST6_SEG2 0
+#define USB_BASE__INST6_SEG3 0
+#define USB_BASE__INST6_SEG4 0
+#define USB_BASE__INST6_SEG5 0
+
+#define USB_BASE__INST7_SEG0 0
+#define USB_BASE__INST7_SEG1 0
+#define USB_BASE__INST7_SEG2 0
+#define USB_BASE__INST7_SEG3 0
+#define USB_BASE__INST7_SEG4 0
+#define USB_BASE__INST7_SEG5 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+#define VCN_BASE__INST0_SEG5 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+#define VCN_BASE__INST1_SEG5 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+#define VCN_BASE__INST2_SEG5 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+#define VCN_BASE__INST3_SEG5 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+#define VCN_BASE__INST4_SEG5 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+#define VCN_BASE__INST5_SEG5 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+#define VCN_BASE__INST6_SEG5 0
+
+#define VCN_BASE__INST7_SEG0 0
+#define VCN_BASE__INST7_SEG1 0
+#define VCN_BASE__INST7_SEG2 0
+#define VCN_BASE__INST7_SEG3 0
+#define VCN_BASE__INST7_SEG4 0
+#define VCN_BASE__INST7_SEG5 0
+
+#endif
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
@ 2020-09-28 20:48 ` Luben Tuikov
2020-09-29 14:57 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 20:48 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> This patch adds vangogh_reg_base_init function to init the register base for
> van gogh.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
> .../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
> 4 files changed, 1569 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 39976c7b100c..7866e4666a43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
> vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
> - arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
> + arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
> index aeef50a6a54b..8a3bf476b18f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.h
> @@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
> int navi14_reg_base_init(struct amdgpu_device *adev);
> int navi12_reg_base_init(struct amdgpu_device *adev);
> int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
> +int vangogh_reg_base_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> new file mode 100644
> index 000000000000..4c6c3b415e7b
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> @@ -0,0 +1,51 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#include "amdgpu.h"
> +#include "nv.h"
> +
> +#include "soc15_common.h"
> +#include "soc15_hw_ip.h"
> +#include "vangogh_ip_offset.h"
> +
> +int vangogh_reg_base_init(struct amdgpu_device *adev)
> +{
> + /* HW has more IP blocks, only initialized the blocke needed by driver */
> + uint32_t i;
> + for (i = 0 ; i < MAX_INSTANCE ; ++i) {
> + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
> + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
> + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
> + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
> + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
> + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
> + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
> + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
> + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
> + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
I'd align the equality sign for presentation.
> + }
> + return 0;
> +}
This function should be "void", else the compiler will throw a warning
when you compile nv.c.
> diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> new file mode 100644
> index 000000000000..2875574b060e
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> @@ -0,0 +1,1516 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __VANGOGH_IP_OFFSET_H__
> +#define __VANGOGH_IP_OFFSET_H__
> +
> +#define MAX_INSTANCE 8
> +#define MAX_SEGMENT 6
No. No "max". Use "num" instead, as:
#define NUM_INSTANCE 8
#define NUM_SEGMENT 6
To mean, the _number_ of instances and the _number_ of
segments. (Their count is a number.)
A "maximum" (similarly "minimum") value is an _attainable_ value,
i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
and thus max instance can never be attained.
It is the count, the number of instances (segments, wlg),
not the maximum instance. The maximum instance is 7,
the minimum instance is 0. Similarly for segments.
> +
> +
> +struct IP_BASE_INSTANCE
> +{
> + unsigned int segment[MAX_SEGMENT];
> +};
So, here if you used NUM_SEGMENT, it is very clear
what is intended: an array of number of segments,
i.e. their count, whose array index would be 0 to
NUM_SEGMENTS-1.
Similarly for "instance" below.
Regards,
Luben
> +
> +struct IP_BASE
> +{
> + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> +};
> +
> +
> +static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
> + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
> + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
> + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
> + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
> + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
> + { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
> + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
> + { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
> + { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
> + { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
> + { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
> + { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
> + { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +
> +
> +#define ACP_BASE__INST0_SEG0 0x02403800
> +#define ACP_BASE__INST0_SEG1 0x00480000
> +#define ACP_BASE__INST0_SEG2 0
> +#define ACP_BASE__INST0_SEG3 0
> +#define ACP_BASE__INST0_SEG4 0
> +#define ACP_BASE__INST0_SEG5 0
> +
> +#define ACP_BASE__INST1_SEG0 0
> +#define ACP_BASE__INST1_SEG1 0
> +#define ACP_BASE__INST1_SEG2 0
> +#define ACP_BASE__INST1_SEG3 0
> +#define ACP_BASE__INST1_SEG4 0
> +#define ACP_BASE__INST1_SEG5 0
> +
> +#define ACP_BASE__INST2_SEG0 0
> +#define ACP_BASE__INST2_SEG1 0
> +#define ACP_BASE__INST2_SEG2 0
> +#define ACP_BASE__INST2_SEG3 0
> +#define ACP_BASE__INST2_SEG4 0
> +#define ACP_BASE__INST2_SEG5 0
> +
> +#define ACP_BASE__INST3_SEG0 0
> +#define ACP_BASE__INST3_SEG1 0
> +#define ACP_BASE__INST3_SEG2 0
> +#define ACP_BASE__INST3_SEG3 0
> +#define ACP_BASE__INST3_SEG4 0
> +#define ACP_BASE__INST3_SEG5 0
> +
> +#define ACP_BASE__INST4_SEG0 0
> +#define ACP_BASE__INST4_SEG1 0
> +#define ACP_BASE__INST4_SEG2 0
> +#define ACP_BASE__INST4_SEG3 0
> +#define ACP_BASE__INST4_SEG4 0
> +#define ACP_BASE__INST4_SEG5 0
> +
> +#define ACP_BASE__INST5_SEG0 0
> +#define ACP_BASE__INST5_SEG1 0
> +#define ACP_BASE__INST5_SEG2 0
> +#define ACP_BASE__INST5_SEG3 0
> +#define ACP_BASE__INST5_SEG4 0
> +#define ACP_BASE__INST5_SEG5 0
> +
> +#define ACP_BASE__INST6_SEG0 0
> +#define ACP_BASE__INST6_SEG1 0
> +#define ACP_BASE__INST6_SEG2 0
> +#define ACP_BASE__INST6_SEG3 0
> +#define ACP_BASE__INST6_SEG4 0
> +#define ACP_BASE__INST6_SEG5 0
> +
> +#define ACP_BASE__INST7_SEG0 0
> +#define ACP_BASE__INST7_SEG1 0
> +#define ACP_BASE__INST7_SEG2 0
> +#define ACP_BASE__INST7_SEG3 0
> +#define ACP_BASE__INST7_SEG4 0
> +#define ACP_BASE__INST7_SEG5 0
> +
> +#define ATHUB_BASE__INST0_SEG0 0x00000C00
> +#define ATHUB_BASE__INST0_SEG1 0x00013300
> +#define ATHUB_BASE__INST0_SEG2 0x02408C00
> +#define ATHUB_BASE__INST0_SEG3 0
> +#define ATHUB_BASE__INST0_SEG4 0
> +#define ATHUB_BASE__INST0_SEG5 0
> +
> +#define ATHUB_BASE__INST1_SEG0 0
> +#define ATHUB_BASE__INST1_SEG1 0
> +#define ATHUB_BASE__INST1_SEG2 0
> +#define ATHUB_BASE__INST1_SEG3 0
> +#define ATHUB_BASE__INST1_SEG4 0
> +#define ATHUB_BASE__INST1_SEG5 0
> +
> +#define ATHUB_BASE__INST2_SEG0 0
> +#define ATHUB_BASE__INST2_SEG1 0
> +#define ATHUB_BASE__INST2_SEG2 0
> +#define ATHUB_BASE__INST2_SEG3 0
> +#define ATHUB_BASE__INST2_SEG4 0
> +#define ATHUB_BASE__INST2_SEG5 0
> +
> +#define ATHUB_BASE__INST3_SEG0 0
> +#define ATHUB_BASE__INST3_SEG1 0
> +#define ATHUB_BASE__INST3_SEG2 0
> +#define ATHUB_BASE__INST3_SEG3 0
> +#define ATHUB_BASE__INST3_SEG4 0
> +#define ATHUB_BASE__INST3_SEG5 0
> +
> +#define ATHUB_BASE__INST4_SEG0 0
> +#define ATHUB_BASE__INST4_SEG1 0
> +#define ATHUB_BASE__INST4_SEG2 0
> +#define ATHUB_BASE__INST4_SEG3 0
> +#define ATHUB_BASE__INST4_SEG4 0
> +#define ATHUB_BASE__INST4_SEG5 0
> +
> +#define ATHUB_BASE__INST5_SEG0 0
> +#define ATHUB_BASE__INST5_SEG1 0
> +#define ATHUB_BASE__INST5_SEG2 0
> +#define ATHUB_BASE__INST5_SEG3 0
> +#define ATHUB_BASE__INST5_SEG4 0
> +#define ATHUB_BASE__INST5_SEG5 0
> +
> +#define ATHUB_BASE__INST6_SEG0 0
> +#define ATHUB_BASE__INST6_SEG1 0
> +#define ATHUB_BASE__INST6_SEG2 0
> +#define ATHUB_BASE__INST6_SEG3 0
> +#define ATHUB_BASE__INST6_SEG4 0
> +#define ATHUB_BASE__INST6_SEG5 0
> +
> +#define ATHUB_BASE__INST7_SEG0 0
> +#define ATHUB_BASE__INST7_SEG1 0
> +#define ATHUB_BASE__INST7_SEG2 0
> +#define ATHUB_BASE__INST7_SEG3 0
> +#define ATHUB_BASE__INST7_SEG4 0
> +#define ATHUB_BASE__INST7_SEG5 0
> +
> +#define CLK_BASE__INST0_SEG0 0x00016C00
> +#define CLK_BASE__INST0_SEG1 0x02401800
> +#define CLK_BASE__INST0_SEG2 0
> +#define CLK_BASE__INST0_SEG3 0
> +#define CLK_BASE__INST0_SEG4 0
> +#define CLK_BASE__INST0_SEG5 0
> +
> +#define CLK_BASE__INST1_SEG0 0x00016E00
> +#define CLK_BASE__INST1_SEG1 0x02401C00
> +#define CLK_BASE__INST1_SEG2 0
> +#define CLK_BASE__INST1_SEG3 0
> +#define CLK_BASE__INST1_SEG4 0
> +#define CLK_BASE__INST1_SEG5 0
> +
> +#define CLK_BASE__INST2_SEG0 0x00017000
> +#define CLK_BASE__INST2_SEG1 0x02402000
> +#define CLK_BASE__INST2_SEG2 0
> +#define CLK_BASE__INST2_SEG3 0
> +#define CLK_BASE__INST2_SEG4 0
> +#define CLK_BASE__INST2_SEG5 0
> +
> +#define CLK_BASE__INST3_SEG0 0x00017200
> +#define CLK_BASE__INST3_SEG1 0x02402400
> +#define CLK_BASE__INST3_SEG2 0
> +#define CLK_BASE__INST3_SEG3 0
> +#define CLK_BASE__INST3_SEG4 0
> +#define CLK_BASE__INST3_SEG5 0
> +
> +#define CLK_BASE__INST4_SEG0 0x0001B000
> +#define CLK_BASE__INST4_SEG1 0x0242D800
> +#define CLK_BASE__INST4_SEG2 0
> +#define CLK_BASE__INST4_SEG3 0
> +#define CLK_BASE__INST4_SEG4 0
> +#define CLK_BASE__INST4_SEG5 0
> +
> +#define CLK_BASE__INST5_SEG0 0x0001B200
> +#define CLK_BASE__INST5_SEG1 0x0242DC00
> +#define CLK_BASE__INST5_SEG2 0
> +#define CLK_BASE__INST5_SEG3 0
> +#define CLK_BASE__INST5_SEG4 0
> +#define CLK_BASE__INST5_SEG5 0
> +
> +#define CLK_BASE__INST6_SEG0 0x0001B400
> +#define CLK_BASE__INST6_SEG1 0x0242E000
> +#define CLK_BASE__INST6_SEG2 0
> +#define CLK_BASE__INST6_SEG3 0
> +#define CLK_BASE__INST6_SEG4 0
> +#define CLK_BASE__INST6_SEG5 0
> +
> +#define CLK_BASE__INST7_SEG0 0x00017E00
> +#define CLK_BASE__INST7_SEG1 0x0240BC00
> +#define CLK_BASE__INST7_SEG2 0
> +#define CLK_BASE__INST7_SEG3 0
> +#define CLK_BASE__INST7_SEG4 0
> +#define CLK_BASE__INST7_SEG5 0
> +
> +#define DF_BASE__INST0_SEG0 0x00007000
> +#define DF_BASE__INST0_SEG1 0x0240B800
> +#define DF_BASE__INST0_SEG2 0
> +#define DF_BASE__INST0_SEG3 0
> +#define DF_BASE__INST0_SEG4 0
> +#define DF_BASE__INST0_SEG5 0
> +
> +#define DF_BASE__INST1_SEG0 0
> +#define DF_BASE__INST1_SEG1 0
> +#define DF_BASE__INST1_SEG2 0
> +#define DF_BASE__INST1_SEG3 0
> +#define DF_BASE__INST1_SEG4 0
> +#define DF_BASE__INST1_SEG5 0
> +
> +#define DF_BASE__INST2_SEG0 0
> +#define DF_BASE__INST2_SEG1 0
> +#define DF_BASE__INST2_SEG2 0
> +#define DF_BASE__INST2_SEG3 0
> +#define DF_BASE__INST2_SEG4 0
> +#define DF_BASE__INST2_SEG5 0
> +
> +#define DF_BASE__INST3_SEG0 0
> +#define DF_BASE__INST3_SEG1 0
> +#define DF_BASE__INST3_SEG2 0
> +#define DF_BASE__INST3_SEG3 0
> +#define DF_BASE__INST3_SEG4 0
> +#define DF_BASE__INST3_SEG5 0
> +
> +#define DF_BASE__INST4_SEG0 0
> +#define DF_BASE__INST4_SEG1 0
> +#define DF_BASE__INST4_SEG2 0
> +#define DF_BASE__INST4_SEG3 0
> +#define DF_BASE__INST4_SEG4 0
> +#define DF_BASE__INST4_SEG5 0
> +
> +#define DF_BASE__INST5_SEG0 0
> +#define DF_BASE__INST5_SEG1 0
> +#define DF_BASE__INST5_SEG2 0
> +#define DF_BASE__INST5_SEG3 0
> +#define DF_BASE__INST5_SEG4 0
> +#define DF_BASE__INST5_SEG5 0
> +
> +#define DF_BASE__INST6_SEG0 0
> +#define DF_BASE__INST6_SEG1 0
> +#define DF_BASE__INST6_SEG2 0
> +#define DF_BASE__INST6_SEG3 0
> +#define DF_BASE__INST6_SEG4 0
> +#define DF_BASE__INST6_SEG5 0
> +
> +#define DF_BASE__INST7_SEG0 0
> +#define DF_BASE__INST7_SEG1 0
> +#define DF_BASE__INST7_SEG2 0
> +#define DF_BASE__INST7_SEG3 0
> +#define DF_BASE__INST7_SEG4 0
> +#define DF_BASE__INST7_SEG5 0
> +
> +#define DCN_BASE__INST0_SEG0 0x00000012
> +#define DCN_BASE__INST0_SEG1 0x000000C0
> +#define DCN_BASE__INST0_SEG2 0x000034C0
> +#define DCN_BASE__INST0_SEG3 0x00009000
> +#define DCN_BASE__INST0_SEG4 0x02403C00
> +#define DCN_BASE__INST0_SEG5 0
> +
> +#define DCN_BASE__INST1_SEG0 0
> +#define DCN_BASE__INST1_SEG1 0
> +#define DCN_BASE__INST1_SEG2 0
> +#define DCN_BASE__INST1_SEG3 0
> +#define DCN_BASE__INST1_SEG4 0
> +#define DCN_BASE__INST1_SEG5 0
> +
> +#define DCN_BASE__INST2_SEG0 0
> +#define DCN_BASE__INST2_SEG1 0
> +#define DCN_BASE__INST2_SEG2 0
> +#define DCN_BASE__INST2_SEG3 0
> +#define DCN_BASE__INST2_SEG4 0
> +#define DCN_BASE__INST2_SEG5 0
> +
> +#define DCN_BASE__INST3_SEG0 0
> +#define DCN_BASE__INST3_SEG1 0
> +#define DCN_BASE__INST3_SEG2 0
> +#define DCN_BASE__INST3_SEG3 0
> +#define DCN_BASE__INST3_SEG4 0
> +#define DCN_BASE__INST3_SEG5 0
> +
> +#define DCN_BASE__INST4_SEG0 0
> +#define DCN_BASE__INST4_SEG1 0
> +#define DCN_BASE__INST4_SEG2 0
> +#define DCN_BASE__INST4_SEG3 0
> +#define DCN_BASE__INST4_SEG4 0
> +#define DCN_BASE__INST4_SEG5 0
> +
> +#define DCN_BASE__INST5_SEG0 0
> +#define DCN_BASE__INST5_SEG1 0
> +#define DCN_BASE__INST5_SEG2 0
> +#define DCN_BASE__INST5_SEG3 0
> +#define DCN_BASE__INST5_SEG4 0
> +#define DCN_BASE__INST5_SEG5 0
> +
> +#define DCN_BASE__INST6_SEG0 0
> +#define DCN_BASE__INST6_SEG1 0
> +#define DCN_BASE__INST6_SEG2 0
> +#define DCN_BASE__INST6_SEG3 0
> +#define DCN_BASE__INST6_SEG4 0
> +#define DCN_BASE__INST6_SEG5 0
> +
> +#define DCN_BASE__INST7_SEG0 0
> +#define DCN_BASE__INST7_SEG1 0
> +#define DCN_BASE__INST7_SEG2 0
> +#define DCN_BASE__INST7_SEG3 0
> +#define DCN_BASE__INST7_SEG4 0
> +#define DCN_BASE__INST7_SEG5 0
> +
> +#define DPCS_BASE__INST0_SEG0 0x00000012
> +#define DPCS_BASE__INST0_SEG1 0x000000C0
> +#define DPCS_BASE__INST0_SEG2 0x000034C0
> +#define DPCS_BASE__INST0_SEG3 0x00009000
> +#define DPCS_BASE__INST0_SEG4 0x02403C00
> +#define DPCS_BASE__INST0_SEG5 0
> +
> +#define DPCS_BASE__INST1_SEG0 0
> +#define DPCS_BASE__INST1_SEG1 0
> +#define DPCS_BASE__INST1_SEG2 0
> +#define DPCS_BASE__INST1_SEG3 0
> +#define DPCS_BASE__INST1_SEG4 0
> +#define DPCS_BASE__INST1_SEG5 0
> +
> +#define DPCS_BASE__INST2_SEG0 0
> +#define DPCS_BASE__INST2_SEG1 0
> +#define DPCS_BASE__INST2_SEG2 0
> +#define DPCS_BASE__INST2_SEG3 0
> +#define DPCS_BASE__INST2_SEG4 0
> +#define DPCS_BASE__INST2_SEG5 0
> +
> +#define DPCS_BASE__INST3_SEG0 0
> +#define DPCS_BASE__INST3_SEG1 0
> +#define DPCS_BASE__INST3_SEG2 0
> +#define DPCS_BASE__INST3_SEG3 0
> +#define DPCS_BASE__INST3_SEG4 0
> +#define DPCS_BASE__INST3_SEG5 0
> +
> +#define DPCS_BASE__INST4_SEG0 0
> +#define DPCS_BASE__INST4_SEG1 0
> +#define DPCS_BASE__INST4_SEG2 0
> +#define DPCS_BASE__INST4_SEG3 0
> +#define DPCS_BASE__INST4_SEG4 0
> +#define DPCS_BASE__INST4_SEG5 0
> +
> +#define DPCS_BASE__INST5_SEG0 0
> +#define DPCS_BASE__INST5_SEG1 0
> +#define DPCS_BASE__INST5_SEG2 0
> +#define DPCS_BASE__INST5_SEG3 0
> +#define DPCS_BASE__INST5_SEG4 0
> +#define DPCS_BASE__INST5_SEG5 0
> +
> +#define DPCS_BASE__INST6_SEG0 0
> +#define DPCS_BASE__INST6_SEG1 0
> +#define DPCS_BASE__INST6_SEG2 0
> +#define DPCS_BASE__INST6_SEG3 0
> +#define DPCS_BASE__INST6_SEG4 0
> +#define DPCS_BASE__INST6_SEG5 0
> +
> +#define DPCS_BASE__INST7_SEG0 0
> +#define DPCS_BASE__INST7_SEG1 0
> +#define DPCS_BASE__INST7_SEG2 0
> +#define DPCS_BASE__INST7_SEG3 0
> +#define DPCS_BASE__INST7_SEG4 0
> +#define DPCS_BASE__INST7_SEG5 0
> +
> +#define FCH_BASE__INST0_SEG0 0x0240C000
> +#define FCH_BASE__INST0_SEG1 0x00B40000
> +#define FCH_BASE__INST0_SEG2 0x11000000
> +#define FCH_BASE__INST0_SEG3 0
> +#define FCH_BASE__INST0_SEG4 0
> +#define FCH_BASE__INST0_SEG5 0
> +
> +#define FCH_BASE__INST1_SEG0 0
> +#define FCH_BASE__INST1_SEG1 0
> +#define FCH_BASE__INST1_SEG2 0
> +#define FCH_BASE__INST1_SEG3 0
> +#define FCH_BASE__INST1_SEG4 0
> +#define FCH_BASE__INST1_SEG5 0
> +
> +#define FCH_BASE__INST2_SEG0 0
> +#define FCH_BASE__INST2_SEG1 0
> +#define FCH_BASE__INST2_SEG2 0
> +#define FCH_BASE__INST2_SEG3 0
> +#define FCH_BASE__INST2_SEG4 0
> +#define FCH_BASE__INST2_SEG5 0
> +
> +#define FCH_BASE__INST3_SEG0 0
> +#define FCH_BASE__INST3_SEG1 0
> +#define FCH_BASE__INST3_SEG2 0
> +#define FCH_BASE__INST3_SEG3 0
> +#define FCH_BASE__INST3_SEG4 0
> +#define FCH_BASE__INST3_SEG5 0
> +
> +#define FCH_BASE__INST4_SEG0 0
> +#define FCH_BASE__INST4_SEG1 0
> +#define FCH_BASE__INST4_SEG2 0
> +#define FCH_BASE__INST4_SEG3 0
> +#define FCH_BASE__INST4_SEG4 0
> +#define FCH_BASE__INST4_SEG5 0
> +
> +#define FCH_BASE__INST5_SEG0 0
> +#define FCH_BASE__INST5_SEG1 0
> +#define FCH_BASE__INST5_SEG2 0
> +#define FCH_BASE__INST5_SEG3 0
> +#define FCH_BASE__INST5_SEG4 0
> +#define FCH_BASE__INST5_SEG5 0
> +
> +#define FCH_BASE__INST6_SEG0 0
> +#define FCH_BASE__INST6_SEG1 0
> +#define FCH_BASE__INST6_SEG2 0
> +#define FCH_BASE__INST6_SEG3 0
> +#define FCH_BASE__INST6_SEG4 0
> +#define FCH_BASE__INST6_SEG5 0
> +
> +#define FCH_BASE__INST7_SEG0 0
> +#define FCH_BASE__INST7_SEG1 0
> +#define FCH_BASE__INST7_SEG2 0
> +#define FCH_BASE__INST7_SEG3 0
> +#define FCH_BASE__INST7_SEG4 0
> +#define FCH_BASE__INST7_SEG5 0
> +
> +#define FUSE_BASE__INST0_SEG0 0x00017400
> +#define FUSE_BASE__INST0_SEG1 0x02401400
> +#define FUSE_BASE__INST0_SEG2 0
> +#define FUSE_BASE__INST0_SEG3 0
> +#define FUSE_BASE__INST0_SEG4 0
> +#define FUSE_BASE__INST0_SEG5 0
> +
> +#define FUSE_BASE__INST1_SEG0 0
> +#define FUSE_BASE__INST1_SEG1 0
> +#define FUSE_BASE__INST1_SEG2 0
> +#define FUSE_BASE__INST1_SEG3 0
> +#define FUSE_BASE__INST1_SEG4 0
> +#define FUSE_BASE__INST1_SEG5 0
> +
> +#define FUSE_BASE__INST2_SEG0 0
> +#define FUSE_BASE__INST2_SEG1 0
> +#define FUSE_BASE__INST2_SEG2 0
> +#define FUSE_BASE__INST2_SEG3 0
> +#define FUSE_BASE__INST2_SEG4 0
> +#define FUSE_BASE__INST2_SEG5 0
> +
> +#define FUSE_BASE__INST3_SEG0 0
> +#define FUSE_BASE__INST3_SEG1 0
> +#define FUSE_BASE__INST3_SEG2 0
> +#define FUSE_BASE__INST3_SEG3 0
> +#define FUSE_BASE__INST3_SEG4 0
> +#define FUSE_BASE__INST3_SEG5 0
> +
> +#define FUSE_BASE__INST4_SEG0 0
> +#define FUSE_BASE__INST4_SEG1 0
> +#define FUSE_BASE__INST4_SEG2 0
> +#define FUSE_BASE__INST4_SEG3 0
> +#define FUSE_BASE__INST4_SEG4 0
> +#define FUSE_BASE__INST4_SEG5 0
> +
> +#define FUSE_BASE__INST5_SEG0 0
> +#define FUSE_BASE__INST5_SEG1 0
> +#define FUSE_BASE__INST5_SEG2 0
> +#define FUSE_BASE__INST5_SEG3 0
> +#define FUSE_BASE__INST5_SEG4 0
> +#define FUSE_BASE__INST5_SEG5 0
> +
> +#define FUSE_BASE__INST6_SEG0 0
> +#define FUSE_BASE__INST6_SEG1 0
> +#define FUSE_BASE__INST6_SEG2 0
> +#define FUSE_BASE__INST6_SEG3 0
> +#define FUSE_BASE__INST6_SEG4 0
> +#define FUSE_BASE__INST6_SEG5 0
> +
> +#define FUSE_BASE__INST7_SEG0 0
> +#define FUSE_BASE__INST7_SEG1 0
> +#define FUSE_BASE__INST7_SEG2 0
> +#define FUSE_BASE__INST7_SEG3 0
> +#define FUSE_BASE__INST7_SEG4 0
> +#define FUSE_BASE__INST7_SEG5 0
> +
> +#define GC_BASE__INST0_SEG0 0x00001260
> +#define GC_BASE__INST0_SEG1 0x0000A000
> +#define GC_BASE__INST0_SEG2 0x02402C00
> +#define GC_BASE__INST0_SEG3 0
> +#define GC_BASE__INST0_SEG4 0
> +#define GC_BASE__INST0_SEG5 0
> +
> +#define GC_BASE__INST1_SEG0 0
> +#define GC_BASE__INST1_SEG1 0
> +#define GC_BASE__INST1_SEG2 0
> +#define GC_BASE__INST1_SEG3 0
> +#define GC_BASE__INST1_SEG4 0
> +#define GC_BASE__INST1_SEG5 0
> +
> +#define GC_BASE__INST2_SEG0 0
> +#define GC_BASE__INST2_SEG1 0
> +#define GC_BASE__INST2_SEG2 0
> +#define GC_BASE__INST2_SEG3 0
> +#define GC_BASE__INST2_SEG4 0
> +#define GC_BASE__INST2_SEG5 0
> +
> +#define GC_BASE__INST3_SEG0 0
> +#define GC_BASE__INST3_SEG1 0
> +#define GC_BASE__INST3_SEG2 0
> +#define GC_BASE__INST3_SEG3 0
> +#define GC_BASE__INST3_SEG4 0
> +#define GC_BASE__INST3_SEG5 0
> +
> +#define GC_BASE__INST4_SEG0 0
> +#define GC_BASE__INST4_SEG1 0
> +#define GC_BASE__INST4_SEG2 0
> +#define GC_BASE__INST4_SEG3 0
> +#define GC_BASE__INST4_SEG4 0
> +#define GC_BASE__INST4_SEG5 0
> +
> +#define GC_BASE__INST5_SEG0 0
> +#define GC_BASE__INST5_SEG1 0
> +#define GC_BASE__INST5_SEG2 0
> +#define GC_BASE__INST5_SEG3 0
> +#define GC_BASE__INST5_SEG4 0
> +#define GC_BASE__INST5_SEG5 0
> +
> +#define GC_BASE__INST6_SEG0 0
> +#define GC_BASE__INST6_SEG1 0
> +#define GC_BASE__INST6_SEG2 0
> +#define GC_BASE__INST6_SEG3 0
> +#define GC_BASE__INST6_SEG4 0
> +#define GC_BASE__INST6_SEG5 0
> +
> +#define GC_BASE__INST7_SEG0 0
> +#define GC_BASE__INST7_SEG1 0
> +#define GC_BASE__INST7_SEG2 0
> +#define GC_BASE__INST7_SEG3 0
> +#define GC_BASE__INST7_SEG4 0
> +#define GC_BASE__INST7_SEG5 0
> +
> +#define HDP_BASE__INST0_SEG0 0x00000F20
> +#define HDP_BASE__INST0_SEG1 0x0240A400
> +#define HDP_BASE__INST0_SEG2 0
> +#define HDP_BASE__INST0_SEG3 0
> +#define HDP_BASE__INST0_SEG4 0
> +#define HDP_BASE__INST0_SEG5 0
> +
> +#define HDP_BASE__INST1_SEG0 0
> +#define HDP_BASE__INST1_SEG1 0
> +#define HDP_BASE__INST1_SEG2 0
> +#define HDP_BASE__INST1_SEG3 0
> +#define HDP_BASE__INST1_SEG4 0
> +#define HDP_BASE__INST1_SEG5 0
> +
> +#define HDP_BASE__INST2_SEG0 0
> +#define HDP_BASE__INST2_SEG1 0
> +#define HDP_BASE__INST2_SEG2 0
> +#define HDP_BASE__INST2_SEG3 0
> +#define HDP_BASE__INST2_SEG4 0
> +#define HDP_BASE__INST2_SEG5 0
> +
> +#define HDP_BASE__INST3_SEG0 0
> +#define HDP_BASE__INST3_SEG1 0
> +#define HDP_BASE__INST3_SEG2 0
> +#define HDP_BASE__INST3_SEG3 0
> +#define HDP_BASE__INST3_SEG4 0
> +#define HDP_BASE__INST3_SEG5 0
> +
> +#define HDP_BASE__INST4_SEG0 0
> +#define HDP_BASE__INST4_SEG1 0
> +#define HDP_BASE__INST4_SEG2 0
> +#define HDP_BASE__INST4_SEG3 0
> +#define HDP_BASE__INST4_SEG4 0
> +#define HDP_BASE__INST4_SEG5 0
> +
> +#define HDP_BASE__INST5_SEG0 0
> +#define HDP_BASE__INST5_SEG1 0
> +#define HDP_BASE__INST5_SEG2 0
> +#define HDP_BASE__INST5_SEG3 0
> +#define HDP_BASE__INST5_SEG4 0
> +#define HDP_BASE__INST5_SEG5 0
> +
> +#define HDP_BASE__INST6_SEG0 0
> +#define HDP_BASE__INST6_SEG1 0
> +#define HDP_BASE__INST6_SEG2 0
> +#define HDP_BASE__INST6_SEG3 0
> +#define HDP_BASE__INST6_SEG4 0
> +#define HDP_BASE__INST6_SEG5 0
> +
> +#define HDP_BASE__INST7_SEG0 0
> +#define HDP_BASE__INST7_SEG1 0
> +#define HDP_BASE__INST7_SEG2 0
> +#define HDP_BASE__INST7_SEG3 0
> +#define HDP_BASE__INST7_SEG4 0
> +#define HDP_BASE__INST7_SEG5 0
> +
> +#define ISP_BASE__INST0_SEG0 0x00018000
> +#define ISP_BASE__INST0_SEG1 0x0240B000
> +#define ISP_BASE__INST0_SEG2 0
> +#define ISP_BASE__INST0_SEG3 0
> +#define ISP_BASE__INST0_SEG4 0
> +#define ISP_BASE__INST0_SEG5 0
> +
> +#define ISP_BASE__INST1_SEG0 0
> +#define ISP_BASE__INST1_SEG1 0
> +#define ISP_BASE__INST1_SEG2 0
> +#define ISP_BASE__INST1_SEG3 0
> +#define ISP_BASE__INST1_SEG4 0
> +#define ISP_BASE__INST1_SEG5 0
> +
> +#define ISP_BASE__INST2_SEG0 0
> +#define ISP_BASE__INST2_SEG1 0
> +#define ISP_BASE__INST2_SEG2 0
> +#define ISP_BASE__INST2_SEG3 0
> +#define ISP_BASE__INST2_SEG4 0
> +#define ISP_BASE__INST2_SEG5 0
> +
> +#define ISP_BASE__INST3_SEG0 0
> +#define ISP_BASE__INST3_SEG1 0
> +#define ISP_BASE__INST3_SEG2 0
> +#define ISP_BASE__INST3_SEG3 0
> +#define ISP_BASE__INST3_SEG4 0
> +#define ISP_BASE__INST3_SEG5 0
> +
> +#define ISP_BASE__INST4_SEG0 0
> +#define ISP_BASE__INST4_SEG1 0
> +#define ISP_BASE__INST4_SEG2 0
> +#define ISP_BASE__INST4_SEG3 0
> +#define ISP_BASE__INST4_SEG4 0
> +#define ISP_BASE__INST4_SEG5 0
> +
> +#define ISP_BASE__INST5_SEG0 0
> +#define ISP_BASE__INST5_SEG1 0
> +#define ISP_BASE__INST5_SEG2 0
> +#define ISP_BASE__INST5_SEG3 0
> +#define ISP_BASE__INST5_SEG4 0
> +#define ISP_BASE__INST5_SEG5 0
> +
> +#define ISP_BASE__INST6_SEG0 0
> +#define ISP_BASE__INST6_SEG1 0
> +#define ISP_BASE__INST6_SEG2 0
> +#define ISP_BASE__INST6_SEG3 0
> +#define ISP_BASE__INST6_SEG4 0
> +#define ISP_BASE__INST6_SEG5 0
> +
> +#define ISP_BASE__INST7_SEG0 0
> +#define ISP_BASE__INST7_SEG1 0
> +#define ISP_BASE__INST7_SEG2 0
> +#define ISP_BASE__INST7_SEG3 0
> +#define ISP_BASE__INST7_SEG4 0
> +#define ISP_BASE__INST7_SEG5 0
> +
> +#define MMHUB_BASE__INST0_SEG0 0x00013200
> +#define MMHUB_BASE__INST0_SEG1 0x0001A000
> +#define MMHUB_BASE__INST0_SEG2 0x02408800
> +#define MMHUB_BASE__INST0_SEG3 0
> +#define MMHUB_BASE__INST0_SEG4 0
> +#define MMHUB_BASE__INST0_SEG5 0
> +
> +#define MMHUB_BASE__INST1_SEG0 0
> +#define MMHUB_BASE__INST1_SEG1 0
> +#define MMHUB_BASE__INST1_SEG2 0
> +#define MMHUB_BASE__INST1_SEG3 0
> +#define MMHUB_BASE__INST1_SEG4 0
> +#define MMHUB_BASE__INST1_SEG5 0
> +
> +#define MMHUB_BASE__INST2_SEG0 0
> +#define MMHUB_BASE__INST2_SEG1 0
> +#define MMHUB_BASE__INST2_SEG2 0
> +#define MMHUB_BASE__INST2_SEG3 0
> +#define MMHUB_BASE__INST2_SEG4 0
> +#define MMHUB_BASE__INST2_SEG5 0
> +
> +#define MMHUB_BASE__INST3_SEG0 0
> +#define MMHUB_BASE__INST3_SEG1 0
> +#define MMHUB_BASE__INST3_SEG2 0
> +#define MMHUB_BASE__INST3_SEG3 0
> +#define MMHUB_BASE__INST3_SEG4 0
> +#define MMHUB_BASE__INST3_SEG5 0
> +
> +#define MMHUB_BASE__INST4_SEG0 0
> +#define MMHUB_BASE__INST4_SEG1 0
> +#define MMHUB_BASE__INST4_SEG2 0
> +#define MMHUB_BASE__INST4_SEG3 0
> +#define MMHUB_BASE__INST4_SEG4 0
> +#define MMHUB_BASE__INST4_SEG5 0
> +
> +#define MMHUB_BASE__INST5_SEG0 0
> +#define MMHUB_BASE__INST5_SEG1 0
> +#define MMHUB_BASE__INST5_SEG2 0
> +#define MMHUB_BASE__INST5_SEG3 0
> +#define MMHUB_BASE__INST5_SEG4 0
> +#define MMHUB_BASE__INST5_SEG5 0
> +
> +#define MMHUB_BASE__INST6_SEG0 0
> +#define MMHUB_BASE__INST6_SEG1 0
> +#define MMHUB_BASE__INST6_SEG2 0
> +#define MMHUB_BASE__INST6_SEG3 0
> +#define MMHUB_BASE__INST6_SEG4 0
> +#define MMHUB_BASE__INST6_SEG5 0
> +
> +#define MMHUB_BASE__INST7_SEG0 0
> +#define MMHUB_BASE__INST7_SEG1 0
> +#define MMHUB_BASE__INST7_SEG2 0
> +#define MMHUB_BASE__INST7_SEG3 0
> +#define MMHUB_BASE__INST7_SEG4 0
> +#define MMHUB_BASE__INST7_SEG5 0
> +
> +#define MP0_BASE__INST0_SEG0 0x00016000
> +#define MP0_BASE__INST0_SEG1 0x0243FC00
> +#define MP0_BASE__INST0_SEG2 0x00DC0000
> +#define MP0_BASE__INST0_SEG3 0x00E00000
> +#define MP0_BASE__INST0_SEG4 0x00E40000
> +#define MP0_BASE__INST0_SEG5 0
> +
> +#define MP0_BASE__INST1_SEG0 0
> +#define MP0_BASE__INST1_SEG1 0
> +#define MP0_BASE__INST1_SEG2 0
> +#define MP0_BASE__INST1_SEG3 0
> +#define MP0_BASE__INST1_SEG4 0
> +#define MP0_BASE__INST1_SEG5 0
> +
> +#define MP0_BASE__INST2_SEG0 0
> +#define MP0_BASE__INST2_SEG1 0
> +#define MP0_BASE__INST2_SEG2 0
> +#define MP0_BASE__INST2_SEG3 0
> +#define MP0_BASE__INST2_SEG4 0
> +#define MP0_BASE__INST2_SEG5 0
> +
> +#define MP0_BASE__INST3_SEG0 0
> +#define MP0_BASE__INST3_SEG1 0
> +#define MP0_BASE__INST3_SEG2 0
> +#define MP0_BASE__INST3_SEG3 0
> +#define MP0_BASE__INST3_SEG4 0
> +#define MP0_BASE__INST3_SEG5 0
> +
> +#define MP0_BASE__INST4_SEG0 0
> +#define MP0_BASE__INST4_SEG1 0
> +#define MP0_BASE__INST4_SEG2 0
> +#define MP0_BASE__INST4_SEG3 0
> +#define MP0_BASE__INST4_SEG4 0
> +#define MP0_BASE__INST4_SEG5 0
> +
> +#define MP0_BASE__INST5_SEG0 0
> +#define MP0_BASE__INST5_SEG1 0
> +#define MP0_BASE__INST5_SEG2 0
> +#define MP0_BASE__INST5_SEG3 0
> +#define MP0_BASE__INST5_SEG4 0
> +#define MP0_BASE__INST5_SEG5 0
> +
> +#define MP0_BASE__INST6_SEG0 0
> +#define MP0_BASE__INST6_SEG1 0
> +#define MP0_BASE__INST6_SEG2 0
> +#define MP0_BASE__INST6_SEG3 0
> +#define MP0_BASE__INST6_SEG4 0
> +#define MP0_BASE__INST6_SEG5 0
> +
> +#define MP0_BASE__INST7_SEG0 0
> +#define MP0_BASE__INST7_SEG1 0
> +#define MP0_BASE__INST7_SEG2 0
> +#define MP0_BASE__INST7_SEG3 0
> +#define MP0_BASE__INST7_SEG4 0
> +#define MP0_BASE__INST7_SEG5 0
> +
> +#define MP1_BASE__INST0_SEG0 0x00016000
> +#define MP1_BASE__INST0_SEG1 0x0243FC00
> +#define MP1_BASE__INST0_SEG2 0x00DC0000
> +#define MP1_BASE__INST0_SEG3 0x00E00000
> +#define MP1_BASE__INST0_SEG4 0x00E40000
> +#define MP1_BASE__INST0_SEG5 0
> +
> +#define MP1_BASE__INST1_SEG0 0
> +#define MP1_BASE__INST1_SEG1 0
> +#define MP1_BASE__INST1_SEG2 0
> +#define MP1_BASE__INST1_SEG3 0
> +#define MP1_BASE__INST1_SEG4 0
> +#define MP1_BASE__INST1_SEG5 0
> +
> +#define MP1_BASE__INST2_SEG0 0
> +#define MP1_BASE__INST2_SEG1 0
> +#define MP1_BASE__INST2_SEG2 0
> +#define MP1_BASE__INST2_SEG3 0
> +#define MP1_BASE__INST2_SEG4 0
> +#define MP1_BASE__INST2_SEG5 0
> +
> +#define MP1_BASE__INST3_SEG0 0
> +#define MP1_BASE__INST3_SEG1 0
> +#define MP1_BASE__INST3_SEG2 0
> +#define MP1_BASE__INST3_SEG3 0
> +#define MP1_BASE__INST3_SEG4 0
> +#define MP1_BASE__INST3_SEG5 0
> +
> +#define MP1_BASE__INST4_SEG0 0
> +#define MP1_BASE__INST4_SEG1 0
> +#define MP1_BASE__INST4_SEG2 0
> +#define MP1_BASE__INST4_SEG3 0
> +#define MP1_BASE__INST4_SEG4 0
> +#define MP1_BASE__INST4_SEG5 0
> +
> +#define MP1_BASE__INST5_SEG0 0
> +#define MP1_BASE__INST5_SEG1 0
> +#define MP1_BASE__INST5_SEG2 0
> +#define MP1_BASE__INST5_SEG3 0
> +#define MP1_BASE__INST5_SEG4 0
> +#define MP1_BASE__INST5_SEG5 0
> +
> +#define MP1_BASE__INST6_SEG0 0
> +#define MP1_BASE__INST6_SEG1 0
> +#define MP1_BASE__INST6_SEG2 0
> +#define MP1_BASE__INST6_SEG3 0
> +#define MP1_BASE__INST6_SEG4 0
> +#define MP1_BASE__INST6_SEG5 0
> +
> +#define MP1_BASE__INST7_SEG0 0
> +#define MP1_BASE__INST7_SEG1 0
> +#define MP1_BASE__INST7_SEG2 0
> +#define MP1_BASE__INST7_SEG3 0
> +#define MP1_BASE__INST7_SEG4 0
> +#define MP1_BASE__INST7_SEG5 0
> +
> +#define MP2_BASE__INST0_SEG0 0x00016400
> +#define MP2_BASE__INST0_SEG1 0x02400800
> +#define MP2_BASE__INST0_SEG2 0x00F40000
> +#define MP2_BASE__INST0_SEG3 0x00F80000
> +#define MP2_BASE__INST0_SEG4 0x00FC0000
> +#define MP2_BASE__INST0_SEG5 0
> +
> +#define MP2_BASE__INST1_SEG0 0
> +#define MP2_BASE__INST1_SEG1 0
> +#define MP2_BASE__INST1_SEG2 0
> +#define MP2_BASE__INST1_SEG3 0
> +#define MP2_BASE__INST1_SEG4 0
> +#define MP2_BASE__INST1_SEG5 0
> +
> +#define MP2_BASE__INST2_SEG0 0
> +#define MP2_BASE__INST2_SEG1 0
> +#define MP2_BASE__INST2_SEG2 0
> +#define MP2_BASE__INST2_SEG3 0
> +#define MP2_BASE__INST2_SEG4 0
> +#define MP2_BASE__INST2_SEG5 0
> +
> +#define MP2_BASE__INST3_SEG0 0
> +#define MP2_BASE__INST3_SEG1 0
> +#define MP2_BASE__INST3_SEG2 0
> +#define MP2_BASE__INST3_SEG3 0
> +#define MP2_BASE__INST3_SEG4 0
> +#define MP2_BASE__INST3_SEG5 0
> +
> +#define MP2_BASE__INST4_SEG0 0
> +#define MP2_BASE__INST4_SEG1 0
> +#define MP2_BASE__INST4_SEG2 0
> +#define MP2_BASE__INST4_SEG3 0
> +#define MP2_BASE__INST4_SEG4 0
> +#define MP2_BASE__INST4_SEG5 0
> +
> +#define MP2_BASE__INST5_SEG0 0
> +#define MP2_BASE__INST5_SEG1 0
> +#define MP2_BASE__INST5_SEG2 0
> +#define MP2_BASE__INST5_SEG3 0
> +#define MP2_BASE__INST5_SEG4 0
> +#define MP2_BASE__INST5_SEG5 0
> +
> +#define MP2_BASE__INST6_SEG0 0
> +#define MP2_BASE__INST6_SEG1 0
> +#define MP2_BASE__INST6_SEG2 0
> +#define MP2_BASE__INST6_SEG3 0
> +#define MP2_BASE__INST6_SEG4 0
> +#define MP2_BASE__INST6_SEG5 0
> +
> +#define MP2_BASE__INST7_SEG0 0
> +#define MP2_BASE__INST7_SEG1 0
> +#define MP2_BASE__INST7_SEG2 0
> +#define MP2_BASE__INST7_SEG3 0
> +#define MP2_BASE__INST7_SEG4 0
> +#define MP2_BASE__INST7_SEG5 0
> +
> +#define NBIO_BASE__INST0_SEG0 0x00000000
> +#define NBIO_BASE__INST0_SEG1 0x00000014
> +#define NBIO_BASE__INST0_SEG2 0x00000D20
> +#define NBIO_BASE__INST0_SEG3 0x00010400
> +#define NBIO_BASE__INST0_SEG4 0x0241B000
> +#define NBIO_BASE__INST0_SEG5 0x04040000
> +
> +#define NBIO_BASE__INST1_SEG0 0
> +#define NBIO_BASE__INST1_SEG1 0
> +#define NBIO_BASE__INST1_SEG2 0
> +#define NBIO_BASE__INST1_SEG3 0
> +#define NBIO_BASE__INST1_SEG4 0
> +#define NBIO_BASE__INST1_SEG5 0
> +
> +#define NBIO_BASE__INST2_SEG0 0
> +#define NBIO_BASE__INST2_SEG1 0
> +#define NBIO_BASE__INST2_SEG2 0
> +#define NBIO_BASE__INST2_SEG3 0
> +#define NBIO_BASE__INST2_SEG4 0
> +#define NBIO_BASE__INST2_SEG5 0
> +
> +#define NBIO_BASE__INST3_SEG0 0
> +#define NBIO_BASE__INST3_SEG1 0
> +#define NBIO_BASE__INST3_SEG2 0
> +#define NBIO_BASE__INST3_SEG3 0
> +#define NBIO_BASE__INST3_SEG4 0
> +#define NBIO_BASE__INST3_SEG5 0
> +
> +#define NBIO_BASE__INST4_SEG0 0
> +#define NBIO_BASE__INST4_SEG1 0
> +#define NBIO_BASE__INST4_SEG2 0
> +#define NBIO_BASE__INST4_SEG3 0
> +#define NBIO_BASE__INST4_SEG4 0
> +#define NBIO_BASE__INST4_SEG5 0
> +
> +#define NBIO_BASE__INST5_SEG0 0
> +#define NBIO_BASE__INST5_SEG1 0
> +#define NBIO_BASE__INST5_SEG2 0
> +#define NBIO_BASE__INST5_SEG3 0
> +#define NBIO_BASE__INST5_SEG4 0
> +#define NBIO_BASE__INST5_SEG5 0
> +
> +#define NBIO_BASE__INST6_SEG0 0
> +#define NBIO_BASE__INST6_SEG1 0
> +#define NBIO_BASE__INST6_SEG2 0
> +#define NBIO_BASE__INST6_SEG3 0
> +#define NBIO_BASE__INST6_SEG4 0
> +#define NBIO_BASE__INST6_SEG5 0
> +
> +#define NBIO_BASE__INST7_SEG0 0
> +#define NBIO_BASE__INST7_SEG1 0
> +#define NBIO_BASE__INST7_SEG2 0
> +#define NBIO_BASE__INST7_SEG3 0
> +#define NBIO_BASE__INST7_SEG4 0
> +#define NBIO_BASE__INST7_SEG5 0
> +
> +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> +#define OSSSYS_BASE__INST0_SEG1 0x0240A000
> +#define OSSSYS_BASE__INST0_SEG2 0
> +#define OSSSYS_BASE__INST0_SEG3 0
> +#define OSSSYS_BASE__INST0_SEG4 0
> +#define OSSSYS_BASE__INST0_SEG5 0
> +
> +#define OSSSYS_BASE__INST1_SEG0 0
> +#define OSSSYS_BASE__INST1_SEG1 0
> +#define OSSSYS_BASE__INST1_SEG2 0
> +#define OSSSYS_BASE__INST1_SEG3 0
> +#define OSSSYS_BASE__INST1_SEG4 0
> +#define OSSSYS_BASE__INST1_SEG5 0
> +
> +#define OSSSYS_BASE__INST2_SEG0 0
> +#define OSSSYS_BASE__INST2_SEG1 0
> +#define OSSSYS_BASE__INST2_SEG2 0
> +#define OSSSYS_BASE__INST2_SEG3 0
> +#define OSSSYS_BASE__INST2_SEG4 0
> +#define OSSSYS_BASE__INST2_SEG5 0
> +
> +#define OSSSYS_BASE__INST3_SEG0 0
> +#define OSSSYS_BASE__INST3_SEG1 0
> +#define OSSSYS_BASE__INST3_SEG2 0
> +#define OSSSYS_BASE__INST3_SEG3 0
> +#define OSSSYS_BASE__INST3_SEG4 0
> +#define OSSSYS_BASE__INST3_SEG5 0
> +
> +#define OSSSYS_BASE__INST4_SEG0 0
> +#define OSSSYS_BASE__INST4_SEG1 0
> +#define OSSSYS_BASE__INST4_SEG2 0
> +#define OSSSYS_BASE__INST4_SEG3 0
> +#define OSSSYS_BASE__INST4_SEG4 0
> +#define OSSSYS_BASE__INST4_SEG5 0
> +
> +#define OSSSYS_BASE__INST5_SEG0 0
> +#define OSSSYS_BASE__INST5_SEG1 0
> +#define OSSSYS_BASE__INST5_SEG2 0
> +#define OSSSYS_BASE__INST5_SEG3 0
> +#define OSSSYS_BASE__INST5_SEG4 0
> +#define OSSSYS_BASE__INST5_SEG5 0
> +
> +#define OSSSYS_BASE__INST6_SEG0 0
> +#define OSSSYS_BASE__INST6_SEG1 0
> +#define OSSSYS_BASE__INST6_SEG2 0
> +#define OSSSYS_BASE__INST6_SEG3 0
> +#define OSSSYS_BASE__INST6_SEG4 0
> +#define OSSSYS_BASE__INST6_SEG5 0
> +
> +#define OSSSYS_BASE__INST7_SEG0 0
> +#define OSSSYS_BASE__INST7_SEG1 0
> +#define OSSSYS_BASE__INST7_SEG2 0
> +#define OSSSYS_BASE__INST7_SEG3 0
> +#define OSSSYS_BASE__INST7_SEG4 0
> +#define OSSSYS_BASE__INST7_SEG5 0
> +
> +#define PCIE0_BASE__INST0_SEG0 0x00000000
> +#define PCIE0_BASE__INST0_SEG1 0x00000014
> +#define PCIE0_BASE__INST0_SEG2 0x00000D20
> +#define PCIE0_BASE__INST0_SEG3 0x00010400
> +#define PCIE0_BASE__INST0_SEG4 0x0241B000
> +#define PCIE0_BASE__INST0_SEG5 0x04040000
> +
> +#define PCIE0_BASE__INST1_SEG0 0
> +#define PCIE0_BASE__INST1_SEG1 0
> +#define PCIE0_BASE__INST1_SEG2 0
> +#define PCIE0_BASE__INST1_SEG3 0
> +#define PCIE0_BASE__INST1_SEG4 0
> +#define PCIE0_BASE__INST1_SEG5 0
> +
> +#define PCIE0_BASE__INST2_SEG0 0
> +#define PCIE0_BASE__INST2_SEG1 0
> +#define PCIE0_BASE__INST2_SEG2 0
> +#define PCIE0_BASE__INST2_SEG3 0
> +#define PCIE0_BASE__INST2_SEG4 0
> +#define PCIE0_BASE__INST2_SEG5 0
> +
> +#define PCIE0_BASE__INST3_SEG0 0
> +#define PCIE0_BASE__INST3_SEG1 0
> +#define PCIE0_BASE__INST3_SEG2 0
> +#define PCIE0_BASE__INST3_SEG3 0
> +#define PCIE0_BASE__INST3_SEG4 0
> +#define PCIE0_BASE__INST3_SEG5 0
> +
> +#define PCIE0_BASE__INST4_SEG0 0
> +#define PCIE0_BASE__INST4_SEG1 0
> +#define PCIE0_BASE__INST4_SEG2 0
> +#define PCIE0_BASE__INST4_SEG3 0
> +#define PCIE0_BASE__INST4_SEG4 0
> +#define PCIE0_BASE__INST4_SEG5 0
> +
> +#define PCIE0_BASE__INST5_SEG0 0
> +#define PCIE0_BASE__INST5_SEG1 0
> +#define PCIE0_BASE__INST5_SEG2 0
> +#define PCIE0_BASE__INST5_SEG3 0
> +#define PCIE0_BASE__INST5_SEG4 0
> +#define PCIE0_BASE__INST5_SEG5 0
> +
> +#define PCIE0_BASE__INST6_SEG0 0
> +#define PCIE0_BASE__INST6_SEG1 0
> +#define PCIE0_BASE__INST6_SEG2 0
> +#define PCIE0_BASE__INST6_SEG3 0
> +#define PCIE0_BASE__INST6_SEG4 0
> +#define PCIE0_BASE__INST6_SEG5 0
> +
> +#define PCIE0_BASE__INST7_SEG0 0
> +#define PCIE0_BASE__INST7_SEG1 0
> +#define PCIE0_BASE__INST7_SEG2 0
> +#define PCIE0_BASE__INST7_SEG3 0
> +#define PCIE0_BASE__INST7_SEG4 0
> +#define PCIE0_BASE__INST7_SEG5 0
> +
> +#define SMUIO_BASE__INST0_SEG0 0x00016800
> +#define SMUIO_BASE__INST0_SEG1 0x00016A00
> +#define SMUIO_BASE__INST0_SEG2 0x02401000
> +#define SMUIO_BASE__INST0_SEG3 0x00440000
> +#define SMUIO_BASE__INST0_SEG4 0
> +#define SMUIO_BASE__INST0_SEG5 0
> +
> +#define SMUIO_BASE__INST1_SEG0 0x0001BC00
> +#define SMUIO_BASE__INST1_SEG1 0x0242D400
> +#define SMUIO_BASE__INST1_SEG2 0
> +#define SMUIO_BASE__INST1_SEG3 0
> +#define SMUIO_BASE__INST1_SEG4 0
> +#define SMUIO_BASE__INST1_SEG5 0
> +
> +#define SMUIO_BASE__INST2_SEG0 0
> +#define SMUIO_BASE__INST2_SEG1 0
> +#define SMUIO_BASE__INST2_SEG2 0
> +#define SMUIO_BASE__INST2_SEG3 0
> +#define SMUIO_BASE__INST2_SEG4 0
> +#define SMUIO_BASE__INST2_SEG5 0
> +
> +#define SMUIO_BASE__INST3_SEG0 0
> +#define SMUIO_BASE__INST3_SEG1 0
> +#define SMUIO_BASE__INST3_SEG2 0
> +#define SMUIO_BASE__INST3_SEG3 0
> +#define SMUIO_BASE__INST3_SEG4 0
> +#define SMUIO_BASE__INST3_SEG5 0
> +
> +#define SMUIO_BASE__INST4_SEG0 0
> +#define SMUIO_BASE__INST4_SEG1 0
> +#define SMUIO_BASE__INST4_SEG2 0
> +#define SMUIO_BASE__INST4_SEG3 0
> +#define SMUIO_BASE__INST4_SEG4 0
> +#define SMUIO_BASE__INST4_SEG5 0
> +
> +#define SMUIO_BASE__INST5_SEG0 0
> +#define SMUIO_BASE__INST5_SEG1 0
> +#define SMUIO_BASE__INST5_SEG2 0
> +#define SMUIO_BASE__INST5_SEG3 0
> +#define SMUIO_BASE__INST5_SEG4 0
> +#define SMUIO_BASE__INST5_SEG5 0
> +
> +#define SMUIO_BASE__INST6_SEG0 0
> +#define SMUIO_BASE__INST6_SEG1 0
> +#define SMUIO_BASE__INST6_SEG2 0
> +#define SMUIO_BASE__INST6_SEG3 0
> +#define SMUIO_BASE__INST6_SEG4 0
> +#define SMUIO_BASE__INST6_SEG5 0
> +
> +#define SMUIO_BASE__INST7_SEG0 0
> +#define SMUIO_BASE__INST7_SEG1 0
> +#define SMUIO_BASE__INST7_SEG2 0
> +#define SMUIO_BASE__INST7_SEG3 0
> +#define SMUIO_BASE__INST7_SEG4 0
> +#define SMUIO_BASE__INST7_SEG5 0
> +
> +#define THM_BASE__INST0_SEG0 0x00016600
> +#define THM_BASE__INST0_SEG1 0x02400C00
> +#define THM_BASE__INST0_SEG2 0
> +#define THM_BASE__INST0_SEG3 0
> +#define THM_BASE__INST0_SEG4 0
> +#define THM_BASE__INST0_SEG5 0
> +
> +#define THM_BASE__INST1_SEG0 0
> +#define THM_BASE__INST1_SEG1 0
> +#define THM_BASE__INST1_SEG2 0
> +#define THM_BASE__INST1_SEG3 0
> +#define THM_BASE__INST1_SEG4 0
> +#define THM_BASE__INST1_SEG5 0
> +
> +#define THM_BASE__INST2_SEG0 0
> +#define THM_BASE__INST2_SEG1 0
> +#define THM_BASE__INST2_SEG2 0
> +#define THM_BASE__INST2_SEG3 0
> +#define THM_BASE__INST2_SEG4 0
> +#define THM_BASE__INST2_SEG5 0
> +
> +#define THM_BASE__INST3_SEG0 0
> +#define THM_BASE__INST3_SEG1 0
> +#define THM_BASE__INST3_SEG2 0
> +#define THM_BASE__INST3_SEG3 0
> +#define THM_BASE__INST3_SEG4 0
> +#define THM_BASE__INST3_SEG5 0
> +
> +#define THM_BASE__INST4_SEG0 0
> +#define THM_BASE__INST4_SEG1 0
> +#define THM_BASE__INST4_SEG2 0
> +#define THM_BASE__INST4_SEG3 0
> +#define THM_BASE__INST4_SEG4 0
> +#define THM_BASE__INST4_SEG5 0
> +
> +#define THM_BASE__INST5_SEG0 0
> +#define THM_BASE__INST5_SEG1 0
> +#define THM_BASE__INST5_SEG2 0
> +#define THM_BASE__INST5_SEG3 0
> +#define THM_BASE__INST5_SEG4 0
> +#define THM_BASE__INST5_SEG5 0
> +
> +#define THM_BASE__INST6_SEG0 0
> +#define THM_BASE__INST6_SEG1 0
> +#define THM_BASE__INST6_SEG2 0
> +#define THM_BASE__INST6_SEG3 0
> +#define THM_BASE__INST6_SEG4 0
> +#define THM_BASE__INST6_SEG5 0
> +
> +#define THM_BASE__INST7_SEG0 0
> +#define THM_BASE__INST7_SEG1 0
> +#define THM_BASE__INST7_SEG2 0
> +#define THM_BASE__INST7_SEG3 0
> +#define THM_BASE__INST7_SEG4 0
> +#define THM_BASE__INST7_SEG5 0
> +
> +#define UMC_BASE__INST0_SEG0 0x00014000
> +#define UMC_BASE__INST0_SEG1 0x02425800
> +#define UMC_BASE__INST0_SEG2 0
> +#define UMC_BASE__INST0_SEG3 0
> +#define UMC_BASE__INST0_SEG4 0
> +#define UMC_BASE__INST0_SEG5 0
> +
> +#define UMC_BASE__INST1_SEG0 0x00054000
> +#define UMC_BASE__INST1_SEG1 0x02425C00
> +#define UMC_BASE__INST1_SEG2 0
> +#define UMC_BASE__INST1_SEG3 0
> +#define UMC_BASE__INST1_SEG4 0
> +#define UMC_BASE__INST1_SEG5 0
> +
> +#define UMC_BASE__INST2_SEG0 0x00094000
> +#define UMC_BASE__INST2_SEG1 0x02426000
> +#define UMC_BASE__INST2_SEG2 0
> +#define UMC_BASE__INST2_SEG3 0
> +#define UMC_BASE__INST2_SEG4 0
> +#define UMC_BASE__INST2_SEG5 0
> +
> +#define UMC_BASE__INST3_SEG0 0x000D4000
> +#define UMC_BASE__INST3_SEG1 0x02426400
> +#define UMC_BASE__INST3_SEG2 0
> +#define UMC_BASE__INST3_SEG3 0
> +#define UMC_BASE__INST3_SEG4 0
> +#define UMC_BASE__INST3_SEG5 0
> +
> +#define UMC_BASE__INST4_SEG0 0
> +#define UMC_BASE__INST4_SEG1 0
> +#define UMC_BASE__INST4_SEG2 0
> +#define UMC_BASE__INST4_SEG3 0
> +#define UMC_BASE__INST4_SEG4 0
> +#define UMC_BASE__INST4_SEG5 0
> +
> +#define UMC_BASE__INST5_SEG0 0
> +#define UMC_BASE__INST5_SEG1 0
> +#define UMC_BASE__INST5_SEG2 0
> +#define UMC_BASE__INST5_SEG3 0
> +#define UMC_BASE__INST5_SEG4 0
> +#define UMC_BASE__INST5_SEG5 0
> +
> +#define UMC_BASE__INST6_SEG0 0
> +#define UMC_BASE__INST6_SEG1 0
> +#define UMC_BASE__INST6_SEG2 0
> +#define UMC_BASE__INST6_SEG3 0
> +#define UMC_BASE__INST6_SEG4 0
> +#define UMC_BASE__INST6_SEG5 0
> +
> +#define UMC_BASE__INST7_SEG0 0
> +#define UMC_BASE__INST7_SEG1 0
> +#define UMC_BASE__INST7_SEG2 0
> +#define UMC_BASE__INST7_SEG3 0
> +#define UMC_BASE__INST7_SEG4 0
> +#define UMC_BASE__INST7_SEG5 0
> +
> +#define USB_BASE__INST0_SEG0 0x0242A800
> +#define USB_BASE__INST0_SEG1 0x05B00000
> +#define USB_BASE__INST0_SEG2 0
> +#define USB_BASE__INST0_SEG3 0
> +#define USB_BASE__INST0_SEG4 0
> +#define USB_BASE__INST0_SEG5 0
> +
> +#define USB_BASE__INST1_SEG0 0x0242AC00
> +#define USB_BASE__INST1_SEG1 0x05B80000
> +#define USB_BASE__INST1_SEG2 0
> +#define USB_BASE__INST1_SEG3 0
> +#define USB_BASE__INST1_SEG4 0
> +#define USB_BASE__INST1_SEG5 0
> +
> +#define USB_BASE__INST2_SEG0 0x0242B000
> +#define USB_BASE__INST2_SEG1 0x05C00000
> +#define USB_BASE__INST2_SEG2 0
> +#define USB_BASE__INST2_SEG3 0
> +#define USB_BASE__INST2_SEG4 0
> +#define USB_BASE__INST2_SEG5 0
> +
> +#define USB_BASE__INST3_SEG0 0
> +#define USB_BASE__INST3_SEG1 0
> +#define USB_BASE__INST3_SEG2 0
> +#define USB_BASE__INST3_SEG3 0
> +#define USB_BASE__INST3_SEG4 0
> +#define USB_BASE__INST3_SEG5 0
> +
> +#define USB_BASE__INST4_SEG0 0
> +#define USB_BASE__INST4_SEG1 0
> +#define USB_BASE__INST4_SEG2 0
> +#define USB_BASE__INST4_SEG3 0
> +#define USB_BASE__INST4_SEG4 0
> +#define USB_BASE__INST4_SEG5 0
> +
> +#define USB_BASE__INST5_SEG0 0
> +#define USB_BASE__INST5_SEG1 0
> +#define USB_BASE__INST5_SEG2 0
> +#define USB_BASE__INST5_SEG3 0
> +#define USB_BASE__INST5_SEG4 0
> +#define USB_BASE__INST5_SEG5 0
> +
> +#define USB_BASE__INST6_SEG0 0
> +#define USB_BASE__INST6_SEG1 0
> +#define USB_BASE__INST6_SEG2 0
> +#define USB_BASE__INST6_SEG3 0
> +#define USB_BASE__INST6_SEG4 0
> +#define USB_BASE__INST6_SEG5 0
> +
> +#define USB_BASE__INST7_SEG0 0
> +#define USB_BASE__INST7_SEG1 0
> +#define USB_BASE__INST7_SEG2 0
> +#define USB_BASE__INST7_SEG3 0
> +#define USB_BASE__INST7_SEG4 0
> +#define USB_BASE__INST7_SEG5 0
> +
> +#define VCN_BASE__INST0_SEG0 0x00007800
> +#define VCN_BASE__INST0_SEG1 0x00007E00
> +#define VCN_BASE__INST0_SEG2 0x02403000
> +#define VCN_BASE__INST0_SEG3 0
> +#define VCN_BASE__INST0_SEG4 0
> +#define VCN_BASE__INST0_SEG5 0
> +
> +#define VCN_BASE__INST1_SEG0 0
> +#define VCN_BASE__INST1_SEG1 0
> +#define VCN_BASE__INST1_SEG2 0
> +#define VCN_BASE__INST1_SEG3 0
> +#define VCN_BASE__INST1_SEG4 0
> +#define VCN_BASE__INST1_SEG5 0
> +
> +#define VCN_BASE__INST2_SEG0 0
> +#define VCN_BASE__INST2_SEG1 0
> +#define VCN_BASE__INST2_SEG2 0
> +#define VCN_BASE__INST2_SEG3 0
> +#define VCN_BASE__INST2_SEG4 0
> +#define VCN_BASE__INST2_SEG5 0
> +
> +#define VCN_BASE__INST3_SEG0 0
> +#define VCN_BASE__INST3_SEG1 0
> +#define VCN_BASE__INST3_SEG2 0
> +#define VCN_BASE__INST3_SEG3 0
> +#define VCN_BASE__INST3_SEG4 0
> +#define VCN_BASE__INST3_SEG5 0
> +
> +#define VCN_BASE__INST4_SEG0 0
> +#define VCN_BASE__INST4_SEG1 0
> +#define VCN_BASE__INST4_SEG2 0
> +#define VCN_BASE__INST4_SEG3 0
> +#define VCN_BASE__INST4_SEG4 0
> +#define VCN_BASE__INST4_SEG5 0
> +
> +#define VCN_BASE__INST5_SEG0 0
> +#define VCN_BASE__INST5_SEG1 0
> +#define VCN_BASE__INST5_SEG2 0
> +#define VCN_BASE__INST5_SEG3 0
> +#define VCN_BASE__INST5_SEG4 0
> +#define VCN_BASE__INST5_SEG5 0
> +
> +#define VCN_BASE__INST6_SEG0 0
> +#define VCN_BASE__INST6_SEG1 0
> +#define VCN_BASE__INST6_SEG2 0
> +#define VCN_BASE__INST6_SEG3 0
> +#define VCN_BASE__INST6_SEG4 0
> +#define VCN_BASE__INST6_SEG5 0
> +
> +#define VCN_BASE__INST7_SEG0 0
> +#define VCN_BASE__INST7_SEG1 0
> +#define VCN_BASE__INST7_SEG2 0
> +#define VCN_BASE__INST7_SEG3 0
> +#define VCN_BASE__INST7_SEG4 0
> +#define VCN_BASE__INST7_SEG5 0
> +
> +#endif
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-28 20:48 ` Luben Tuikov
@ 2020-09-29 14:57 ` Alex Deucher
2020-09-29 18:59 ` Luben Tuikov
0 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 14:57 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 4:49 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > This patch adds vangogh_reg_base_init function to init the register base for
> > van gogh.
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> > drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
> > .../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
> > 4 files changed, 1569 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> > index 39976c7b100c..7866e4666a43 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> > @@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
> > amdgpu-y += \
> > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
> > vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
> > - arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
> > + arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
> >
> > # add DF block
> > amdgpu-y += \
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
> > index aeef50a6a54b..8a3bf476b18f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.h
> > @@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
> > int navi14_reg_base_init(struct amdgpu_device *adev);
> > int navi12_reg_base_init(struct amdgpu_device *adev);
> > int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
> > +int vangogh_reg_base_init(struct amdgpu_device *adev);
> > #endif
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > new file mode 100644
> > index 000000000000..4c6c3b415e7b
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > @@ -0,0 +1,51 @@
> > +/*
> > + * Copyright 2019 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + */
> > +#include "amdgpu.h"
> > +#include "nv.h"
> > +
> > +#include "soc15_common.h"
> > +#include "soc15_hw_ip.h"
> > +#include "vangogh_ip_offset.h"
> > +
> > +int vangogh_reg_base_init(struct amdgpu_device *adev)
> > +{
> > + /* HW has more IP blocks, only initialized the blocke needed by driver */
> > + uint32_t i;
> > + for (i = 0 ; i < MAX_INSTANCE ; ++i) {
> > + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> > + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
> > + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
> > + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
> > + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> > + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
> > + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
> > + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
> > + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
> > + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
> > + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
> > + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> > + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> > + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
>
> I'd align the equality sign for presentation.
>
Updated.
> > + }
> > + return 0;
> > +}
>
> This function should be "void", else the compiler will throw a warning
> when you compile nv.c.
>
Fixed.
> > diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> > new file mode 100644
> > index 000000000000..2875574b060e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> > @@ -0,0 +1,1516 @@
> > +/*
> > + * Copyright 2019 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#ifndef __VANGOGH_IP_OFFSET_H__
> > +#define __VANGOGH_IP_OFFSET_H__
> > +
> > +#define MAX_INSTANCE 8
> > +#define MAX_SEGMENT 6
>
> No. No "max". Use "num" instead, as:
>
> #define NUM_INSTANCE 8
> #define NUM_SEGMENT 6
>
> To mean, the _number_ of instances and the _number_ of
> segments. (Their count is a number.)
>
> A "maximum" (similarly "minimum") value is an _attainable_ value,
> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
> and thus max instance can never be attained.
>
> It is the count, the number of instances (segments, wlg),
> not the maximum instance. The maximum instance is 7,
> the minimum instance is 0. Similarly for segments.
Valid point, but this file is shared across components so I'd like to
minimize the differences.
Alex
>
> > +
> > +
> > +struct IP_BASE_INSTANCE
> > +{
> > + unsigned int segment[MAX_SEGMENT];
> > +};
>
> So, here if you used NUM_SEGMENT, it is very clear
> what is intended: an array of number of segments,
> i.e. their count, whose array index would be 0 to
> NUM_SEGMENTS-1.
>
> Similarly for "instance" below.
>
> Regards,
> Luben
>
> > +
> > +struct IP_BASE
> > +{
> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> > +};
> > +
> > +
> > +static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
> > + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
> > + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
> > + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
> > + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
> > + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
> > + { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
> > + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
> > + { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
> > + { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
> > + { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
> > + { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
> > + { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
> > + { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +
> > +
> > +#define ACP_BASE__INST0_SEG0 0x02403800
> > +#define ACP_BASE__INST0_SEG1 0x00480000
> > +#define ACP_BASE__INST0_SEG2 0
> > +#define ACP_BASE__INST0_SEG3 0
> > +#define ACP_BASE__INST0_SEG4 0
> > +#define ACP_BASE__INST0_SEG5 0
> > +
> > +#define ACP_BASE__INST1_SEG0 0
> > +#define ACP_BASE__INST1_SEG1 0
> > +#define ACP_BASE__INST1_SEG2 0
> > +#define ACP_BASE__INST1_SEG3 0
> > +#define ACP_BASE__INST1_SEG4 0
> > +#define ACP_BASE__INST1_SEG5 0
> > +
> > +#define ACP_BASE__INST2_SEG0 0
> > +#define ACP_BASE__INST2_SEG1 0
> > +#define ACP_BASE__INST2_SEG2 0
> > +#define ACP_BASE__INST2_SEG3 0
> > +#define ACP_BASE__INST2_SEG4 0
> > +#define ACP_BASE__INST2_SEG5 0
> > +
> > +#define ACP_BASE__INST3_SEG0 0
> > +#define ACP_BASE__INST3_SEG1 0
> > +#define ACP_BASE__INST3_SEG2 0
> > +#define ACP_BASE__INST3_SEG3 0
> > +#define ACP_BASE__INST3_SEG4 0
> > +#define ACP_BASE__INST3_SEG5 0
> > +
> > +#define ACP_BASE__INST4_SEG0 0
> > +#define ACP_BASE__INST4_SEG1 0
> > +#define ACP_BASE__INST4_SEG2 0
> > +#define ACP_BASE__INST4_SEG3 0
> > +#define ACP_BASE__INST4_SEG4 0
> > +#define ACP_BASE__INST4_SEG5 0
> > +
> > +#define ACP_BASE__INST5_SEG0 0
> > +#define ACP_BASE__INST5_SEG1 0
> > +#define ACP_BASE__INST5_SEG2 0
> > +#define ACP_BASE__INST5_SEG3 0
> > +#define ACP_BASE__INST5_SEG4 0
> > +#define ACP_BASE__INST5_SEG5 0
> > +
> > +#define ACP_BASE__INST6_SEG0 0
> > +#define ACP_BASE__INST6_SEG1 0
> > +#define ACP_BASE__INST6_SEG2 0
> > +#define ACP_BASE__INST6_SEG3 0
> > +#define ACP_BASE__INST6_SEG4 0
> > +#define ACP_BASE__INST6_SEG5 0
> > +
> > +#define ACP_BASE__INST7_SEG0 0
> > +#define ACP_BASE__INST7_SEG1 0
> > +#define ACP_BASE__INST7_SEG2 0
> > +#define ACP_BASE__INST7_SEG3 0
> > +#define ACP_BASE__INST7_SEG4 0
> > +#define ACP_BASE__INST7_SEG5 0
> > +
> > +#define ATHUB_BASE__INST0_SEG0 0x00000C00
> > +#define ATHUB_BASE__INST0_SEG1 0x00013300
> > +#define ATHUB_BASE__INST0_SEG2 0x02408C00
> > +#define ATHUB_BASE__INST0_SEG3 0
> > +#define ATHUB_BASE__INST0_SEG4 0
> > +#define ATHUB_BASE__INST0_SEG5 0
> > +
> > +#define ATHUB_BASE__INST1_SEG0 0
> > +#define ATHUB_BASE__INST1_SEG1 0
> > +#define ATHUB_BASE__INST1_SEG2 0
> > +#define ATHUB_BASE__INST1_SEG3 0
> > +#define ATHUB_BASE__INST1_SEG4 0
> > +#define ATHUB_BASE__INST1_SEG5 0
> > +
> > +#define ATHUB_BASE__INST2_SEG0 0
> > +#define ATHUB_BASE__INST2_SEG1 0
> > +#define ATHUB_BASE__INST2_SEG2 0
> > +#define ATHUB_BASE__INST2_SEG3 0
> > +#define ATHUB_BASE__INST2_SEG4 0
> > +#define ATHUB_BASE__INST2_SEG5 0
> > +
> > +#define ATHUB_BASE__INST3_SEG0 0
> > +#define ATHUB_BASE__INST3_SEG1 0
> > +#define ATHUB_BASE__INST3_SEG2 0
> > +#define ATHUB_BASE__INST3_SEG3 0
> > +#define ATHUB_BASE__INST3_SEG4 0
> > +#define ATHUB_BASE__INST3_SEG5 0
> > +
> > +#define ATHUB_BASE__INST4_SEG0 0
> > +#define ATHUB_BASE__INST4_SEG1 0
> > +#define ATHUB_BASE__INST4_SEG2 0
> > +#define ATHUB_BASE__INST4_SEG3 0
> > +#define ATHUB_BASE__INST4_SEG4 0
> > +#define ATHUB_BASE__INST4_SEG5 0
> > +
> > +#define ATHUB_BASE__INST5_SEG0 0
> > +#define ATHUB_BASE__INST5_SEG1 0
> > +#define ATHUB_BASE__INST5_SEG2 0
> > +#define ATHUB_BASE__INST5_SEG3 0
> > +#define ATHUB_BASE__INST5_SEG4 0
> > +#define ATHUB_BASE__INST5_SEG5 0
> > +
> > +#define ATHUB_BASE__INST6_SEG0 0
> > +#define ATHUB_BASE__INST6_SEG1 0
> > +#define ATHUB_BASE__INST6_SEG2 0
> > +#define ATHUB_BASE__INST6_SEG3 0
> > +#define ATHUB_BASE__INST6_SEG4 0
> > +#define ATHUB_BASE__INST6_SEG5 0
> > +
> > +#define ATHUB_BASE__INST7_SEG0 0
> > +#define ATHUB_BASE__INST7_SEG1 0
> > +#define ATHUB_BASE__INST7_SEG2 0
> > +#define ATHUB_BASE__INST7_SEG3 0
> > +#define ATHUB_BASE__INST7_SEG4 0
> > +#define ATHUB_BASE__INST7_SEG5 0
> > +
> > +#define CLK_BASE__INST0_SEG0 0x00016C00
> > +#define CLK_BASE__INST0_SEG1 0x02401800
> > +#define CLK_BASE__INST0_SEG2 0
> > +#define CLK_BASE__INST0_SEG3 0
> > +#define CLK_BASE__INST0_SEG4 0
> > +#define CLK_BASE__INST0_SEG5 0
> > +
> > +#define CLK_BASE__INST1_SEG0 0x00016E00
> > +#define CLK_BASE__INST1_SEG1 0x02401C00
> > +#define CLK_BASE__INST1_SEG2 0
> > +#define CLK_BASE__INST1_SEG3 0
> > +#define CLK_BASE__INST1_SEG4 0
> > +#define CLK_BASE__INST1_SEG5 0
> > +
> > +#define CLK_BASE__INST2_SEG0 0x00017000
> > +#define CLK_BASE__INST2_SEG1 0x02402000
> > +#define CLK_BASE__INST2_SEG2 0
> > +#define CLK_BASE__INST2_SEG3 0
> > +#define CLK_BASE__INST2_SEG4 0
> > +#define CLK_BASE__INST2_SEG5 0
> > +
> > +#define CLK_BASE__INST3_SEG0 0x00017200
> > +#define CLK_BASE__INST3_SEG1 0x02402400
> > +#define CLK_BASE__INST3_SEG2 0
> > +#define CLK_BASE__INST3_SEG3 0
> > +#define CLK_BASE__INST3_SEG4 0
> > +#define CLK_BASE__INST3_SEG5 0
> > +
> > +#define CLK_BASE__INST4_SEG0 0x0001B000
> > +#define CLK_BASE__INST4_SEG1 0x0242D800
> > +#define CLK_BASE__INST4_SEG2 0
> > +#define CLK_BASE__INST4_SEG3 0
> > +#define CLK_BASE__INST4_SEG4 0
> > +#define CLK_BASE__INST4_SEG5 0
> > +
> > +#define CLK_BASE__INST5_SEG0 0x0001B200
> > +#define CLK_BASE__INST5_SEG1 0x0242DC00
> > +#define CLK_BASE__INST5_SEG2 0
> > +#define CLK_BASE__INST5_SEG3 0
> > +#define CLK_BASE__INST5_SEG4 0
> > +#define CLK_BASE__INST5_SEG5 0
> > +
> > +#define CLK_BASE__INST6_SEG0 0x0001B400
> > +#define CLK_BASE__INST6_SEG1 0x0242E000
> > +#define CLK_BASE__INST6_SEG2 0
> > +#define CLK_BASE__INST6_SEG3 0
> > +#define CLK_BASE__INST6_SEG4 0
> > +#define CLK_BASE__INST6_SEG5 0
> > +
> > +#define CLK_BASE__INST7_SEG0 0x00017E00
> > +#define CLK_BASE__INST7_SEG1 0x0240BC00
> > +#define CLK_BASE__INST7_SEG2 0
> > +#define CLK_BASE__INST7_SEG3 0
> > +#define CLK_BASE__INST7_SEG4 0
> > +#define CLK_BASE__INST7_SEG5 0
> > +
> > +#define DF_BASE__INST0_SEG0 0x00007000
> > +#define DF_BASE__INST0_SEG1 0x0240B800
> > +#define DF_BASE__INST0_SEG2 0
> > +#define DF_BASE__INST0_SEG3 0
> > +#define DF_BASE__INST0_SEG4 0
> > +#define DF_BASE__INST0_SEG5 0
> > +
> > +#define DF_BASE__INST1_SEG0 0
> > +#define DF_BASE__INST1_SEG1 0
> > +#define DF_BASE__INST1_SEG2 0
> > +#define DF_BASE__INST1_SEG3 0
> > +#define DF_BASE__INST1_SEG4 0
> > +#define DF_BASE__INST1_SEG5 0
> > +
> > +#define DF_BASE__INST2_SEG0 0
> > +#define DF_BASE__INST2_SEG1 0
> > +#define DF_BASE__INST2_SEG2 0
> > +#define DF_BASE__INST2_SEG3 0
> > +#define DF_BASE__INST2_SEG4 0
> > +#define DF_BASE__INST2_SEG5 0
> > +
> > +#define DF_BASE__INST3_SEG0 0
> > +#define DF_BASE__INST3_SEG1 0
> > +#define DF_BASE__INST3_SEG2 0
> > +#define DF_BASE__INST3_SEG3 0
> > +#define DF_BASE__INST3_SEG4 0
> > +#define DF_BASE__INST3_SEG5 0
> > +
> > +#define DF_BASE__INST4_SEG0 0
> > +#define DF_BASE__INST4_SEG1 0
> > +#define DF_BASE__INST4_SEG2 0
> > +#define DF_BASE__INST4_SEG3 0
> > +#define DF_BASE__INST4_SEG4 0
> > +#define DF_BASE__INST4_SEG5 0
> > +
> > +#define DF_BASE__INST5_SEG0 0
> > +#define DF_BASE__INST5_SEG1 0
> > +#define DF_BASE__INST5_SEG2 0
> > +#define DF_BASE__INST5_SEG3 0
> > +#define DF_BASE__INST5_SEG4 0
> > +#define DF_BASE__INST5_SEG5 0
> > +
> > +#define DF_BASE__INST6_SEG0 0
> > +#define DF_BASE__INST6_SEG1 0
> > +#define DF_BASE__INST6_SEG2 0
> > +#define DF_BASE__INST6_SEG3 0
> > +#define DF_BASE__INST6_SEG4 0
> > +#define DF_BASE__INST6_SEG5 0
> > +
> > +#define DF_BASE__INST7_SEG0 0
> > +#define DF_BASE__INST7_SEG1 0
> > +#define DF_BASE__INST7_SEG2 0
> > +#define DF_BASE__INST7_SEG3 0
> > +#define DF_BASE__INST7_SEG4 0
> > +#define DF_BASE__INST7_SEG5 0
> > +
> > +#define DCN_BASE__INST0_SEG0 0x00000012
> > +#define DCN_BASE__INST0_SEG1 0x000000C0
> > +#define DCN_BASE__INST0_SEG2 0x000034C0
> > +#define DCN_BASE__INST0_SEG3 0x00009000
> > +#define DCN_BASE__INST0_SEG4 0x02403C00
> > +#define DCN_BASE__INST0_SEG5 0
> > +
> > +#define DCN_BASE__INST1_SEG0 0
> > +#define DCN_BASE__INST1_SEG1 0
> > +#define DCN_BASE__INST1_SEG2 0
> > +#define DCN_BASE__INST1_SEG3 0
> > +#define DCN_BASE__INST1_SEG4 0
> > +#define DCN_BASE__INST1_SEG5 0
> > +
> > +#define DCN_BASE__INST2_SEG0 0
> > +#define DCN_BASE__INST2_SEG1 0
> > +#define DCN_BASE__INST2_SEG2 0
> > +#define DCN_BASE__INST2_SEG3 0
> > +#define DCN_BASE__INST2_SEG4 0
> > +#define DCN_BASE__INST2_SEG5 0
> > +
> > +#define DCN_BASE__INST3_SEG0 0
> > +#define DCN_BASE__INST3_SEG1 0
> > +#define DCN_BASE__INST3_SEG2 0
> > +#define DCN_BASE__INST3_SEG3 0
> > +#define DCN_BASE__INST3_SEG4 0
> > +#define DCN_BASE__INST3_SEG5 0
> > +
> > +#define DCN_BASE__INST4_SEG0 0
> > +#define DCN_BASE__INST4_SEG1 0
> > +#define DCN_BASE__INST4_SEG2 0
> > +#define DCN_BASE__INST4_SEG3 0
> > +#define DCN_BASE__INST4_SEG4 0
> > +#define DCN_BASE__INST4_SEG5 0
> > +
> > +#define DCN_BASE__INST5_SEG0 0
> > +#define DCN_BASE__INST5_SEG1 0
> > +#define DCN_BASE__INST5_SEG2 0
> > +#define DCN_BASE__INST5_SEG3 0
> > +#define DCN_BASE__INST5_SEG4 0
> > +#define DCN_BASE__INST5_SEG5 0
> > +
> > +#define DCN_BASE__INST6_SEG0 0
> > +#define DCN_BASE__INST6_SEG1 0
> > +#define DCN_BASE__INST6_SEG2 0
> > +#define DCN_BASE__INST6_SEG3 0
> > +#define DCN_BASE__INST6_SEG4 0
> > +#define DCN_BASE__INST6_SEG5 0
> > +
> > +#define DCN_BASE__INST7_SEG0 0
> > +#define DCN_BASE__INST7_SEG1 0
> > +#define DCN_BASE__INST7_SEG2 0
> > +#define DCN_BASE__INST7_SEG3 0
> > +#define DCN_BASE__INST7_SEG4 0
> > +#define DCN_BASE__INST7_SEG5 0
> > +
> > +#define DPCS_BASE__INST0_SEG0 0x00000012
> > +#define DPCS_BASE__INST0_SEG1 0x000000C0
> > +#define DPCS_BASE__INST0_SEG2 0x000034C0
> > +#define DPCS_BASE__INST0_SEG3 0x00009000
> > +#define DPCS_BASE__INST0_SEG4 0x02403C00
> > +#define DPCS_BASE__INST0_SEG5 0
> > +
> > +#define DPCS_BASE__INST1_SEG0 0
> > +#define DPCS_BASE__INST1_SEG1 0
> > +#define DPCS_BASE__INST1_SEG2 0
> > +#define DPCS_BASE__INST1_SEG3 0
> > +#define DPCS_BASE__INST1_SEG4 0
> > +#define DPCS_BASE__INST1_SEG5 0
> > +
> > +#define DPCS_BASE__INST2_SEG0 0
> > +#define DPCS_BASE__INST2_SEG1 0
> > +#define DPCS_BASE__INST2_SEG2 0
> > +#define DPCS_BASE__INST2_SEG3 0
> > +#define DPCS_BASE__INST2_SEG4 0
> > +#define DPCS_BASE__INST2_SEG5 0
> > +
> > +#define DPCS_BASE__INST3_SEG0 0
> > +#define DPCS_BASE__INST3_SEG1 0
> > +#define DPCS_BASE__INST3_SEG2 0
> > +#define DPCS_BASE__INST3_SEG3 0
> > +#define DPCS_BASE__INST3_SEG4 0
> > +#define DPCS_BASE__INST3_SEG5 0
> > +
> > +#define DPCS_BASE__INST4_SEG0 0
> > +#define DPCS_BASE__INST4_SEG1 0
> > +#define DPCS_BASE__INST4_SEG2 0
> > +#define DPCS_BASE__INST4_SEG3 0
> > +#define DPCS_BASE__INST4_SEG4 0
> > +#define DPCS_BASE__INST4_SEG5 0
> > +
> > +#define DPCS_BASE__INST5_SEG0 0
> > +#define DPCS_BASE__INST5_SEG1 0
> > +#define DPCS_BASE__INST5_SEG2 0
> > +#define DPCS_BASE__INST5_SEG3 0
> > +#define DPCS_BASE__INST5_SEG4 0
> > +#define DPCS_BASE__INST5_SEG5 0
> > +
> > +#define DPCS_BASE__INST6_SEG0 0
> > +#define DPCS_BASE__INST6_SEG1 0
> > +#define DPCS_BASE__INST6_SEG2 0
> > +#define DPCS_BASE__INST6_SEG3 0
> > +#define DPCS_BASE__INST6_SEG4 0
> > +#define DPCS_BASE__INST6_SEG5 0
> > +
> > +#define DPCS_BASE__INST7_SEG0 0
> > +#define DPCS_BASE__INST7_SEG1 0
> > +#define DPCS_BASE__INST7_SEG2 0
> > +#define DPCS_BASE__INST7_SEG3 0
> > +#define DPCS_BASE__INST7_SEG4 0
> > +#define DPCS_BASE__INST7_SEG5 0
> > +
> > +#define FCH_BASE__INST0_SEG0 0x0240C000
> > +#define FCH_BASE__INST0_SEG1 0x00B40000
> > +#define FCH_BASE__INST0_SEG2 0x11000000
> > +#define FCH_BASE__INST0_SEG3 0
> > +#define FCH_BASE__INST0_SEG4 0
> > +#define FCH_BASE__INST0_SEG5 0
> > +
> > +#define FCH_BASE__INST1_SEG0 0
> > +#define FCH_BASE__INST1_SEG1 0
> > +#define FCH_BASE__INST1_SEG2 0
> > +#define FCH_BASE__INST1_SEG3 0
> > +#define FCH_BASE__INST1_SEG4 0
> > +#define FCH_BASE__INST1_SEG5 0
> > +
> > +#define FCH_BASE__INST2_SEG0 0
> > +#define FCH_BASE__INST2_SEG1 0
> > +#define FCH_BASE__INST2_SEG2 0
> > +#define FCH_BASE__INST2_SEG3 0
> > +#define FCH_BASE__INST2_SEG4 0
> > +#define FCH_BASE__INST2_SEG5 0
> > +
> > +#define FCH_BASE__INST3_SEG0 0
> > +#define FCH_BASE__INST3_SEG1 0
> > +#define FCH_BASE__INST3_SEG2 0
> > +#define FCH_BASE__INST3_SEG3 0
> > +#define FCH_BASE__INST3_SEG4 0
> > +#define FCH_BASE__INST3_SEG5 0
> > +
> > +#define FCH_BASE__INST4_SEG0 0
> > +#define FCH_BASE__INST4_SEG1 0
> > +#define FCH_BASE__INST4_SEG2 0
> > +#define FCH_BASE__INST4_SEG3 0
> > +#define FCH_BASE__INST4_SEG4 0
> > +#define FCH_BASE__INST4_SEG5 0
> > +
> > +#define FCH_BASE__INST5_SEG0 0
> > +#define FCH_BASE__INST5_SEG1 0
> > +#define FCH_BASE__INST5_SEG2 0
> > +#define FCH_BASE__INST5_SEG3 0
> > +#define FCH_BASE__INST5_SEG4 0
> > +#define FCH_BASE__INST5_SEG5 0
> > +
> > +#define FCH_BASE__INST6_SEG0 0
> > +#define FCH_BASE__INST6_SEG1 0
> > +#define FCH_BASE__INST6_SEG2 0
> > +#define FCH_BASE__INST6_SEG3 0
> > +#define FCH_BASE__INST6_SEG4 0
> > +#define FCH_BASE__INST6_SEG5 0
> > +
> > +#define FCH_BASE__INST7_SEG0 0
> > +#define FCH_BASE__INST7_SEG1 0
> > +#define FCH_BASE__INST7_SEG2 0
> > +#define FCH_BASE__INST7_SEG3 0
> > +#define FCH_BASE__INST7_SEG4 0
> > +#define FCH_BASE__INST7_SEG5 0
> > +
> > +#define FUSE_BASE__INST0_SEG0 0x00017400
> > +#define FUSE_BASE__INST0_SEG1 0x02401400
> > +#define FUSE_BASE__INST0_SEG2 0
> > +#define FUSE_BASE__INST0_SEG3 0
> > +#define FUSE_BASE__INST0_SEG4 0
> > +#define FUSE_BASE__INST0_SEG5 0
> > +
> > +#define FUSE_BASE__INST1_SEG0 0
> > +#define FUSE_BASE__INST1_SEG1 0
> > +#define FUSE_BASE__INST1_SEG2 0
> > +#define FUSE_BASE__INST1_SEG3 0
> > +#define FUSE_BASE__INST1_SEG4 0
> > +#define FUSE_BASE__INST1_SEG5 0
> > +
> > +#define FUSE_BASE__INST2_SEG0 0
> > +#define FUSE_BASE__INST2_SEG1 0
> > +#define FUSE_BASE__INST2_SEG2 0
> > +#define FUSE_BASE__INST2_SEG3 0
> > +#define FUSE_BASE__INST2_SEG4 0
> > +#define FUSE_BASE__INST2_SEG5 0
> > +
> > +#define FUSE_BASE__INST3_SEG0 0
> > +#define FUSE_BASE__INST3_SEG1 0
> > +#define FUSE_BASE__INST3_SEG2 0
> > +#define FUSE_BASE__INST3_SEG3 0
> > +#define FUSE_BASE__INST3_SEG4 0
> > +#define FUSE_BASE__INST3_SEG5 0
> > +
> > +#define FUSE_BASE__INST4_SEG0 0
> > +#define FUSE_BASE__INST4_SEG1 0
> > +#define FUSE_BASE__INST4_SEG2 0
> > +#define FUSE_BASE__INST4_SEG3 0
> > +#define FUSE_BASE__INST4_SEG4 0
> > +#define FUSE_BASE__INST4_SEG5 0
> > +
> > +#define FUSE_BASE__INST5_SEG0 0
> > +#define FUSE_BASE__INST5_SEG1 0
> > +#define FUSE_BASE__INST5_SEG2 0
> > +#define FUSE_BASE__INST5_SEG3 0
> > +#define FUSE_BASE__INST5_SEG4 0
> > +#define FUSE_BASE__INST5_SEG5 0
> > +
> > +#define FUSE_BASE__INST6_SEG0 0
> > +#define FUSE_BASE__INST6_SEG1 0
> > +#define FUSE_BASE__INST6_SEG2 0
> > +#define FUSE_BASE__INST6_SEG3 0
> > +#define FUSE_BASE__INST6_SEG4 0
> > +#define FUSE_BASE__INST6_SEG5 0
> > +
> > +#define FUSE_BASE__INST7_SEG0 0
> > +#define FUSE_BASE__INST7_SEG1 0
> > +#define FUSE_BASE__INST7_SEG2 0
> > +#define FUSE_BASE__INST7_SEG3 0
> > +#define FUSE_BASE__INST7_SEG4 0
> > +#define FUSE_BASE__INST7_SEG5 0
> > +
> > +#define GC_BASE__INST0_SEG0 0x00001260
> > +#define GC_BASE__INST0_SEG1 0x0000A000
> > +#define GC_BASE__INST0_SEG2 0x02402C00
> > +#define GC_BASE__INST0_SEG3 0
> > +#define GC_BASE__INST0_SEG4 0
> > +#define GC_BASE__INST0_SEG5 0
> > +
> > +#define GC_BASE__INST1_SEG0 0
> > +#define GC_BASE__INST1_SEG1 0
> > +#define GC_BASE__INST1_SEG2 0
> > +#define GC_BASE__INST1_SEG3 0
> > +#define GC_BASE__INST1_SEG4 0
> > +#define GC_BASE__INST1_SEG5 0
> > +
> > +#define GC_BASE__INST2_SEG0 0
> > +#define GC_BASE__INST2_SEG1 0
> > +#define GC_BASE__INST2_SEG2 0
> > +#define GC_BASE__INST2_SEG3 0
> > +#define GC_BASE__INST2_SEG4 0
> > +#define GC_BASE__INST2_SEG5 0
> > +
> > +#define GC_BASE__INST3_SEG0 0
> > +#define GC_BASE__INST3_SEG1 0
> > +#define GC_BASE__INST3_SEG2 0
> > +#define GC_BASE__INST3_SEG3 0
> > +#define GC_BASE__INST3_SEG4 0
> > +#define GC_BASE__INST3_SEG5 0
> > +
> > +#define GC_BASE__INST4_SEG0 0
> > +#define GC_BASE__INST4_SEG1 0
> > +#define GC_BASE__INST4_SEG2 0
> > +#define GC_BASE__INST4_SEG3 0
> > +#define GC_BASE__INST4_SEG4 0
> > +#define GC_BASE__INST4_SEG5 0
> > +
> > +#define GC_BASE__INST5_SEG0 0
> > +#define GC_BASE__INST5_SEG1 0
> > +#define GC_BASE__INST5_SEG2 0
> > +#define GC_BASE__INST5_SEG3 0
> > +#define GC_BASE__INST5_SEG4 0
> > +#define GC_BASE__INST5_SEG5 0
> > +
> > +#define GC_BASE__INST6_SEG0 0
> > +#define GC_BASE__INST6_SEG1 0
> > +#define GC_BASE__INST6_SEG2 0
> > +#define GC_BASE__INST6_SEG3 0
> > +#define GC_BASE__INST6_SEG4 0
> > +#define GC_BASE__INST6_SEG5 0
> > +
> > +#define GC_BASE__INST7_SEG0 0
> > +#define GC_BASE__INST7_SEG1 0
> > +#define GC_BASE__INST7_SEG2 0
> > +#define GC_BASE__INST7_SEG3 0
> > +#define GC_BASE__INST7_SEG4 0
> > +#define GC_BASE__INST7_SEG5 0
> > +
> > +#define HDP_BASE__INST0_SEG0 0x00000F20
> > +#define HDP_BASE__INST0_SEG1 0x0240A400
> > +#define HDP_BASE__INST0_SEG2 0
> > +#define HDP_BASE__INST0_SEG3 0
> > +#define HDP_BASE__INST0_SEG4 0
> > +#define HDP_BASE__INST0_SEG5 0
> > +
> > +#define HDP_BASE__INST1_SEG0 0
> > +#define HDP_BASE__INST1_SEG1 0
> > +#define HDP_BASE__INST1_SEG2 0
> > +#define HDP_BASE__INST1_SEG3 0
> > +#define HDP_BASE__INST1_SEG4 0
> > +#define HDP_BASE__INST1_SEG5 0
> > +
> > +#define HDP_BASE__INST2_SEG0 0
> > +#define HDP_BASE__INST2_SEG1 0
> > +#define HDP_BASE__INST2_SEG2 0
> > +#define HDP_BASE__INST2_SEG3 0
> > +#define HDP_BASE__INST2_SEG4 0
> > +#define HDP_BASE__INST2_SEG5 0
> > +
> > +#define HDP_BASE__INST3_SEG0 0
> > +#define HDP_BASE__INST3_SEG1 0
> > +#define HDP_BASE__INST3_SEG2 0
> > +#define HDP_BASE__INST3_SEG3 0
> > +#define HDP_BASE__INST3_SEG4 0
> > +#define HDP_BASE__INST3_SEG5 0
> > +
> > +#define HDP_BASE__INST4_SEG0 0
> > +#define HDP_BASE__INST4_SEG1 0
> > +#define HDP_BASE__INST4_SEG2 0
> > +#define HDP_BASE__INST4_SEG3 0
> > +#define HDP_BASE__INST4_SEG4 0
> > +#define HDP_BASE__INST4_SEG5 0
> > +
> > +#define HDP_BASE__INST5_SEG0 0
> > +#define HDP_BASE__INST5_SEG1 0
> > +#define HDP_BASE__INST5_SEG2 0
> > +#define HDP_BASE__INST5_SEG3 0
> > +#define HDP_BASE__INST5_SEG4 0
> > +#define HDP_BASE__INST5_SEG5 0
> > +
> > +#define HDP_BASE__INST6_SEG0 0
> > +#define HDP_BASE__INST6_SEG1 0
> > +#define HDP_BASE__INST6_SEG2 0
> > +#define HDP_BASE__INST6_SEG3 0
> > +#define HDP_BASE__INST6_SEG4 0
> > +#define HDP_BASE__INST6_SEG5 0
> > +
> > +#define HDP_BASE__INST7_SEG0 0
> > +#define HDP_BASE__INST7_SEG1 0
> > +#define HDP_BASE__INST7_SEG2 0
> > +#define HDP_BASE__INST7_SEG3 0
> > +#define HDP_BASE__INST7_SEG4 0
> > +#define HDP_BASE__INST7_SEG5 0
> > +
> > +#define ISP_BASE__INST0_SEG0 0x00018000
> > +#define ISP_BASE__INST0_SEG1 0x0240B000
> > +#define ISP_BASE__INST0_SEG2 0
> > +#define ISP_BASE__INST0_SEG3 0
> > +#define ISP_BASE__INST0_SEG4 0
> > +#define ISP_BASE__INST0_SEG5 0
> > +
> > +#define ISP_BASE__INST1_SEG0 0
> > +#define ISP_BASE__INST1_SEG1 0
> > +#define ISP_BASE__INST1_SEG2 0
> > +#define ISP_BASE__INST1_SEG3 0
> > +#define ISP_BASE__INST1_SEG4 0
> > +#define ISP_BASE__INST1_SEG5 0
> > +
> > +#define ISP_BASE__INST2_SEG0 0
> > +#define ISP_BASE__INST2_SEG1 0
> > +#define ISP_BASE__INST2_SEG2 0
> > +#define ISP_BASE__INST2_SEG3 0
> > +#define ISP_BASE__INST2_SEG4 0
> > +#define ISP_BASE__INST2_SEG5 0
> > +
> > +#define ISP_BASE__INST3_SEG0 0
> > +#define ISP_BASE__INST3_SEG1 0
> > +#define ISP_BASE__INST3_SEG2 0
> > +#define ISP_BASE__INST3_SEG3 0
> > +#define ISP_BASE__INST3_SEG4 0
> > +#define ISP_BASE__INST3_SEG5 0
> > +
> > +#define ISP_BASE__INST4_SEG0 0
> > +#define ISP_BASE__INST4_SEG1 0
> > +#define ISP_BASE__INST4_SEG2 0
> > +#define ISP_BASE__INST4_SEG3 0
> > +#define ISP_BASE__INST4_SEG4 0
> > +#define ISP_BASE__INST4_SEG5 0
> > +
> > +#define ISP_BASE__INST5_SEG0 0
> > +#define ISP_BASE__INST5_SEG1 0
> > +#define ISP_BASE__INST5_SEG2 0
> > +#define ISP_BASE__INST5_SEG3 0
> > +#define ISP_BASE__INST5_SEG4 0
> > +#define ISP_BASE__INST5_SEG5 0
> > +
> > +#define ISP_BASE__INST6_SEG0 0
> > +#define ISP_BASE__INST6_SEG1 0
> > +#define ISP_BASE__INST6_SEG2 0
> > +#define ISP_BASE__INST6_SEG3 0
> > +#define ISP_BASE__INST6_SEG4 0
> > +#define ISP_BASE__INST6_SEG5 0
> > +
> > +#define ISP_BASE__INST7_SEG0 0
> > +#define ISP_BASE__INST7_SEG1 0
> > +#define ISP_BASE__INST7_SEG2 0
> > +#define ISP_BASE__INST7_SEG3 0
> > +#define ISP_BASE__INST7_SEG4 0
> > +#define ISP_BASE__INST7_SEG5 0
> > +
> > +#define MMHUB_BASE__INST0_SEG0 0x00013200
> > +#define MMHUB_BASE__INST0_SEG1 0x0001A000
> > +#define MMHUB_BASE__INST0_SEG2 0x02408800
> > +#define MMHUB_BASE__INST0_SEG3 0
> > +#define MMHUB_BASE__INST0_SEG4 0
> > +#define MMHUB_BASE__INST0_SEG5 0
> > +
> > +#define MMHUB_BASE__INST1_SEG0 0
> > +#define MMHUB_BASE__INST1_SEG1 0
> > +#define MMHUB_BASE__INST1_SEG2 0
> > +#define MMHUB_BASE__INST1_SEG3 0
> > +#define MMHUB_BASE__INST1_SEG4 0
> > +#define MMHUB_BASE__INST1_SEG5 0
> > +
> > +#define MMHUB_BASE__INST2_SEG0 0
> > +#define MMHUB_BASE__INST2_SEG1 0
> > +#define MMHUB_BASE__INST2_SEG2 0
> > +#define MMHUB_BASE__INST2_SEG3 0
> > +#define MMHUB_BASE__INST2_SEG4 0
> > +#define MMHUB_BASE__INST2_SEG5 0
> > +
> > +#define MMHUB_BASE__INST3_SEG0 0
> > +#define MMHUB_BASE__INST3_SEG1 0
> > +#define MMHUB_BASE__INST3_SEG2 0
> > +#define MMHUB_BASE__INST3_SEG3 0
> > +#define MMHUB_BASE__INST3_SEG4 0
> > +#define MMHUB_BASE__INST3_SEG5 0
> > +
> > +#define MMHUB_BASE__INST4_SEG0 0
> > +#define MMHUB_BASE__INST4_SEG1 0
> > +#define MMHUB_BASE__INST4_SEG2 0
> > +#define MMHUB_BASE__INST4_SEG3 0
> > +#define MMHUB_BASE__INST4_SEG4 0
> > +#define MMHUB_BASE__INST4_SEG5 0
> > +
> > +#define MMHUB_BASE__INST5_SEG0 0
> > +#define MMHUB_BASE__INST5_SEG1 0
> > +#define MMHUB_BASE__INST5_SEG2 0
> > +#define MMHUB_BASE__INST5_SEG3 0
> > +#define MMHUB_BASE__INST5_SEG4 0
> > +#define MMHUB_BASE__INST5_SEG5 0
> > +
> > +#define MMHUB_BASE__INST6_SEG0 0
> > +#define MMHUB_BASE__INST6_SEG1 0
> > +#define MMHUB_BASE__INST6_SEG2 0
> > +#define MMHUB_BASE__INST6_SEG3 0
> > +#define MMHUB_BASE__INST6_SEG4 0
> > +#define MMHUB_BASE__INST6_SEG5 0
> > +
> > +#define MMHUB_BASE__INST7_SEG0 0
> > +#define MMHUB_BASE__INST7_SEG1 0
> > +#define MMHUB_BASE__INST7_SEG2 0
> > +#define MMHUB_BASE__INST7_SEG3 0
> > +#define MMHUB_BASE__INST7_SEG4 0
> > +#define MMHUB_BASE__INST7_SEG5 0
> > +
> > +#define MP0_BASE__INST0_SEG0 0x00016000
> > +#define MP0_BASE__INST0_SEG1 0x0243FC00
> > +#define MP0_BASE__INST0_SEG2 0x00DC0000
> > +#define MP0_BASE__INST0_SEG3 0x00E00000
> > +#define MP0_BASE__INST0_SEG4 0x00E40000
> > +#define MP0_BASE__INST0_SEG5 0
> > +
> > +#define MP0_BASE__INST1_SEG0 0
> > +#define MP0_BASE__INST1_SEG1 0
> > +#define MP0_BASE__INST1_SEG2 0
> > +#define MP0_BASE__INST1_SEG3 0
> > +#define MP0_BASE__INST1_SEG4 0
> > +#define MP0_BASE__INST1_SEG5 0
> > +
> > +#define MP0_BASE__INST2_SEG0 0
> > +#define MP0_BASE__INST2_SEG1 0
> > +#define MP0_BASE__INST2_SEG2 0
> > +#define MP0_BASE__INST2_SEG3 0
> > +#define MP0_BASE__INST2_SEG4 0
> > +#define MP0_BASE__INST2_SEG5 0
> > +
> > +#define MP0_BASE__INST3_SEG0 0
> > +#define MP0_BASE__INST3_SEG1 0
> > +#define MP0_BASE__INST3_SEG2 0
> > +#define MP0_BASE__INST3_SEG3 0
> > +#define MP0_BASE__INST3_SEG4 0
> > +#define MP0_BASE__INST3_SEG5 0
> > +
> > +#define MP0_BASE__INST4_SEG0 0
> > +#define MP0_BASE__INST4_SEG1 0
> > +#define MP0_BASE__INST4_SEG2 0
> > +#define MP0_BASE__INST4_SEG3 0
> > +#define MP0_BASE__INST4_SEG4 0
> > +#define MP0_BASE__INST4_SEG5 0
> > +
> > +#define MP0_BASE__INST5_SEG0 0
> > +#define MP0_BASE__INST5_SEG1 0
> > +#define MP0_BASE__INST5_SEG2 0
> > +#define MP0_BASE__INST5_SEG3 0
> > +#define MP0_BASE__INST5_SEG4 0
> > +#define MP0_BASE__INST5_SEG5 0
> > +
> > +#define MP0_BASE__INST6_SEG0 0
> > +#define MP0_BASE__INST6_SEG1 0
> > +#define MP0_BASE__INST6_SEG2 0
> > +#define MP0_BASE__INST6_SEG3 0
> > +#define MP0_BASE__INST6_SEG4 0
> > +#define MP0_BASE__INST6_SEG5 0
> > +
> > +#define MP0_BASE__INST7_SEG0 0
> > +#define MP0_BASE__INST7_SEG1 0
> > +#define MP0_BASE__INST7_SEG2 0
> > +#define MP0_BASE__INST7_SEG3 0
> > +#define MP0_BASE__INST7_SEG4 0
> > +#define MP0_BASE__INST7_SEG5 0
> > +
> > +#define MP1_BASE__INST0_SEG0 0x00016000
> > +#define MP1_BASE__INST0_SEG1 0x0243FC00
> > +#define MP1_BASE__INST0_SEG2 0x00DC0000
> > +#define MP1_BASE__INST0_SEG3 0x00E00000
> > +#define MP1_BASE__INST0_SEG4 0x00E40000
> > +#define MP1_BASE__INST0_SEG5 0
> > +
> > +#define MP1_BASE__INST1_SEG0 0
> > +#define MP1_BASE__INST1_SEG1 0
> > +#define MP1_BASE__INST1_SEG2 0
> > +#define MP1_BASE__INST1_SEG3 0
> > +#define MP1_BASE__INST1_SEG4 0
> > +#define MP1_BASE__INST1_SEG5 0
> > +
> > +#define MP1_BASE__INST2_SEG0 0
> > +#define MP1_BASE__INST2_SEG1 0
> > +#define MP1_BASE__INST2_SEG2 0
> > +#define MP1_BASE__INST2_SEG3 0
> > +#define MP1_BASE__INST2_SEG4 0
> > +#define MP1_BASE__INST2_SEG5 0
> > +
> > +#define MP1_BASE__INST3_SEG0 0
> > +#define MP1_BASE__INST3_SEG1 0
> > +#define MP1_BASE__INST3_SEG2 0
> > +#define MP1_BASE__INST3_SEG3 0
> > +#define MP1_BASE__INST3_SEG4 0
> > +#define MP1_BASE__INST3_SEG5 0
> > +
> > +#define MP1_BASE__INST4_SEG0 0
> > +#define MP1_BASE__INST4_SEG1 0
> > +#define MP1_BASE__INST4_SEG2 0
> > +#define MP1_BASE__INST4_SEG3 0
> > +#define MP1_BASE__INST4_SEG4 0
> > +#define MP1_BASE__INST4_SEG5 0
> > +
> > +#define MP1_BASE__INST5_SEG0 0
> > +#define MP1_BASE__INST5_SEG1 0
> > +#define MP1_BASE__INST5_SEG2 0
> > +#define MP1_BASE__INST5_SEG3 0
> > +#define MP1_BASE__INST5_SEG4 0
> > +#define MP1_BASE__INST5_SEG5 0
> > +
> > +#define MP1_BASE__INST6_SEG0 0
> > +#define MP1_BASE__INST6_SEG1 0
> > +#define MP1_BASE__INST6_SEG2 0
> > +#define MP1_BASE__INST6_SEG3 0
> > +#define MP1_BASE__INST6_SEG4 0
> > +#define MP1_BASE__INST6_SEG5 0
> > +
> > +#define MP1_BASE__INST7_SEG0 0
> > +#define MP1_BASE__INST7_SEG1 0
> > +#define MP1_BASE__INST7_SEG2 0
> > +#define MP1_BASE__INST7_SEG3 0
> > +#define MP1_BASE__INST7_SEG4 0
> > +#define MP1_BASE__INST7_SEG5 0
> > +
> > +#define MP2_BASE__INST0_SEG0 0x00016400
> > +#define MP2_BASE__INST0_SEG1 0x02400800
> > +#define MP2_BASE__INST0_SEG2 0x00F40000
> > +#define MP2_BASE__INST0_SEG3 0x00F80000
> > +#define MP2_BASE__INST0_SEG4 0x00FC0000
> > +#define MP2_BASE__INST0_SEG5 0
> > +
> > +#define MP2_BASE__INST1_SEG0 0
> > +#define MP2_BASE__INST1_SEG1 0
> > +#define MP2_BASE__INST1_SEG2 0
> > +#define MP2_BASE__INST1_SEG3 0
> > +#define MP2_BASE__INST1_SEG4 0
> > +#define MP2_BASE__INST1_SEG5 0
> > +
> > +#define MP2_BASE__INST2_SEG0 0
> > +#define MP2_BASE__INST2_SEG1 0
> > +#define MP2_BASE__INST2_SEG2 0
> > +#define MP2_BASE__INST2_SEG3 0
> > +#define MP2_BASE__INST2_SEG4 0
> > +#define MP2_BASE__INST2_SEG5 0
> > +
> > +#define MP2_BASE__INST3_SEG0 0
> > +#define MP2_BASE__INST3_SEG1 0
> > +#define MP2_BASE__INST3_SEG2 0
> > +#define MP2_BASE__INST3_SEG3 0
> > +#define MP2_BASE__INST3_SEG4 0
> > +#define MP2_BASE__INST3_SEG5 0
> > +
> > +#define MP2_BASE__INST4_SEG0 0
> > +#define MP2_BASE__INST4_SEG1 0
> > +#define MP2_BASE__INST4_SEG2 0
> > +#define MP2_BASE__INST4_SEG3 0
> > +#define MP2_BASE__INST4_SEG4 0
> > +#define MP2_BASE__INST4_SEG5 0
> > +
> > +#define MP2_BASE__INST5_SEG0 0
> > +#define MP2_BASE__INST5_SEG1 0
> > +#define MP2_BASE__INST5_SEG2 0
> > +#define MP2_BASE__INST5_SEG3 0
> > +#define MP2_BASE__INST5_SEG4 0
> > +#define MP2_BASE__INST5_SEG5 0
> > +
> > +#define MP2_BASE__INST6_SEG0 0
> > +#define MP2_BASE__INST6_SEG1 0
> > +#define MP2_BASE__INST6_SEG2 0
> > +#define MP2_BASE__INST6_SEG3 0
> > +#define MP2_BASE__INST6_SEG4 0
> > +#define MP2_BASE__INST6_SEG5 0
> > +
> > +#define MP2_BASE__INST7_SEG0 0
> > +#define MP2_BASE__INST7_SEG1 0
> > +#define MP2_BASE__INST7_SEG2 0
> > +#define MP2_BASE__INST7_SEG3 0
> > +#define MP2_BASE__INST7_SEG4 0
> > +#define MP2_BASE__INST7_SEG5 0
> > +
> > +#define NBIO_BASE__INST0_SEG0 0x00000000
> > +#define NBIO_BASE__INST0_SEG1 0x00000014
> > +#define NBIO_BASE__INST0_SEG2 0x00000D20
> > +#define NBIO_BASE__INST0_SEG3 0x00010400
> > +#define NBIO_BASE__INST0_SEG4 0x0241B000
> > +#define NBIO_BASE__INST0_SEG5 0x04040000
> > +
> > +#define NBIO_BASE__INST1_SEG0 0
> > +#define NBIO_BASE__INST1_SEG1 0
> > +#define NBIO_BASE__INST1_SEG2 0
> > +#define NBIO_BASE__INST1_SEG3 0
> > +#define NBIO_BASE__INST1_SEG4 0
> > +#define NBIO_BASE__INST1_SEG5 0
> > +
> > +#define NBIO_BASE__INST2_SEG0 0
> > +#define NBIO_BASE__INST2_SEG1 0
> > +#define NBIO_BASE__INST2_SEG2 0
> > +#define NBIO_BASE__INST2_SEG3 0
> > +#define NBIO_BASE__INST2_SEG4 0
> > +#define NBIO_BASE__INST2_SEG5 0
> > +
> > +#define NBIO_BASE__INST3_SEG0 0
> > +#define NBIO_BASE__INST3_SEG1 0
> > +#define NBIO_BASE__INST3_SEG2 0
> > +#define NBIO_BASE__INST3_SEG3 0
> > +#define NBIO_BASE__INST3_SEG4 0
> > +#define NBIO_BASE__INST3_SEG5 0
> > +
> > +#define NBIO_BASE__INST4_SEG0 0
> > +#define NBIO_BASE__INST4_SEG1 0
> > +#define NBIO_BASE__INST4_SEG2 0
> > +#define NBIO_BASE__INST4_SEG3 0
> > +#define NBIO_BASE__INST4_SEG4 0
> > +#define NBIO_BASE__INST4_SEG5 0
> > +
> > +#define NBIO_BASE__INST5_SEG0 0
> > +#define NBIO_BASE__INST5_SEG1 0
> > +#define NBIO_BASE__INST5_SEG2 0
> > +#define NBIO_BASE__INST5_SEG3 0
> > +#define NBIO_BASE__INST5_SEG4 0
> > +#define NBIO_BASE__INST5_SEG5 0
> > +
> > +#define NBIO_BASE__INST6_SEG0 0
> > +#define NBIO_BASE__INST6_SEG1 0
> > +#define NBIO_BASE__INST6_SEG2 0
> > +#define NBIO_BASE__INST6_SEG3 0
> > +#define NBIO_BASE__INST6_SEG4 0
> > +#define NBIO_BASE__INST6_SEG5 0
> > +
> > +#define NBIO_BASE__INST7_SEG0 0
> > +#define NBIO_BASE__INST7_SEG1 0
> > +#define NBIO_BASE__INST7_SEG2 0
> > +#define NBIO_BASE__INST7_SEG3 0
> > +#define NBIO_BASE__INST7_SEG4 0
> > +#define NBIO_BASE__INST7_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> > +#define OSSSYS_BASE__INST0_SEG1 0x0240A000
> > +#define OSSSYS_BASE__INST0_SEG2 0
> > +#define OSSSYS_BASE__INST0_SEG3 0
> > +#define OSSSYS_BASE__INST0_SEG4 0
> > +#define OSSSYS_BASE__INST0_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST1_SEG0 0
> > +#define OSSSYS_BASE__INST1_SEG1 0
> > +#define OSSSYS_BASE__INST1_SEG2 0
> > +#define OSSSYS_BASE__INST1_SEG3 0
> > +#define OSSSYS_BASE__INST1_SEG4 0
> > +#define OSSSYS_BASE__INST1_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST2_SEG0 0
> > +#define OSSSYS_BASE__INST2_SEG1 0
> > +#define OSSSYS_BASE__INST2_SEG2 0
> > +#define OSSSYS_BASE__INST2_SEG3 0
> > +#define OSSSYS_BASE__INST2_SEG4 0
> > +#define OSSSYS_BASE__INST2_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST3_SEG0 0
> > +#define OSSSYS_BASE__INST3_SEG1 0
> > +#define OSSSYS_BASE__INST3_SEG2 0
> > +#define OSSSYS_BASE__INST3_SEG3 0
> > +#define OSSSYS_BASE__INST3_SEG4 0
> > +#define OSSSYS_BASE__INST3_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST4_SEG0 0
> > +#define OSSSYS_BASE__INST4_SEG1 0
> > +#define OSSSYS_BASE__INST4_SEG2 0
> > +#define OSSSYS_BASE__INST4_SEG3 0
> > +#define OSSSYS_BASE__INST4_SEG4 0
> > +#define OSSSYS_BASE__INST4_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST5_SEG0 0
> > +#define OSSSYS_BASE__INST5_SEG1 0
> > +#define OSSSYS_BASE__INST5_SEG2 0
> > +#define OSSSYS_BASE__INST5_SEG3 0
> > +#define OSSSYS_BASE__INST5_SEG4 0
> > +#define OSSSYS_BASE__INST5_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST6_SEG0 0
> > +#define OSSSYS_BASE__INST6_SEG1 0
> > +#define OSSSYS_BASE__INST6_SEG2 0
> > +#define OSSSYS_BASE__INST6_SEG3 0
> > +#define OSSSYS_BASE__INST6_SEG4 0
> > +#define OSSSYS_BASE__INST6_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST7_SEG0 0
> > +#define OSSSYS_BASE__INST7_SEG1 0
> > +#define OSSSYS_BASE__INST7_SEG2 0
> > +#define OSSSYS_BASE__INST7_SEG3 0
> > +#define OSSSYS_BASE__INST7_SEG4 0
> > +#define OSSSYS_BASE__INST7_SEG5 0
> > +
> > +#define PCIE0_BASE__INST0_SEG0 0x00000000
> > +#define PCIE0_BASE__INST0_SEG1 0x00000014
> > +#define PCIE0_BASE__INST0_SEG2 0x00000D20
> > +#define PCIE0_BASE__INST0_SEG3 0x00010400
> > +#define PCIE0_BASE__INST0_SEG4 0x0241B000
> > +#define PCIE0_BASE__INST0_SEG5 0x04040000
> > +
> > +#define PCIE0_BASE__INST1_SEG0 0
> > +#define PCIE0_BASE__INST1_SEG1 0
> > +#define PCIE0_BASE__INST1_SEG2 0
> > +#define PCIE0_BASE__INST1_SEG3 0
> > +#define PCIE0_BASE__INST1_SEG4 0
> > +#define PCIE0_BASE__INST1_SEG5 0
> > +
> > +#define PCIE0_BASE__INST2_SEG0 0
> > +#define PCIE0_BASE__INST2_SEG1 0
> > +#define PCIE0_BASE__INST2_SEG2 0
> > +#define PCIE0_BASE__INST2_SEG3 0
> > +#define PCIE0_BASE__INST2_SEG4 0
> > +#define PCIE0_BASE__INST2_SEG5 0
> > +
> > +#define PCIE0_BASE__INST3_SEG0 0
> > +#define PCIE0_BASE__INST3_SEG1 0
> > +#define PCIE0_BASE__INST3_SEG2 0
> > +#define PCIE0_BASE__INST3_SEG3 0
> > +#define PCIE0_BASE__INST3_SEG4 0
> > +#define PCIE0_BASE__INST3_SEG5 0
> > +
> > +#define PCIE0_BASE__INST4_SEG0 0
> > +#define PCIE0_BASE__INST4_SEG1 0
> > +#define PCIE0_BASE__INST4_SEG2 0
> > +#define PCIE0_BASE__INST4_SEG3 0
> > +#define PCIE0_BASE__INST4_SEG4 0
> > +#define PCIE0_BASE__INST4_SEG5 0
> > +
> > +#define PCIE0_BASE__INST5_SEG0 0
> > +#define PCIE0_BASE__INST5_SEG1 0
> > +#define PCIE0_BASE__INST5_SEG2 0
> > +#define PCIE0_BASE__INST5_SEG3 0
> > +#define PCIE0_BASE__INST5_SEG4 0
> > +#define PCIE0_BASE__INST5_SEG5 0
> > +
> > +#define PCIE0_BASE__INST6_SEG0 0
> > +#define PCIE0_BASE__INST6_SEG1 0
> > +#define PCIE0_BASE__INST6_SEG2 0
> > +#define PCIE0_BASE__INST6_SEG3 0
> > +#define PCIE0_BASE__INST6_SEG4 0
> > +#define PCIE0_BASE__INST6_SEG5 0
> > +
> > +#define PCIE0_BASE__INST7_SEG0 0
> > +#define PCIE0_BASE__INST7_SEG1 0
> > +#define PCIE0_BASE__INST7_SEG2 0
> > +#define PCIE0_BASE__INST7_SEG3 0
> > +#define PCIE0_BASE__INST7_SEG4 0
> > +#define PCIE0_BASE__INST7_SEG5 0
> > +
> > +#define SMUIO_BASE__INST0_SEG0 0x00016800
> > +#define SMUIO_BASE__INST0_SEG1 0x00016A00
> > +#define SMUIO_BASE__INST0_SEG2 0x02401000
> > +#define SMUIO_BASE__INST0_SEG3 0x00440000
> > +#define SMUIO_BASE__INST0_SEG4 0
> > +#define SMUIO_BASE__INST0_SEG5 0
> > +
> > +#define SMUIO_BASE__INST1_SEG0 0x0001BC00
> > +#define SMUIO_BASE__INST1_SEG1 0x0242D400
> > +#define SMUIO_BASE__INST1_SEG2 0
> > +#define SMUIO_BASE__INST1_SEG3 0
> > +#define SMUIO_BASE__INST1_SEG4 0
> > +#define SMUIO_BASE__INST1_SEG5 0
> > +
> > +#define SMUIO_BASE__INST2_SEG0 0
> > +#define SMUIO_BASE__INST2_SEG1 0
> > +#define SMUIO_BASE__INST2_SEG2 0
> > +#define SMUIO_BASE__INST2_SEG3 0
> > +#define SMUIO_BASE__INST2_SEG4 0
> > +#define SMUIO_BASE__INST2_SEG5 0
> > +
> > +#define SMUIO_BASE__INST3_SEG0 0
> > +#define SMUIO_BASE__INST3_SEG1 0
> > +#define SMUIO_BASE__INST3_SEG2 0
> > +#define SMUIO_BASE__INST3_SEG3 0
> > +#define SMUIO_BASE__INST3_SEG4 0
> > +#define SMUIO_BASE__INST3_SEG5 0
> > +
> > +#define SMUIO_BASE__INST4_SEG0 0
> > +#define SMUIO_BASE__INST4_SEG1 0
> > +#define SMUIO_BASE__INST4_SEG2 0
> > +#define SMUIO_BASE__INST4_SEG3 0
> > +#define SMUIO_BASE__INST4_SEG4 0
> > +#define SMUIO_BASE__INST4_SEG5 0
> > +
> > +#define SMUIO_BASE__INST5_SEG0 0
> > +#define SMUIO_BASE__INST5_SEG1 0
> > +#define SMUIO_BASE__INST5_SEG2 0
> > +#define SMUIO_BASE__INST5_SEG3 0
> > +#define SMUIO_BASE__INST5_SEG4 0
> > +#define SMUIO_BASE__INST5_SEG5 0
> > +
> > +#define SMUIO_BASE__INST6_SEG0 0
> > +#define SMUIO_BASE__INST6_SEG1 0
> > +#define SMUIO_BASE__INST6_SEG2 0
> > +#define SMUIO_BASE__INST6_SEG3 0
> > +#define SMUIO_BASE__INST6_SEG4 0
> > +#define SMUIO_BASE__INST6_SEG5 0
> > +
> > +#define SMUIO_BASE__INST7_SEG0 0
> > +#define SMUIO_BASE__INST7_SEG1 0
> > +#define SMUIO_BASE__INST7_SEG2 0
> > +#define SMUIO_BASE__INST7_SEG3 0
> > +#define SMUIO_BASE__INST7_SEG4 0
> > +#define SMUIO_BASE__INST7_SEG5 0
> > +
> > +#define THM_BASE__INST0_SEG0 0x00016600
> > +#define THM_BASE__INST0_SEG1 0x02400C00
> > +#define THM_BASE__INST0_SEG2 0
> > +#define THM_BASE__INST0_SEG3 0
> > +#define THM_BASE__INST0_SEG4 0
> > +#define THM_BASE__INST0_SEG5 0
> > +
> > +#define THM_BASE__INST1_SEG0 0
> > +#define THM_BASE__INST1_SEG1 0
> > +#define THM_BASE__INST1_SEG2 0
> > +#define THM_BASE__INST1_SEG3 0
> > +#define THM_BASE__INST1_SEG4 0
> > +#define THM_BASE__INST1_SEG5 0
> > +
> > +#define THM_BASE__INST2_SEG0 0
> > +#define THM_BASE__INST2_SEG1 0
> > +#define THM_BASE__INST2_SEG2 0
> > +#define THM_BASE__INST2_SEG3 0
> > +#define THM_BASE__INST2_SEG4 0
> > +#define THM_BASE__INST2_SEG5 0
> > +
> > +#define THM_BASE__INST3_SEG0 0
> > +#define THM_BASE__INST3_SEG1 0
> > +#define THM_BASE__INST3_SEG2 0
> > +#define THM_BASE__INST3_SEG3 0
> > +#define THM_BASE__INST3_SEG4 0
> > +#define THM_BASE__INST3_SEG5 0
> > +
> > +#define THM_BASE__INST4_SEG0 0
> > +#define THM_BASE__INST4_SEG1 0
> > +#define THM_BASE__INST4_SEG2 0
> > +#define THM_BASE__INST4_SEG3 0
> > +#define THM_BASE__INST4_SEG4 0
> > +#define THM_BASE__INST4_SEG5 0
> > +
> > +#define THM_BASE__INST5_SEG0 0
> > +#define THM_BASE__INST5_SEG1 0
> > +#define THM_BASE__INST5_SEG2 0
> > +#define THM_BASE__INST5_SEG3 0
> > +#define THM_BASE__INST5_SEG4 0
> > +#define THM_BASE__INST5_SEG5 0
> > +
> > +#define THM_BASE__INST6_SEG0 0
> > +#define THM_BASE__INST6_SEG1 0
> > +#define THM_BASE__INST6_SEG2 0
> > +#define THM_BASE__INST6_SEG3 0
> > +#define THM_BASE__INST6_SEG4 0
> > +#define THM_BASE__INST6_SEG5 0
> > +
> > +#define THM_BASE__INST7_SEG0 0
> > +#define THM_BASE__INST7_SEG1 0
> > +#define THM_BASE__INST7_SEG2 0
> > +#define THM_BASE__INST7_SEG3 0
> > +#define THM_BASE__INST7_SEG4 0
> > +#define THM_BASE__INST7_SEG5 0
> > +
> > +#define UMC_BASE__INST0_SEG0 0x00014000
> > +#define UMC_BASE__INST0_SEG1 0x02425800
> > +#define UMC_BASE__INST0_SEG2 0
> > +#define UMC_BASE__INST0_SEG3 0
> > +#define UMC_BASE__INST0_SEG4 0
> > +#define UMC_BASE__INST0_SEG5 0
> > +
> > +#define UMC_BASE__INST1_SEG0 0x00054000
> > +#define UMC_BASE__INST1_SEG1 0x02425C00
> > +#define UMC_BASE__INST1_SEG2 0
> > +#define UMC_BASE__INST1_SEG3 0
> > +#define UMC_BASE__INST1_SEG4 0
> > +#define UMC_BASE__INST1_SEG5 0
> > +
> > +#define UMC_BASE__INST2_SEG0 0x00094000
> > +#define UMC_BASE__INST2_SEG1 0x02426000
> > +#define UMC_BASE__INST2_SEG2 0
> > +#define UMC_BASE__INST2_SEG3 0
> > +#define UMC_BASE__INST2_SEG4 0
> > +#define UMC_BASE__INST2_SEG5 0
> > +
> > +#define UMC_BASE__INST3_SEG0 0x000D4000
> > +#define UMC_BASE__INST3_SEG1 0x02426400
> > +#define UMC_BASE__INST3_SEG2 0
> > +#define UMC_BASE__INST3_SEG3 0
> > +#define UMC_BASE__INST3_SEG4 0
> > +#define UMC_BASE__INST3_SEG5 0
> > +
> > +#define UMC_BASE__INST4_SEG0 0
> > +#define UMC_BASE__INST4_SEG1 0
> > +#define UMC_BASE__INST4_SEG2 0
> > +#define UMC_BASE__INST4_SEG3 0
> > +#define UMC_BASE__INST4_SEG4 0
> > +#define UMC_BASE__INST4_SEG5 0
> > +
> > +#define UMC_BASE__INST5_SEG0 0
> > +#define UMC_BASE__INST5_SEG1 0
> > +#define UMC_BASE__INST5_SEG2 0
> > +#define UMC_BASE__INST5_SEG3 0
> > +#define UMC_BASE__INST5_SEG4 0
> > +#define UMC_BASE__INST5_SEG5 0
> > +
> > +#define UMC_BASE__INST6_SEG0 0
> > +#define UMC_BASE__INST6_SEG1 0
> > +#define UMC_BASE__INST6_SEG2 0
> > +#define UMC_BASE__INST6_SEG3 0
> > +#define UMC_BASE__INST6_SEG4 0
> > +#define UMC_BASE__INST6_SEG5 0
> > +
> > +#define UMC_BASE__INST7_SEG0 0
> > +#define UMC_BASE__INST7_SEG1 0
> > +#define UMC_BASE__INST7_SEG2 0
> > +#define UMC_BASE__INST7_SEG3 0
> > +#define UMC_BASE__INST7_SEG4 0
> > +#define UMC_BASE__INST7_SEG5 0
> > +
> > +#define USB_BASE__INST0_SEG0 0x0242A800
> > +#define USB_BASE__INST0_SEG1 0x05B00000
> > +#define USB_BASE__INST0_SEG2 0
> > +#define USB_BASE__INST0_SEG3 0
> > +#define USB_BASE__INST0_SEG4 0
> > +#define USB_BASE__INST0_SEG5 0
> > +
> > +#define USB_BASE__INST1_SEG0 0x0242AC00
> > +#define USB_BASE__INST1_SEG1 0x05B80000
> > +#define USB_BASE__INST1_SEG2 0
> > +#define USB_BASE__INST1_SEG3 0
> > +#define USB_BASE__INST1_SEG4 0
> > +#define USB_BASE__INST1_SEG5 0
> > +
> > +#define USB_BASE__INST2_SEG0 0x0242B000
> > +#define USB_BASE__INST2_SEG1 0x05C00000
> > +#define USB_BASE__INST2_SEG2 0
> > +#define USB_BASE__INST2_SEG3 0
> > +#define USB_BASE__INST2_SEG4 0
> > +#define USB_BASE__INST2_SEG5 0
> > +
> > +#define USB_BASE__INST3_SEG0 0
> > +#define USB_BASE__INST3_SEG1 0
> > +#define USB_BASE__INST3_SEG2 0
> > +#define USB_BASE__INST3_SEG3 0
> > +#define USB_BASE__INST3_SEG4 0
> > +#define USB_BASE__INST3_SEG5 0
> > +
> > +#define USB_BASE__INST4_SEG0 0
> > +#define USB_BASE__INST4_SEG1 0
> > +#define USB_BASE__INST4_SEG2 0
> > +#define USB_BASE__INST4_SEG3 0
> > +#define USB_BASE__INST4_SEG4 0
> > +#define USB_BASE__INST4_SEG5 0
> > +
> > +#define USB_BASE__INST5_SEG0 0
> > +#define USB_BASE__INST5_SEG1 0
> > +#define USB_BASE__INST5_SEG2 0
> > +#define USB_BASE__INST5_SEG3 0
> > +#define USB_BASE__INST5_SEG4 0
> > +#define USB_BASE__INST5_SEG5 0
> > +
> > +#define USB_BASE__INST6_SEG0 0
> > +#define USB_BASE__INST6_SEG1 0
> > +#define USB_BASE__INST6_SEG2 0
> > +#define USB_BASE__INST6_SEG3 0
> > +#define USB_BASE__INST6_SEG4 0
> > +#define USB_BASE__INST6_SEG5 0
> > +
> > +#define USB_BASE__INST7_SEG0 0
> > +#define USB_BASE__INST7_SEG1 0
> > +#define USB_BASE__INST7_SEG2 0
> > +#define USB_BASE__INST7_SEG3 0
> > +#define USB_BASE__INST7_SEG4 0
> > +#define USB_BASE__INST7_SEG5 0
> > +
> > +#define VCN_BASE__INST0_SEG0 0x00007800
> > +#define VCN_BASE__INST0_SEG1 0x00007E00
> > +#define VCN_BASE__INST0_SEG2 0x02403000
> > +#define VCN_BASE__INST0_SEG3 0
> > +#define VCN_BASE__INST0_SEG4 0
> > +#define VCN_BASE__INST0_SEG5 0
> > +
> > +#define VCN_BASE__INST1_SEG0 0
> > +#define VCN_BASE__INST1_SEG1 0
> > +#define VCN_BASE__INST1_SEG2 0
> > +#define VCN_BASE__INST1_SEG3 0
> > +#define VCN_BASE__INST1_SEG4 0
> > +#define VCN_BASE__INST1_SEG5 0
> > +
> > +#define VCN_BASE__INST2_SEG0 0
> > +#define VCN_BASE__INST2_SEG1 0
> > +#define VCN_BASE__INST2_SEG2 0
> > +#define VCN_BASE__INST2_SEG3 0
> > +#define VCN_BASE__INST2_SEG4 0
> > +#define VCN_BASE__INST2_SEG5 0
> > +
> > +#define VCN_BASE__INST3_SEG0 0
> > +#define VCN_BASE__INST3_SEG1 0
> > +#define VCN_BASE__INST3_SEG2 0
> > +#define VCN_BASE__INST3_SEG3 0
> > +#define VCN_BASE__INST3_SEG4 0
> > +#define VCN_BASE__INST3_SEG5 0
> > +
> > +#define VCN_BASE__INST4_SEG0 0
> > +#define VCN_BASE__INST4_SEG1 0
> > +#define VCN_BASE__INST4_SEG2 0
> > +#define VCN_BASE__INST4_SEG3 0
> > +#define VCN_BASE__INST4_SEG4 0
> > +#define VCN_BASE__INST4_SEG5 0
> > +
> > +#define VCN_BASE__INST5_SEG0 0
> > +#define VCN_BASE__INST5_SEG1 0
> > +#define VCN_BASE__INST5_SEG2 0
> > +#define VCN_BASE__INST5_SEG3 0
> > +#define VCN_BASE__INST5_SEG4 0
> > +#define VCN_BASE__INST5_SEG5 0
> > +
> > +#define VCN_BASE__INST6_SEG0 0
> > +#define VCN_BASE__INST6_SEG1 0
> > +#define VCN_BASE__INST6_SEG2 0
> > +#define VCN_BASE__INST6_SEG3 0
> > +#define VCN_BASE__INST6_SEG4 0
> > +#define VCN_BASE__INST6_SEG5 0
> > +
> > +#define VCN_BASE__INST7_SEG0 0
> > +#define VCN_BASE__INST7_SEG1 0
> > +#define VCN_BASE__INST7_SEG2 0
> > +#define VCN_BASE__INST7_SEG3 0
> > +#define VCN_BASE__INST7_SEG4 0
> > +#define VCN_BASE__INST7_SEG5 0
> > +
> > +#endif
> >
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-29 14:57 ` Alex Deucher
@ 2020-09-29 18:59 ` Luben Tuikov
2020-09-29 20:15 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-29 18:59 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On 2020-09-29 10:57 a.m., Alex Deucher wrote:
>>> +#ifndef __VANGOGH_IP_OFFSET_H__
>>> +#define __VANGOGH_IP_OFFSET_H__
>>> +
>>> +#define MAX_INSTANCE 8
>>> +#define MAX_SEGMENT 6
>> No. No "max". Use "num" instead, as:
>>
>> #define NUM_INSTANCE 8
>> #define NUM_SEGMENT 6
>>
>> To mean, the _number_ of instances and the _number_ of
>> segments. (Their count is a number.)
>>
>> A "maximum" (similarly "minimum") value is an _attainable_ value,
>> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
>> and thus max instance can never be attained.
>>
>> It is the count, the number of instances (segments, wlg),
>> not the maximum instance. The maximum instance is 7,
>> the minimum instance is 0. Similarly for segments.
> Valid point, but this file is shared across components so I'd like to
> minimize the differences.
>
Is it possible to educate the organization?
Is it possible for knowledge to flow backwards,
i.e. from the Linux team back in?
As a mathematician, this really, really bothers me.
It leaves traces of badly named objects and new people reading
it would pick this bad naming up, and experienced people would
either be confused or find it incorrect.
Let's fix this at the source.
Regards,
Luben
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-29 18:59 ` Luben Tuikov
@ 2020-09-29 20:15 ` Alex Deucher
0 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 20:15 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Tue, Sep 29, 2020 at 2:59 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-29 10:57 a.m., Alex Deucher wrote:
> >>> +#ifndef __VANGOGH_IP_OFFSET_H__
> >>> +#define __VANGOGH_IP_OFFSET_H__
> >>> +
> >>> +#define MAX_INSTANCE 8
> >>> +#define MAX_SEGMENT 6
> >> No. No "max". Use "num" instead, as:
> >>
> >> #define NUM_INSTANCE 8
> >> #define NUM_SEGMENT 6
> >>
> >> To mean, the _number_ of instances and the _number_ of
> >> segments. (Their count is a number.)
> >>
> >> A "maximum" (similarly "minimum") value is an _attainable_ value,
> >> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
> >> and thus max instance can never be attained.
> >>
> >> It is the count, the number of instances (segments, wlg),
> >> not the maximum instance. The maximum instance is 7,
> >> the minimum instance is 0. Similarly for segments.
> > Valid point, but this file is shared across components so I'd like to
> > minimize the differences.
> >
>
> Is it possible to educate the organization?
>
> Is it possible for knowledge to flow backwards,
> i.e. from the Linux team back in?
>
> As a mathematician, this really, really bothers me.
>
> It leaves traces of badly named objects and new people reading
> it would pick this bad naming up, and experienced people would
> either be confused or find it incorrect.
>
> Let's fix this at the source.
We can take it up with the internal teams that generate these files.
Alex
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 06/45] drm/amdgpu: add nv common ip block support for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (3 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-28 20:50 ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Alex Deucher
` (38 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds common ip support for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index bc894cfba60c..2077f897d6eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -478,6 +478,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER:
sienna_cichlid_reg_base_init(adev);
break;
+ case CHIP_VANGOGH:
+ vangogh_reg_base_init(adev);
+ break;
default:
return -EINVAL;
}
@@ -858,6 +861,11 @@ static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x32;
break;
+ case CHIP_VANGOGH:
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x01;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 06/45] drm/amdgpu: add nv common ip block support for van gogh
2020-09-25 20:09 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
@ 2020-09-28 20:50 ` Luben Tuikov
0 siblings, 0 replies; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 20:50 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> This patch adds common ip support for van gogh.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index bc894cfba60c..2077f897d6eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -478,6 +478,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
> case CHIP_NAVY_FLOUNDER:
> sienna_cichlid_reg_base_init(adev);
> break;
> + case CHIP_VANGOGH:
> + vangogh_reg_base_init(adev);
> + break;
That's gonna throw a warning when compiled, since you're not
collecting the return value. As per my email to the previous
patch in this sequence, define this function as "void".
Regards,
Luben
> default:
> return -EINVAL;
> }
> @@ -858,6 +861,11 @@ static int nv_common_early_init(void *handle)
> adev->external_rev_id = adev->rev_id + 0x32;
> break;
>
> + case CHIP_VANGOGH:
> + adev->cg_flags = 0;
> + adev->pg_flags = 0;
> + adev->external_rev_id = adev->rev_id + 0x01;
> + break;
> default:
> /* FIXME: not supported yet */
> return -EINVAL;
>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (4 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-28 20:52 ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 08/45] drm/amdgpu: add van gogh support for ih block Alex Deucher
` (37 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Van gogh only has one sdma.
v2: use num_instances rather than APU flag
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2077f897d6eb..8616d397da00 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -289,7 +289,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
*value = 0;
for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
en = &nv_allowed_read_registers[i];
- if (reg_offset !=
+ if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
+ reg_offset !=
(adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
continue;
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)
2020-09-25 20:09 ` [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Alex Deucher
@ 2020-09-28 20:52 ` Luben Tuikov
2020-09-29 14:37 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 20:52 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> Van gogh only has one sdma.
>
> v2: use num_instances rather than APU flag
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 2077f897d6eb..8616d397da00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -289,7 +289,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
> *value = 0;
> for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
> en = &nv_allowed_read_registers[i];
> - if (reg_offset !=
> + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> + reg_offset !=
What is the significance here of the number 7?
Ah, notice here "sdma.num_instances" as opposed to "sdma.max_instances",
how it makes sense, right?
Regards,
Luben
> (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> continue;
>
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)
2020-09-28 20:52 ` Luben Tuikov
@ 2020-09-29 14:37 ` Alex Deucher
0 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 14:37 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 4:52 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > Van gogh only has one sdma.
> >
> > v2: use num_instances rather than APU flag
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> > index 2077f897d6eb..8616d397da00 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -289,7 +289,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
> > *value = 0;
> > for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
> > en = &nv_allowed_read_registers[i];
> > - if (reg_offset !=
> > + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> > + reg_offset !=
>
> What is the significance here of the number 7?
>
7th register in the list (SOC15_REG_ENTRY(SDMA1, 0,
mmSDMA1_STATUS_REG) is not present on chips with one SDMA instance.
Alex
> Ah, notice here "sdma.num_instances" as opposed to "sdma.max_instances",
> how it makes sense, right?
>
> Regards,
> Luben
>
> > (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> > continue;
> >
> >
>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 08/45] drm/amdgpu: add van gogh support for ih block
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (5 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
` (36 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds the support for van gogh ih block.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..ce4a974ab777 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -314,6 +314,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (6 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 08/45] drm/amdgpu: add van gogh support for ih block Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-28 20:57 ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type Alex Deucher
` (35 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
The interrupts are not stable while uses guest physical address (GPA)
for interrupt packet write space even on direct loading case.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index ce4a974ab777..b66414998c90 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -661,7 +661,10 @@ static int navi10_ih_sw_init(void *handle)
/* use gpu virtual address for ih ring
* until ih_checken is programmed to allow
* use bus address for ih ring by psp bl */
- use_bus_addr =
+ if (adev->flags & AMD_IS_APU)
+ use_bus_addr = false;
+ else
+ use_bus_addr =
(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
if (r)
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh
2020-09-25 20:09 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
@ 2020-09-28 20:57 ` Luben Tuikov
2020-09-29 15:02 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 20:57 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> The interrupts are not stable while uses guest physical address (GPA)
> for interrupt packet write space even on direct loading case.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index ce4a974ab777..b66414998c90 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -661,7 +661,10 @@ static int navi10_ih_sw_init(void *handle)
> /* use gpu virtual address for ih ring
> * until ih_checken is programmed to allow
> * use bus address for ih ring by psp bl */
> - use_bus_addr =
> + if (adev->flags & AMD_IS_APU)
> + use_bus_addr = false;
> + else
> + use_bus_addr =
> (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
Previously to this patch, as a one-liner, it made sense to use a ternary expression,
but adding the if-conditional, perhaps a more readable way would be:
if (adev->flags & AMD_IS_APU ||
adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
use_bus_addr = false;
else
use_bus_addr = true;
Regards,
Luben
> r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
> if (r)
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh
2020-09-28 20:57 ` Luben Tuikov
@ 2020-09-29 15:02 ` Alex Deucher
0 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 15:02 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 4:57 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > The interrupts are not stable while uses guest physical address (GPA)
> > for interrupt packet write space even on direct loading case.
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > index ce4a974ab777..b66414998c90 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > @@ -661,7 +661,10 @@ static int navi10_ih_sw_init(void *handle)
> > /* use gpu virtual address for ih ring
> > * until ih_checken is programmed to allow
> > * use bus address for ih ring by psp bl */
> > - use_bus_addr =
> > + if (adev->flags & AMD_IS_APU)
> > + use_bus_addr = false;
> > + else
> > + use_bus_addr =
> > (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
>
> Previously to this patch, as a one-liner, it made sense to use a ternary expression,
> but adding the if-conditional, perhaps a more readable way would be:
>
> if (adev->flags & AMD_IS_APU ||
> adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> use_bus_addr = false;
> else
> use_bus_addr = true;
>
Updated. Thanks!
Alex
> Regards,
> Luben
>
> > r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
> > if (r)
> >
>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (7 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header Alex Deucher
` (34 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds van gogh memory type as DDR5.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8d416188ddb3..d98d4e6f311b 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -949,6 +949,7 @@ struct drm_amdgpu_info_firmware {
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9
+#define AMDGPU_VRAM_TYPE_DDR5 10
struct drm_amdgpu_info_device {
/** PCI Device ID */
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (8 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables Alex Deucher
` (33 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add new nemory types in atomfirmware header.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/atomfirmware.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 3e526c394f6c..0799a9ca0440 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1367,6 +1367,11 @@ enum atom_dmi_t17_mem_type_def{
LpDdr2MemType, ///< Assign 28 to LPDDR2
LpDdr3MemType, ///< Assign 29 to LPDDR3
LpDdr4MemType, ///< Assign 30 to LPDDR4
+ GDdr6MemType, ///< Assign 31 to GDDR6
+ HbmMemType, ///< Assign 32 to HBM
+ Hbm2MemType, ///< Assign 33 to HBM2
+ Ddr5MemType, ///< Assign 34 to DDR5
+ LpDdr5MemType, ///< Assign 35 to LPDDR5
};
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (9 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh Alex Deucher
` (32 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Harry Wentland, Roman Li
From: Roman Li <Roman.Li@amd.com>
Required for vangogh.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/atomfirmware.h | 62 +++++++++++++++++++++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 0799a9ca0440..4eb578b1baef 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1304,11 +1304,71 @@ struct atom_integrated_system_info_v1_12
struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
- struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
+ struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
uint32_t reserved[63];
};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+
+struct edp_info_table
+{
+ uint16_t edp_backlight_pwm_hz;
+ uint16_t edp_ss_percentage;
+ uint16_t edp_ss_rate_10hz;
+ uint16_t reserved1;
+ uint32_t reserved2;
+ uint8_t edp_pwr_on_off_delay;
+ uint8_t edp_pwr_on_vary_bl_to_blon;
+ uint8_t edp_pwr_down_bloff_to_vary_bloff;
+ uint8_t edp_panel_bpc;
+ uint8_t edp_bootup_bl_level;
+ uint8_t reserved3[3];
+ uint32_t reserved4[3];
+};
+
+struct atom_integrated_system_info_v2_1
+{
+ struct atom_common_table_header table_header;
+ uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
+ uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
+ uint32_t system_config;
+ uint32_t cpucapinfo;
+ uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
+ uint16_t gpuclk_ss_type;
+ uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
+ uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
+ uint8_t umachannelnumber; // number of memory channels
+ uint8_t htc_hyst_limit;
+ uint8_t htc_tmp_limit;
+ uint8_t reserved1;
+ uint8_t reserved2;
+ struct edp_info_table edp1_info;
+ struct edp_info_table edp2_info;
+ uint32_t reserved3[8];
+ struct atom_external_display_connection_info extdispconninfo;
+ struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
+ uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
+ struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
+ struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
+ struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
+ struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
+ struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
+ uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
+ struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
+ struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
+ struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
+ struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
+ uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
+ uint32_t reserved7[32];
+
+};
+#endif
+
// system_config
enum atom_system_vbiosmisc_def{
INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (10 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3) Alex Deucher
` (31 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to get the correct vram type from atombios for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 17c010d0431f..e0e3a7e4774f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -149,6 +149,10 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
case LpDdr4MemType:
vram_type = AMDGPU_VRAM_TYPE_DDR4;
break;
+ case Ddr5MemType:
+ case LpDdr5MemType:
+ vram_type = AMDGPU_VRAM_TYPE_DDR5;
+ break;
default:
vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 92fbbfb16cff..2ce79bccfc30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1063,6 +1063,7 @@ static const char *amdgpu_vram_names[] = {
"DDR3",
"DDR4",
"GDDR6",
+ "DDR5"
};
/**
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (11 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 15/45] drm/amdgpu: set fw load type for van gogh Alex Deucher
` (30 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add gfx memory controller support for van gogh.
v2: don't use dynamic invalidate eng allocation for van gogh.
v3: squash in other fixes
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 33 ++++++++++++++++++++------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 31359e519d69..fa0a0c8a6b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -677,7 +677,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
u64 base = 0;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
base = gfxhub_v2_1_get_fb_location(adev);
else
base = gfxhub_v2_0_get_fb_location(adev);
@@ -690,7 +691,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
/* base offset of vram pages */
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
else
adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
@@ -726,6 +728,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+#ifdef CONFIG_X86_64
+ if (adev->flags & AMD_IS_APU) {
+ adev->gmc.aper_base = gfxhub_v2_1_get_mc_fb_offset(adev);
+ adev->gmc.aper_size = adev->gmc.real_vram_size;
+ }
+#endif
+
/* In case the PCI BAR is larger than the actual amount of vram */
adev->gmc.visible_vram_size = adev->gmc.aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
@@ -739,6 +748,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@@ -778,7 +788,8 @@ static int gmc_v10_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
gfxhub_v2_1_init(adev);
else
gfxhub_v2_0_init(adev);
@@ -787,7 +798,10 @@ static int gmc_v10_0_sw_init(void *handle)
spin_lock_init(&adev->gmc.invalidate_lock);
- if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+ if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
+ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
+ adev->gmc.vram_width = 64;
+ } else if (amdgpu_emu_mode == 1) {
adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
} else {
@@ -805,6 +819,7 @@ static int gmc_v10_0_sw_init(void *handle)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
@@ -918,6 +933,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
break;
default:
break;
@@ -945,7 +961,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
return r;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
r = gfxhub_v2_1_gart_enable(adev);
else
r = gfxhub_v2_0_gart_enable(adev);
@@ -970,7 +987,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
false : true;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
gfxhub_v2_1_set_fault_enable_default(adev, value);
else
gfxhub_v2_0_set_fault_enable_default(adev, value);
@@ -1015,7 +1033,8 @@ static int gmc_v10_0_hw_init(void *handle)
static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
gfxhub_v2_1_gart_disable(adev);
else
gfxhub_v2_0_gart_disable(adev);
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 15/45] drm/amdgpu: set fw load type for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (12 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3) Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2) Alex Deucher
` (29 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch sets fw load type as direct for van gogh for the moment.
Will switch to psp when psp is ready.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 55fe19a2f332..3f791ca73ff7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -395,6 +395,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
+ case CHIP_VANGOGH:
+ return AMDGPU_FW_LOAD_DIRECT;
default:
DRM_ERROR("Unknown firmware load type\n");
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (13 preceding siblings ...)
2020-09-25 20:09 ` [PATCH 15/45] drm/amdgpu: set fw load type for van gogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-28 20:18 ` [PATCH] drm/amdgpu: fix perms of gfx_v10_0.c Luben Tuikov
2020-09-25 20:10 ` [PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3) Alex Deucher
` (28 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add van gogh checks to gfx10 code.
v2: squash in fixes
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 +++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
old mode 100644
new mode 100755
index 17fb2efdadd3..19ab5783214c
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -152,6 +152,13 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_10_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3554,6 +3561,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.cp_fw_write_wait = true;
break;
default:
@@ -3652,6 +3660,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
@@ -4186,6 +4197,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4309,6 +4321,7 @@ static int gfx_v10_0_sw_init(void *handle)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -4564,7 +4577,8 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
return 0;
/* init num_sc */
@@ -5801,6 +5815,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5934,6 +5949,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
break;
default:
@@ -5944,6 +5960,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
(CP_MEC_CNTL__MEC_ME1_HALT_MASK |
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6038,6 +6055,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6758,6 +6776,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
return false;
}
break;
+ case CHIP_VANGOGH:
+ return true;
default:
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
@@ -6785,6 +6805,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7079,6 +7100,7 @@ static int gfx_v10_0_soft_reset(void *handle)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
GRBM_SOFT_RESET,
@@ -7178,6 +7200,7 @@ static int gfx_v10_0_early_init(void *handle)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
break;
default:
@@ -7231,6 +7254,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
/* wait for RLC_SAFE_MODE */
@@ -7263,6 +7287,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
break;
default:
@@ -7574,6 +7599,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
gfx_v10_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
@@ -8676,6 +8702,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
break;
case CHIP_NAVI12:
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (14 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH Alex Deucher
` (27 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add gfx golden settings for vangogh post si.
v2: squash in updates
v3: fix SPI register offset
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 36 +++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 19ab5783214c..6999228cd6c0 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -99,6 +99,9 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
+#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
+#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
+
#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
#define mmCP_HYP_PFP_UCODE_DATA 0x5815
@@ -3170,6 +3173,33 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
};
+static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
+{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
+};
+
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3377,7 +3407,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_3_2,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
break;
-
+ case CHIP_VANGOGH:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_10_3_vangogh,
+ (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
+ break;
default:
break;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (15 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 19/45] drm/amdgpu: add sdma support for van gogh Alex Deucher
` (26 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6999228cd6c0..83183541865f 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -99,8 +99,22 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
-#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
-#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
+#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
+#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
+#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
+#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
+#define mmVGT_TF_RING_SIZE_Vangogh 0x224e
+#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
+#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
+#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
+#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
+#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
+#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_Vangogh 0x2440
+#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 19/45] drm/amdgpu: add sdma support for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (16 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 20/45] drm/amdgpu: set ip blocks " Alex Deucher
` (25 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds the sdma v5.2 support for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 9f3952723c63..100d0a921ede 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -47,6 +47,8 @@
MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
+
#define SDMA1_REG_OFFSET 0x600
#define SDMA3_REG_OFFSET 0x400
#define SDMA0_HYP_DEC_REG_START 0x5880
@@ -87,6 +89,7 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
break;
default:
break;
@@ -160,6 +163,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
@@ -1171,6 +1177,9 @@ static int sdma_v5_2_early_init(void *handle)
case CHIP_NAVY_FLOUNDER:
adev->sdma.num_instances = 2;
break;
+ case CHIP_VANGOGH:
+ adev->sdma.num_instances = 1;
+ break;
default:
break;
}
@@ -1567,6 +1576,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v5_2_update_medium_grain_light_sleep(adev,
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 20/45] drm/amdgpu: set ip blocks for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (17 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 19/45] drm/amdgpu: add sdma support for van gogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 21/45] drm/amdkfd: add Van Gogh KFD support Alex Deucher
` (24 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Enable ip blocks for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 8616d397da00..df94f72e017a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -604,6 +604,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
break;
+ case CHIP_VANGOGH:
+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ break;
default:
return -EINVAL;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 21/45] drm/amdkfd: add Van Gogh KFD support
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (18 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 20/45] drm/amdgpu: set ip blocks " Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4) Alex Deucher
` (23 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Yong Zhao, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add GFX10 based APU Van Gogh KFD support. We will treat Van
Gogh as "dgpu" (bypass IOMMU v2).
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +++++
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 +++++++++++++++++++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
6 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index d2981524dba0..0eeda7904c14 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -141,6 +141,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
#define renoir_cache_info carrizo_cache_info
/* TODO - check & update Navi10 cache details */
#define navi10_cache_info carrizo_cache_info
+#define vangogh_cache_info carrizo_cache_info
static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
struct crat_subtype_computeunit *cu)
@@ -683,6 +684,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
break;
+ case CHIP_VANGOGH:
+ pcache_info = vangogh_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 903170e59342..81751da79feb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -76,6 +76,7 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
[CHIP_NAVI14] = &gfx_v10_kfd2kgd,
[CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
[CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
+ [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
};
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -498,6 +499,24 @@ static const struct kfd_device_info navy_flounder_device_info = {
.num_sdma_queues_per_engine = 8,
};
+static const struct kfd_device_info vangogh_device_info = {
+ .asic_family = CHIP_VANGOGH,
+ .asic_name = "vangogh",
+ .max_pasid_bits = 16,
+ .max_no_of_hqd = 24,
+ .doorbell_size = 8,
+ .ih_ring_entry_size = 8 * sizeof(uint32_t),
+ .event_interrupt_class = &event_interrupt_class_v9,
+ .num_of_watch_points = 4,
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .needs_iommu_device = false,
+ .supports_cwsr = true,
+ .needs_pci_atomics = false,
+ .num_sdma_engines = 1,
+ .num_xgmi_sdma_engines = 0,
+ .num_sdma_queues_per_engine = 2,
+};
+
/* For each entry, [0] is regular and [1] is virtualisation device. */
static const struct kfd_device_info *kfd_supported_devices[][2] = {
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -522,6 +541,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
[CHIP_NAVI14] = {&navi14_device_info, NULL},
[CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
[CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
+ [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
};
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 62504d5fa42b..7971bbe696d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1925,6 +1925,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
device_queue_manager_init_v10_navi10(&dqm->asic_ops);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 3c22909470f2..379457d1b250 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -417,6 +417,7 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
kfd_init_apertures_v9(pdd, id);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 47ee40fbbd86..9beb2eabd56e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -247,6 +247,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
pm->pmf = &kfd_v9_pm_funcs;
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 2b31c3066aaa..da6b493c520f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1375,6 +1375,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (19 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 21/45] drm/amdkfd: add Van Gogh KFD support Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh Alex Deucher
` (22 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
There are too many register offset mismatch between mmhub v2.0 and v2.3.
E.X:
mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3)
mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3)
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32: 0x072b(v2.0) 0x0940(v2.3)
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32: 0x072c(v2.0) 0x0941(v2.3)
mmMMVM_INVALIDATE_ENG0_REQ: 0x06e3(v2.0) 0x0a01(v2.3)
mmMMVM_INVALIDATE_ENG0_ACK: 0x06f5(v2.0) 0x0a02(v2.3)
mmMMVM_CONTEXT0_CNTL: 0x06c0(v2.0) 0x0740(v2.3)
mmMMVM_L2_PROTECTION_FAULT_STATUS: 0x068c(v2.0) 0x070c(v2.3)
mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3)
mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3)
mmDAGB0_CNTL_MISC2: 0x0071(v2.0) 0x0096(v2.3)
...
Continuing using the same file mmhub v2.0 is not good choice, it will
introduce a lot of checking with ASIC types. And also easy to introduce the
issues that offset not align, this kind of issues are really hard to find. Van
Gogh's mmhub vm invalidation is actually caused by the offset mismatch as well.
So it would like to create a new file rather than stick to re-use orignal mmhub
v2.0 here.
v2: add missed translate_further programming.
v3: sync with latest code
v4: add missing callbacks
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 552 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h | 28 ++
4 files changed, 590 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7866e4666a43..7c7e34824c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -81,7 +81,7 @@ amdgpu-y += \
gmc_v7_0.o \
gmc_v8_0.o \
gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
- gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o
+ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o
# add UMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index fa0a0c8a6b11..df14880cf97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -46,6 +46,7 @@
#include "gfxhub_v2_0.h"
#include "gfxhub_v2_1.h"
#include "mmhub_v2_0.h"
+#include "mmhub_v2_3.h"
#include "athub_v2_0.h"
#include "athub_v2_1.h"
@@ -631,7 +632,14 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
{
- adev->mmhub.funcs = &mmhub_v2_0_funcs;
+ switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ adev->mmhub.funcs = &mmhub_v2_3_funcs;
+ break;
+ default:
+ adev->mmhub.funcs = &mmhub_v2_0_funcs;
+ break;
+ }
}
static int gmc_v10_0_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
new file mode 100644
index 000000000000..b39dc2023b5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "mmhub_v2_3.h"
+
+#include "mmhub/mmhub_2_3_0_offset.h"
+#include "mmhub/mmhub_2_3_0_sh_mask.h"
+#include "mmhub/mmhub_2_3_0_default.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vmid*/
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
+static void
+mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ dev_err(adev->dev,
+ "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ status);
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, CID));
+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+ dev_err(adev->dev, "\t RW: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, RW));
+}
+
+static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
+ uint32_t vmid,
+ uint64_t page_table_base)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
+
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
+}
+
+static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+ mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base);
+
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ (u32)(adev->gmc.gart_start >> 12));
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ (u32)(adev->gmc.gart_start >> 44));
+
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ (u32)(adev->gmc.gart_end >> 12));
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ (u32)(adev->gmc.gart_end >> 44));
+}
+
+static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
+{
+ uint64_t value;
+ uint32_t tmp;
+
+ /* Disable AGP. */
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
+
+ /* Program the system aperture low logical page number. */
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ adev->gmc.vram_start >> 18);
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ adev->gmc.vram_end >> 18);
+
+ /* Set default page address. */
+ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+ adev->vm_manager.vram_base_offset;
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+ (u32)(value >> 12));
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+ (u32)(value >> 44));
+
+ /* Program "protection fault". */
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+ (u32)(adev->dummy_page_addr >> 12));
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+ (u32)((u64)adev->dummy_page_addr >> 44));
+
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
+ ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
+}
+
+static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ /* Setup TLB control */
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
+
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+ ENABLE_ADVANCED_DRIVER_MODEL, 1);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+ SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+ MTYPE, MTYPE_UC); /* UC, uncached */
+
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
+}
+
+static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ /* Setup L2 cache */
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
+ ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
+ /* XXX for emulation, Refer to closed source code.*/
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+ 0);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
+
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
+
+ tmp = mmMMVM_L2_CNTL3_DEFAULT;
+ if (adev->gmc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
+
+ tmp = mmMMVM_L2_CNTL4_DEFAULT;
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
+
+ tmp = mmMMVM_L2_CNTL5_DEFAULT;
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
+ WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+}
+
+static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
+ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+}
+
+static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(MMHUB, 0,
+ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+ 0xFFFFFFFF);
+ WREG32_SOC15(MMHUB, 0,
+ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+ 0x0000000F);
+
+ WREG32_SOC15(MMHUB, 0,
+ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
+ WREG32_SOC15(MMHUB, 0,
+ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
+
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
+ 0);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
+ 0);
+}
+
+static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+ int i;
+ uint32_t tmp;
+
+ for (i = 0; i <= 14; i++) {
+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+ adev->vm_manager.num_level);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+ 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ PAGE_TABLE_BLOCK_SIZE,
+ adev->vm_manager.block_size - 9);
+ /* Send no-retry XNACK on fault to suppress VM fault storm. */
+ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+ !amdgpu_noretry);
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
+ i * hub->ctx_distance, tmp);
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+ i * hub->ctx_addr_distance, 0);
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+ i * hub->ctx_addr_distance, 0);
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+ i * hub->ctx_addr_distance,
+ lower_32_bits(adev->vm_manager.max_pfn - 1));
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+ i * hub->ctx_addr_distance,
+ upper_32_bits(adev->vm_manager.max_pfn - 1));
+ }
+}
+
+static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+ unsigned i;
+
+ for (i = 0; i < 18; ++i) {
+ WREG32_SOC15_OFFSET(MMHUB, 0,
+ mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+ i * hub->eng_addr_distance, 0xffffffff);
+ WREG32_SOC15_OFFSET(MMHUB, 0,
+ mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+ i * hub->eng_addr_distance, 0x1f);
+ }
+}
+
+static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
+{
+ if (amdgpu_sriov_vf(adev)) {
+ /*
+ * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+ * VF copy registers so vbios post doesn't program them, for
+ * SRIOV driver need to program them
+ */
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
+ adev->gmc.vram_start >> 24);
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
+ adev->gmc.vram_end >> 24);
+ }
+
+ /* GART Enable. */
+ mmhub_v2_3_init_gart_aperture_regs(adev);
+ mmhub_v2_3_init_system_aperture_regs(adev);
+ mmhub_v2_3_init_tlb_regs(adev);
+ mmhub_v2_3_init_cache_regs(adev);
+
+ mmhub_v2_3_enable_system_domain(adev);
+ mmhub_v2_3_disable_identity_aperture(adev);
+ mmhub_v2_3_setup_vmid_config(adev);
+ mmhub_v2_3_program_invalidation(adev);
+
+ return 0;
+}
+
+static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+ u32 tmp;
+ u32 i;
+
+ /* Disable all tables */
+ for (i = 0; i < 16; i++)
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
+ i * hub->ctx_distance, 0);
+
+ /* Setup TLB control */
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+ ENABLE_ADVANCED_DRIVER_MODEL, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
+
+ /* Setup L2 cache */
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
+}
+
+/**
+ * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
+ bool value)
+{
+ u32 tmp;
+ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
+ value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ if (!value) {
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_NO_RETRY_FAULT, 1);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_RETRY_FAULT, 1);
+ }
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v2_3_get_invalidate_req,
+};
+
+static void mmhub_v2_3_init(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+ hub->ctx0_ptb_addr_lo32 =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
+ hub->vm_inv_eng0_sem =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmMMVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
+ hub->vm_context0_cntl =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+ hub->vm_l2_pro_fault_status =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
+ hub->vm_l2_pro_fault_cntl =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
+
+ hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
+ hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
+ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+ hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
+ mmMMVM_INVALIDATE_ENG0_REQ;
+ hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
+ mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+ hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs;
+}
+
+static void
+mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data, def1, data1;
+
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+ data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
+
+ data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+
+ } else {
+ data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
+
+ data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+ }
+
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+ if (def1 != data1)
+ WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
+}
+
+static void
+mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+ data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+ else
+ data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+}
+
+static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state)
+{
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ mmhub_v2_3_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ mmhub_v2_3_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+
+ return 0;
+}
+
+static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+ int data, data1;
+
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+ data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+
+ /* AMD_CG_SUPPORT_MC_MGCG */
+ if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
+ !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+ *flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+ /* AMD_CG_SUPPORT_MC_LS */
+ if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_LS;
+}
+
+const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = {
+ .ras_late_init = amdgpu_mmhub_ras_late_init,
+ .init = mmhub_v2_3_init,
+ .gart_enable = mmhub_v2_3_gart_enable,
+ .set_fault_enable_default = mmhub_v2_3_set_fault_enable_default,
+ .gart_disable = mmhub_v2_3_gart_disable,
+ .set_clockgating = mmhub_v2_3_set_clockgating,
+ .get_clockgating = mmhub_v2_3_get_clockgating,
+ .setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
new file mode 100644
index 000000000000..2926d21dea8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __MMHUB_V2_3_H__
+#define __MMHUB_V2_3_H__
+
+extern const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs;
+
+#endif
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (20 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv Alex Deucher
` (21 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Thong Thai
From: Thong Thai <thong.thai@amd.com>
Same as other VCN 3.0 asics.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 ++++++++
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 495c3d7bb2b2..81102598cde7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -44,6 +44,7 @@
#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
#define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
#define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
+#define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
@@ -55,6 +56,7 @@ MODULE_FIRMWARE(FIRMWARE_NAVI14);
MODULE_FIRMWARE(FIRMWARE_NAVI12);
MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
+MODULE_FIRMWARE(FIRMWARE_VANGOGH);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -123,6 +125,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
+ case CHIP_VANGOGH:
+ fw_name = FIRMWARE_VANGOGH;
+ if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+ adev->vcn.indirect_sram = true;
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index df94f72e017a..2711c5661a97 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -612,6 +612,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
default:
return -EINVAL;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (21 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2) Alex Deucher
` (20 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add pcie port indirect read/write callback for nv
series. They will be used for new asic.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nv.c | 32 ++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index edaac242ff85..483834a62436 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -53,6 +53,8 @@ struct amdgpu_nbio_funcs {
u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
u32 (*get_rev_id)(struct amdgpu_device *adev);
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2711c5661a97..5b3b70a64a79 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -118,6 +118,21 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
return r;
}
+static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
+{
+ unsigned long flags, address, data;
+ u32 r;
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ r = RREG32(data);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ return r;
+}
+
static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
{
unsigned long flags, address, data;
@@ -140,6 +155,21 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
}
+static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+ unsigned long flags, address, data;
+
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ WREG32(data, v);
+ (void)RREG32(data);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
{
unsigned long flags, address, data;
@@ -746,6 +776,8 @@ static int nv_common_early_init(void *handle)
adev->pcie_wreg = &nv_pcie_wreg;
adev->pcie_rreg64 = &nv_pcie_rreg64;
adev->pcie_wreg64 = &nv_pcie_wreg64;
+ adev->pciep_rreg = &nv_pcie_port_rreg;
+ adev->pciep_wreg = &nv_pcie_port_wreg;
/* TODO: will add them during VCN v2 implementation */
adev->uvd_ctx_rreg = NULL;
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (22 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks " Alex Deucher
` (19 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio
v2.3 for navi series, so add new nbio v7.2 block.
v2: squash in fix for sdma and vcn instances
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 341 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h | 32 +++
drivers/gpu/drm/amd/amdgpu/nv.c | 10 +-
4 files changed, 383 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7c7e34824c51..60cff3b08eb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
+ nbio_v7_2.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
new file mode 100644
index 000000000000..aa36022670f9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "nbio_v7_2.h"
+
+#include "nbio/nbio_7_2_0_offset.h"
+#include "nbio/nbio_7_2_0_sh_mask.h"
+#include <uapi/linux/kfd_ioctl.h>
+
+static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
+static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
+{
+ u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+
+ tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+ tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+ return tmp;
+}
+
+static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+ if (enable)
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+ BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+ BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+ else
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+}
+
+static void nbio_v7_2_hdp_flush(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring)
+{
+ if (!ring || !ring->funcs->emit_wreg)
+ WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ else
+ amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+}
+
+static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
+{
+ return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
+}
+
+static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index,
+ int doorbell_size)
+{
+ u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
+ u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_SDMA0_DOORBELL_RANGE,
+ OFFSET, doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_SDMA0_DOORBELL_RANGE,
+ SIZE, doorbell_size);
+ } else {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_SDMA0_DOORBELL_RANGE,
+ SIZE, 0);
+ }
+
+ WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
+static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
+ int doorbell_index, int instance)
+{
+ u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
+ u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
+ doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
+ } else {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
+ }
+
+ WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
+static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+ u32 reg;
+
+ reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
+ reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
+ BIF_DOORBELL_APER_EN, enable ? 1 : 0);
+
+ WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
+}
+
+static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+ u32 tmp = 0;
+
+ if (enable) {
+ tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_EN, 1) |
+ REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+ REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+ WREG32_SOC15(NBIO, 0,
+ regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+ lower_32_bits(adev->doorbell.base));
+ WREG32_SOC15(NBIO, 0,
+ regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+ upper_32_bits(adev->doorbell.base));
+ }
+
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ tmp);
+}
+
+
+static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index)
+{
+ u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
+
+ if (use_doorbell) {
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
+ doorbell_index);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
+ 2);
+ } else {
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
+ 0);
+ }
+
+ WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
+ ih_doorbell_range);
+}
+
+static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
+{
+ u32 interrupt_cntl;
+
+ /* setup interrupt control */
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
+ adev->dummy_page_addr >> 8);
+
+ interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
+ /*
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+ */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+ IH_DUMMY_RD_OVERRIDE, 0);
+
+ /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+ IH_REQ_NONSNOOP_EN, 0);
+
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
+}
+
+static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
+ data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
+ CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
+ } else {
+ data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
+ CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
+ CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
+ }
+
+ if (def != data)
+ WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
+}
+
+static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+ data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+ PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+ } else {
+ data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+ PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+ }
+
+ if (def != data)
+ WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
+}
+
+static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
+ u32 *flags)
+{
+ int data;
+
+ /* AMD_CG_SUPPORT_BIF_MGCG */
+ data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
+ if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_MGCG;
+
+ /* AMD_CG_SUPPORT_BIF_LS */
+ data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+ if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_LS;
+}
+
+static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
+}
+
+static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
+}
+
+static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
+}
+
+static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
+}
+
+static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
+}
+
+static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
+}
+
+const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
+ .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+ .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
+ .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
+ .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
+ .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
+ .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
+ .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
+ .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
+ .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+ .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
+};
+
+static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
+ data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+ data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+ if (def != data)
+ WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
+ data);
+}
+
+const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
+ .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
+ .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
+ .get_rev_id = nbio_v7_2_get_rev_id,
+ .mc_access_enable = nbio_v7_2_mc_access_enable,
+ .hdp_flush = nbio_v7_2_hdp_flush,
+ .get_memsize = nbio_v7_2_get_memsize,
+ .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
+ .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
+ .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
+ .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
+ .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
+ .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
+ .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
+ .get_clockgating_state = nbio_v7_2_get_clockgating_state,
+ .ih_control = nbio_v7_2_ih_control,
+ .init_registers = nbio_v7_2_init_registers,
+ .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
new file mode 100644
index 000000000000..a8e8e65648a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __NBIO_V7_2_H__
+#define __NBIO_V7_2_H__
+
+#include "soc15_common.h"
+
+extern const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg;
+extern const struct amdgpu_nbio_funcs nbio_v7_2_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5b3b70a64a79..3ac89109ea3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -49,6 +49,7 @@
#include "gfxhub_v2_0.h"
#include "mmhub_v2_0.h"
#include "nbio_v2_3.h"
+#include "nbio_v7_2.h"
#include "nv.h"
#include "navi10_ih.h"
#include "gfx_v10_0.h"
@@ -528,8 +529,13 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
- adev->nbio.funcs = &nbio_v2_3_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ if (adev->flags & AMD_IS_APU) {
+ adev->nbio.funcs = &nbio_v7_2_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+ } else {
+ adev->nbio.funcs = &nbio_v2_3_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ }
if (adev->asic_type == CHIP_SIENNA_CICHLID)
adev->gmc.xgmi.supported = true;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (23 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh Alex Deucher
` (18 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add new smu messages and feature masks for vangogh.
v2: squash in updates and typo fixes
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 53 +++++++++++++++++++++++---
1 file changed, 47 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 35fc46d3c9c0..b1a18fbb7682 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -35,6 +35,7 @@
__SMU_DUMMY_MAP(EnableSmuFeaturesHigh), \
__SMU_DUMMY_MAP(DisableSmuFeaturesLow), \
__SMU_DUMMY_MAP(DisableSmuFeaturesHigh), \
+ __SMU_DUMMY_MAP(GetEnabledSmuFeatures), \
__SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow), \
__SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh), \
__SMU_DUMMY_MAP(SetWorkloadMask), \
@@ -122,7 +123,7 @@
__SMU_DUMMY_MAP(GetVoltageByDpm), \
__SMU_DUMMY_MAP(GetVoltageByDpmOverdrive), \
__SMU_DUMMY_MAP(PowerUpVcn0), \
- __SMU_DUMMY_MAP(PowerDownVcn0), \
+ __SMU_DUMMY_MAP(PowerDownVcn0), \
__SMU_DUMMY_MAP(PowerUpVcn1), \
__SMU_DUMMY_MAP(PowerDownVcn1), \
__SMU_DUMMY_MAP(PowerUpGfx), \
@@ -165,18 +166,24 @@
__SMU_DUMMY_MAP(GpuChangeState), \
__SMU_DUMMY_MAP(SetPowerLimitPercentage), \
__SMU_DUMMY_MAP(ForceGfxContentSave), \
- __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
+ __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown),\
__SMU_DUMMY_MAP(PowerGateAtHub), \
__SMU_DUMMY_MAP(SetSoftMinJpeg), \
__SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
- __SMU_DUMMY_MAP(DFCstateControl), \
- __SMU_DUMMY_MAP(GmiPwrDnControl), \
- __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
+ __SMU_DUMMY_MAP(DFCstateControl), \
+ __SMU_DUMMY_MAP(GmiPwrDnControl), \
+ __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\
__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
__SMU_DUMMY_MAP(GET_UMC_FW_WA), \
__SMU_DUMMY_MAP(Mode1Reset), \
+ __SMU_DUMMY_MAP(Spare), \
+ __SMU_DUMMY_MAP(SetHardMinIspiclkByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinIspxclkByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
+ __SMU_DUMMY_MAP(PowerUpCvip), \
+ __SMU_DUMMY_MAP(PowerDownCvip), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
@@ -265,7 +272,41 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(ATHUB_PG), \
__SMU_DUMMY_MAP(APCC_DFLL), \
__SMU_DUMMY_MAP(DPM_GFX_GPO), \
- __SMU_DUMMY_MAP(WAFL_CG),
+ __SMU_DUMMY_MAP(WAFL_CG), \
+ __SMU_DUMMY_MAP(CCLK_DPM), \
+ __SMU_DUMMY_MAP(FAN_CONTROLLER), \
+ __SMU_DUMMY_MAP(VCN_DPM), \
+ __SMU_DUMMY_MAP(FCLK_DPM), \
+ __SMU_DUMMY_MAP(SOCCLK_DPM), \
+ __SMU_DUMMY_MAP(MP0CLK_DPM), \
+ __SMU_DUMMY_MAP(LCLK_DPM), \
+ __SMU_DUMMY_MAP(SHUBCLK_DPM), \
+ __SMU_DUMMY_MAP(DCFCLK_DPM), \
+ __SMU_DUMMY_MAP(GFX_DPM), \
+ __SMU_DUMMY_MAP(DS_DCFCLK), \
+ __SMU_DUMMY_MAP(S0I2), \
+ __SMU_DUMMY_MAP(SMU_LOW_POWER), \
+ __SMU_DUMMY_MAP(GFX_DEM), \
+ __SMU_DUMMY_MAP(PSI), \
+ __SMU_DUMMY_MAP(PROCHOT), \
+ __SMU_DUMMY_MAP(CPUOFF), \
+ __SMU_DUMMY_MAP(STAPM), \
+ __SMU_DUMMY_MAP(S0I3), \
+ __SMU_DUMMY_MAP(DF_CSTATES), \
+ __SMU_DUMMY_MAP(PERF_LIMIT), \
+ __SMU_DUMMY_MAP(CORE_DLDO), \
+ __SMU_DUMMY_MAP(RSMU_LOW_POWER), \
+ __SMU_DUMMY_MAP(SMN_LOW_POWER), \
+ __SMU_DUMMY_MAP(THM_LOW_POWER), \
+ __SMU_DUMMY_MAP(SMUIO_LOW_POWER), \
+ __SMU_DUMMY_MAP(MP1_LOW_POWER), \
+ __SMU_DUMMY_MAP(DS_VCN), \
+ __SMU_DUMMY_MAP(CPPC), \
+ __SMU_DUMMY_MAP(OS_CSTATES), \
+ __SMU_DUMMY_MAP(ISP_DPM), \
+ __SMU_DUMMY_MAP(A55_DPM), \
+ __SMU_DUMMY_MAP(CVIP_DSP_DPM), \
+ __SMU_DUMMY_MAP(MSMU_LOW_POWER),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (24 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks " Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-28 21:41 ` Luben Tuikov
2020-09-25 20:10 ` [PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) Alex Deucher
` (17 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 239 ++++++++++++++++++
1 file changed, 239 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
new file mode 100644
index 000000000000..20f8c6f460b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
+#define __SMU11_DRIVER_IF_VANGOGH_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU13_DRIVER_IF_VERSION 2
+
+typedef struct {
+ int32_t value;
+ uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+ DSPCLK_DCFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq; // in MHz
+ uint16_t Vid; // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t WmType; // Used for normal pstate change or memory retraining
+ uint8_t Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+ CUSTOM_DPM_SETTING_GFXCLK,
+ CUSTOM_DPM_SETTING_CCLK,
+ CUSTOM_DPM_SETTING_FCLK_CCX,
+ CUSTOM_DPM_SETTING_FCLK_GFX,
+ CUSTOM_DPM_SETTING_FCLK_STALLS,
+ CUSTOM_DPM_SETTING_LCLK,
+ CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+ uint8_t ActiveHystLimit;
+ uint8_t IdleHystLimit;
+ uint8_t FPS;
+ uint8_t MinActiveFreqType;
+ FloatInIntFormat_t MinActiveFreq;
+ FloatInIntFormat_t PD_Data_limit;
+ FloatInIntFormat_t PD_Data_time_constant;
+ FloatInIntFormat_t PD_Data_error_coeff;
+ FloatInIntFormat_t PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+ DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS 6
+#define NUM_DISPCLK_DPM_LEVELS 6
+#define NUM_DPPCLK_DPM_LEVELS 6
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_ISPICLK_DPM_LEVELS 6
+#define NUM_ISPXCLK_DPM_LEVELS 6
+#define NUM_VCN_DPM_LEVELS 8
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_SOC_VOLTAGE_LEVELS 8
+
+typedef struct {
+ uint32_t fclk;
+ uint32_t memclk;
+ uint32_t voltage;
+} df_pstate_t;
+
+typedef struct {
+ uint32_t vclk;
+ uint32_t dclk;
+} vcn_clk_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+
+typedef struct {
+ uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+ uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+ uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+ uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+ uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
+ uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
+ vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
+
+ uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+
+ df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
+
+ uint32_t MinGfxClk;
+ uint32_t MaxGfxClk;
+
+ uint8_t NumDfPstatesEnabled;
+ uint8_t NumDpmLevelsEnabled;
+ uint8_t spare[2];
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL 0
+#define THROTTLER_STATUS_BIT_FPPT 1
+#define THROTTLER_STATUS_BIT_SPPT 2
+#define THROTTLER_STATUS_BIT_SPPT_APU 3
+#define THROTTLER_STATUS_BIT_THM_CORE 4
+#define THROTTLER_STATUS_BIT_THM_GFX 5
+#define THROTTLER_STATUS_BIT_THM_SOC 6
+#define THROTTLER_STATUS_BIT_TDC_VDD 7
+#define THROTTLER_STATUS_BIT_TDC_SOC 8
+#define THROTTLER_STATUS_BIT_TDC_GFX 9
+#define THROTTLER_STATUS_BIT_TDC_CVIP 10
+
+typedef struct {
+ uint16_t AverageGfxclkFrequency; //[MHz]
+ uint16_t AverageSocclkFrequency; //[MHz]
+ uint16_t AverageVclkFrequency; //[MHz]
+ uint16_t AverageDclkFrequency; //[MHz]
+ uint16_t AverageMemclkFrequency; //[MHz]
+ uint16_t spare;
+
+ uint16_t AverageGfxActivity; //[centi]
+ uint16_t AverageUvdActivity; //[centi]
+
+ uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t CurrentSocketPower; //[mW]
+
+ //3rd party tools in Windows need this info in the case of APUs
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
+
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t EdgeTemperature;
+ uint16_t ThrottlerStatus;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_VR_BIT 3
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5
+#define WORKLOAD_PPLIB_COUNT 6
+
+#define TABLE_BIOS_IF 0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_MOMENTARY_PM 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS 7 // Called by Driver
+#define TABLE_COUNT 8
+
+//ISP tile definitions
+typedef enum {
+ TILE_ISPX = 0, // ISPX
+ TILE_ISPM, // ISPM
+ TILE_ISPC, // ISPCORE
+ TILE_ISPPRE, // ISPPRE
+ TILE_ISPPOST, // ISPPOST
+ TILE_MAX
+} TILE_NUM_e;
+
+// Tile Selection (Based on arguments)
+#define TILE_SEL_ISPX (1<<(TILE_ISPX))
+#define TILE_SEL_ISPM (1<<(TILE_ISPM))
+#define TILE_SEL_ISPC (1<<(TILE_ISPC))
+#define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE))
+#define TILE_SEL_ISPPOST (1<<(TILE_ISPPOST))
+
+// Mask for ISP tiles in PGFSM PWR Status Registers
+//Bit[1:0] maps to ISPX, (ISPX)
+//Bit[3:2] maps to ISPM, (ISPM)
+//Bit[5:4] maps to ISPCORE, (ISPCORE)
+//Bit[7:6] maps to ISPPRE, (ISPPRE)
+//Bit[9:8] maps to POST, (ISPPOST
+#define TILE_ISPX_MASK ((1<<0) | (1<<1))
+#define TILE_ISPM_MASK ((1<<2) | (1<<3))
+#define TILE_ISPC_MASK ((1<<4) | (1<<5))
+#define TILE_ISPPRE_MASK ((1<<6) | (1<<7))
+#define TILE_ISPPOST_MASK ((1<<8) | (1<<9))
+
+#endif
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh
2020-09-25 20:10 ` [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh Alex Deucher
@ 2020-09-28 21:41 ` Luben Tuikov
2020-09-29 14:39 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 21:41 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> From: Xiaojian Du <xiaojian.du@amd.com>
>
> This patch is to add smu v11.5 driver interface header for vangogh.
>
> Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 239 ++++++++++++++++++
> 1 file changed, 239 insertions(+)
> create mode 100644 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
> new file mode 100644
> index 000000000000..20f8c6f460b8
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
> @@ -0,0 +1,239 @@
> +/*
> + * Copyright 2020 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
> +#define __SMU11_DRIVER_IF_VANGOGH_H__
> +
> +// *** IMPORTANT ***
> +// SMU TEAM: Always increment the interface version if
> +// any structure is changed in this file
> +#define SMU13_DRIVER_IF_VERSION 2
> +
> +typedef struct {
> + int32_t value;
> + uint32_t numFractionalBits;
> +} FloatInIntFormat_t;
GNU-style indentation as opposed to Linux-style
throughout this file.
Regards,
Luben
> +
> +typedef enum {
> + DSPCLK_DCFCLK = 0,
> + DSPCLK_DISPCLK,
> + DSPCLK_PIXCLK,
> + DSPCLK_PHYCLK,
> + DSPCLK_COUNT,
> +} DSPCLK_e;
> +
> +typedef struct {
> + uint16_t Freq; // in MHz
> + uint16_t Vid; // min voltage in SVI2 VID
> +} DisplayClockTable_t;
> +
> +typedef struct {
> + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
> + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
> + uint16_t MinMclk;
> + uint16_t MaxMclk;
> +
> + uint8_t WmSetting;
> + uint8_t WmType; // Used for normal pstate change or memory retraining
> + uint8_t Padding[2];
> +} WatermarkRowGeneric_t;
> +
> +#define NUM_WM_RANGES 4
> +#define WM_PSTATE_CHG 0
> +#define WM_RETRAINING 1
> +
> +typedef enum {
> + WM_SOCCLK = 0,
> + WM_DCFCLK,
> + WM_COUNT,
> +} WM_CLOCK_e;
> +
> +typedef struct {
> + // Watermarks
> + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
> +
> + uint32_t MmHubPadding[7]; // SMU internal use
> +} Watermarks_t;
> +
> +typedef enum {
> + CUSTOM_DPM_SETTING_GFXCLK,
> + CUSTOM_DPM_SETTING_CCLK,
> + CUSTOM_DPM_SETTING_FCLK_CCX,
> + CUSTOM_DPM_SETTING_FCLK_GFX,
> + CUSTOM_DPM_SETTING_FCLK_STALLS,
> + CUSTOM_DPM_SETTING_LCLK,
> + CUSTOM_DPM_SETTING_COUNT,
> +} CUSTOM_DPM_SETTING_e;
> +
> +typedef struct {
> + uint8_t ActiveHystLimit;
> + uint8_t IdleHystLimit;
> + uint8_t FPS;
> + uint8_t MinActiveFreqType;
> + FloatInIntFormat_t MinActiveFreq;
> + FloatInIntFormat_t PD_Data_limit;
> + FloatInIntFormat_t PD_Data_time_constant;
> + FloatInIntFormat_t PD_Data_error_coeff;
> + FloatInIntFormat_t PD_Data_error_rate_coeff;
> +} DpmActivityMonitorCoeffExt_t;
> +
> +typedef struct {
> + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
> +} CustomDpmSettings_t;
> +
> +#define NUM_DCFCLK_DPM_LEVELS 6
> +#define NUM_DISPCLK_DPM_LEVELS 6
> +#define NUM_DPPCLK_DPM_LEVELS 6
> +#define NUM_SOCCLK_DPM_LEVELS 8
> +#define NUM_ISPICLK_DPM_LEVELS 6
> +#define NUM_ISPXCLK_DPM_LEVELS 6
> +#define NUM_VCN_DPM_LEVELS 8
> +#define NUM_FCLK_DPM_LEVELS 4
> +#define NUM_SOC_VOLTAGE_LEVELS 8
> +
> +typedef struct {
> + uint32_t fclk;
> + uint32_t memclk;
> + uint32_t voltage;
> +} df_pstate_t;
> +
> +typedef struct {
> + uint32_t vclk;
> + uint32_t dclk;
> +} vcn_clk_t;
> +
> +//Freq in MHz
> +//Voltage in milli volts with 2 fractional bits
> +
> +typedef struct {
> + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
> + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
> + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
> + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
> + uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
> + uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
> + vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
> +
> + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
> +
> + df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
> +
> + uint32_t MinGfxClk;
> + uint32_t MaxGfxClk;
> +
> + uint8_t NumDfPstatesEnabled;
> + uint8_t NumDpmLevelsEnabled;
> + uint8_t spare[2];
> +} DpmClocks_t;
> +
> +
> +// Throttler Status Bitmask
> +#define THROTTLER_STATUS_BIT_SPL 0
> +#define THROTTLER_STATUS_BIT_FPPT 1
> +#define THROTTLER_STATUS_BIT_SPPT 2
> +#define THROTTLER_STATUS_BIT_SPPT_APU 3
> +#define THROTTLER_STATUS_BIT_THM_CORE 4
> +#define THROTTLER_STATUS_BIT_THM_GFX 5
> +#define THROTTLER_STATUS_BIT_THM_SOC 6
> +#define THROTTLER_STATUS_BIT_TDC_VDD 7
> +#define THROTTLER_STATUS_BIT_TDC_SOC 8
> +#define THROTTLER_STATUS_BIT_TDC_GFX 9
> +#define THROTTLER_STATUS_BIT_TDC_CVIP 10
> +
> +typedef struct {
> + uint16_t AverageGfxclkFrequency; //[MHz]
> + uint16_t AverageSocclkFrequency; //[MHz]
> + uint16_t AverageVclkFrequency; //[MHz]
> + uint16_t AverageDclkFrequency; //[MHz]
> + uint16_t AverageMemclkFrequency; //[MHz]
> + uint16_t spare;
> +
> + uint16_t AverageGfxActivity; //[centi]
> + uint16_t AverageUvdActivity; //[centi]
> +
> + uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> + uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> + uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> + uint16_t CurrentSocketPower; //[mW]
> +
> + //3rd party tools in Windows need this info in the case of APUs
> + uint16_t CoreFrequency[8]; //[MHz]
> + uint16_t CorePower[8]; //[mW]
> + uint16_t CoreTemperature[8]; //[centi-Celsius]
> + uint16_t L3Frequency[2]; //[MHz]
> + uint16_t L3Temperature[2]; //[centi-Celsius]
> +
> + uint16_t GfxTemperature; //[centi-Celsius]
> + uint16_t SocTemperature; //[centi-Celsius]
> + uint16_t EdgeTemperature;
> + uint16_t ThrottlerStatus;
> +} SmuMetrics_t;
> +
> +
> +// Workload bits
> +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
> +#define WORKLOAD_PPLIB_VIDEO_BIT 2
> +#define WORKLOAD_PPLIB_VR_BIT 3
> +#define WORKLOAD_PPLIB_COMPUTE_BIT 4
> +#define WORKLOAD_PPLIB_CUSTOM_BIT 5
> +#define WORKLOAD_PPLIB_COUNT 6
> +
> +#define TABLE_BIOS_IF 0 // Called by BIOS
> +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
> +#define TABLE_CUSTOM_DPM 2 // Called by Driver
> +#define TABLE_SPARE1 3
> +#define TABLE_DPMCLOCKS 4 // Called by Driver
> +#define TABLE_MOMENTARY_PM 5 // Called by Tools
> +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
> +#define TABLE_SMU_METRICS 7 // Called by Driver
> +#define TABLE_COUNT 8
> +
> +//ISP tile definitions
> +typedef enum {
> + TILE_ISPX = 0, // ISPX
> + TILE_ISPM, // ISPM
> + TILE_ISPC, // ISPCORE
> + TILE_ISPPRE, // ISPPRE
> + TILE_ISPPOST, // ISPPOST
> + TILE_MAX
> +} TILE_NUM_e;
> +
> +// Tile Selection (Based on arguments)
> +#define TILE_SEL_ISPX (1<<(TILE_ISPX))
> +#define TILE_SEL_ISPM (1<<(TILE_ISPM))
> +#define TILE_SEL_ISPC (1<<(TILE_ISPC))
> +#define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE))
> +#define TILE_SEL_ISPPOST (1<<(TILE_ISPPOST))
> +
> +// Mask for ISP tiles in PGFSM PWR Status Registers
> +//Bit[1:0] maps to ISPX, (ISPX)
> +//Bit[3:2] maps to ISPM, (ISPM)
> +//Bit[5:4] maps to ISPCORE, (ISPCORE)
> +//Bit[7:6] maps to ISPPRE, (ISPPRE)
> +//Bit[9:8] maps to POST, (ISPPOST
> +#define TILE_ISPX_MASK ((1<<0) | (1<<1))
> +#define TILE_ISPM_MASK ((1<<2) | (1<<3))
> +#define TILE_ISPC_MASK ((1<<4) | (1<<5))
> +#define TILE_ISPPRE_MASK ((1<<6) | (1<<7))
> +#define TILE_ISPPOST_MASK ((1<<8) | (1<<9))
> +
> +#endif
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh
2020-09-28 21:41 ` Luben Tuikov
@ 2020-09-29 14:39 ` Alex Deucher
0 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 14:39 UTC (permalink / raw)
To: Luben Tuikov
Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du, amd-gfx list
On Mon, Sep 28, 2020 at 5:41 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Xiaojian Du <xiaojian.du@amd.com>
> >
> > This patch is to add smu v11.5 driver interface header for vangogh.
> >
> > Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
> > Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > .../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 239 ++++++++++++++++++
> > 1 file changed, 239 insertions(+)
> > create mode 100644 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
> >
> > diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
> > new file mode 100644
> > index 000000000000..20f8c6f460b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
> > @@ -0,0 +1,239 @@
> > +/*
> > + * Copyright 2020 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + */
> > +#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
> > +#define __SMU11_DRIVER_IF_VANGOGH_H__
> > +
> > +// *** IMPORTANT ***
> > +// SMU TEAM: Always increment the interface version if
> > +// any structure is changed in this file
> > +#define SMU13_DRIVER_IF_VERSION 2
> > +
> > +typedef struct {
> > + int32_t value;
> > + uint32_t numFractionalBits;
> > +} FloatInIntFormat_t;
>
> GNU-style indentation as opposed to Linux-style
> throughout this file.
This file is shared across components. I'd like to minimize the
differences for when we update it.
Alex
>
> Regards,
> Luben
>
> > +
> > +typedef enum {
> > + DSPCLK_DCFCLK = 0,
> > + DSPCLK_DISPCLK,
> > + DSPCLK_PIXCLK,
> > + DSPCLK_PHYCLK,
> > + DSPCLK_COUNT,
> > +} DSPCLK_e;
> > +
> > +typedef struct {
> > + uint16_t Freq; // in MHz
> > + uint16_t Vid; // min voltage in SVI2 VID
> > +} DisplayClockTable_t;
> > +
> > +typedef struct {
> > + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
> > + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
> > + uint16_t MinMclk;
> > + uint16_t MaxMclk;
> > +
> > + uint8_t WmSetting;
> > + uint8_t WmType; // Used for normal pstate change or memory retraining
> > + uint8_t Padding[2];
> > +} WatermarkRowGeneric_t;
> > +
> > +#define NUM_WM_RANGES 4
> > +#define WM_PSTATE_CHG 0
> > +#define WM_RETRAINING 1
> > +
> > +typedef enum {
> > + WM_SOCCLK = 0,
> > + WM_DCFCLK,
> > + WM_COUNT,
> > +} WM_CLOCK_e;
> > +
> > +typedef struct {
> > + // Watermarks
> > + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
> > +
> > + uint32_t MmHubPadding[7]; // SMU internal use
> > +} Watermarks_t;
> > +
> > +typedef enum {
> > + CUSTOM_DPM_SETTING_GFXCLK,
> > + CUSTOM_DPM_SETTING_CCLK,
> > + CUSTOM_DPM_SETTING_FCLK_CCX,
> > + CUSTOM_DPM_SETTING_FCLK_GFX,
> > + CUSTOM_DPM_SETTING_FCLK_STALLS,
> > + CUSTOM_DPM_SETTING_LCLK,
> > + CUSTOM_DPM_SETTING_COUNT,
> > +} CUSTOM_DPM_SETTING_e;
> > +
> > +typedef struct {
> > + uint8_t ActiveHystLimit;
> > + uint8_t IdleHystLimit;
> > + uint8_t FPS;
> > + uint8_t MinActiveFreqType;
> > + FloatInIntFormat_t MinActiveFreq;
> > + FloatInIntFormat_t PD_Data_limit;
> > + FloatInIntFormat_t PD_Data_time_constant;
> > + FloatInIntFormat_t PD_Data_error_coeff;
> > + FloatInIntFormat_t PD_Data_error_rate_coeff;
> > +} DpmActivityMonitorCoeffExt_t;
> > +
> > +typedef struct {
> > + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
> > +} CustomDpmSettings_t;
> > +
> > +#define NUM_DCFCLK_DPM_LEVELS 6
> > +#define NUM_DISPCLK_DPM_LEVELS 6
> > +#define NUM_DPPCLK_DPM_LEVELS 6
> > +#define NUM_SOCCLK_DPM_LEVELS 8
> > +#define NUM_ISPICLK_DPM_LEVELS 6
> > +#define NUM_ISPXCLK_DPM_LEVELS 6
> > +#define NUM_VCN_DPM_LEVELS 8
> > +#define NUM_FCLK_DPM_LEVELS 4
> > +#define NUM_SOC_VOLTAGE_LEVELS 8
> > +
> > +typedef struct {
> > + uint32_t fclk;
> > + uint32_t memclk;
> > + uint32_t voltage;
> > +} df_pstate_t;
> > +
> > +typedef struct {
> > + uint32_t vclk;
> > + uint32_t dclk;
> > +} vcn_clk_t;
> > +
> > +//Freq in MHz
> > +//Voltage in milli volts with 2 fractional bits
> > +
> > +typedef struct {
> > + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
> > + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
> > + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
> > + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
> > + uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
> > + uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
> > + vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
> > +
> > + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
> > +
> > + df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
> > +
> > + uint32_t MinGfxClk;
> > + uint32_t MaxGfxClk;
> > +
> > + uint8_t NumDfPstatesEnabled;
> > + uint8_t NumDpmLevelsEnabled;
> > + uint8_t spare[2];
> > +} DpmClocks_t;
> > +
> > +
> > +// Throttler Status Bitmask
> > +#define THROTTLER_STATUS_BIT_SPL 0
> > +#define THROTTLER_STATUS_BIT_FPPT 1
> > +#define THROTTLER_STATUS_BIT_SPPT 2
> > +#define THROTTLER_STATUS_BIT_SPPT_APU 3
> > +#define THROTTLER_STATUS_BIT_THM_CORE 4
> > +#define THROTTLER_STATUS_BIT_THM_GFX 5
> > +#define THROTTLER_STATUS_BIT_THM_SOC 6
> > +#define THROTTLER_STATUS_BIT_TDC_VDD 7
> > +#define THROTTLER_STATUS_BIT_TDC_SOC 8
> > +#define THROTTLER_STATUS_BIT_TDC_GFX 9
> > +#define THROTTLER_STATUS_BIT_TDC_CVIP 10
> > +
> > +typedef struct {
> > + uint16_t AverageGfxclkFrequency; //[MHz]
> > + uint16_t AverageSocclkFrequency; //[MHz]
> > + uint16_t AverageVclkFrequency; //[MHz]
> > + uint16_t AverageDclkFrequency; //[MHz]
> > + uint16_t AverageMemclkFrequency; //[MHz]
> > + uint16_t spare;
> > +
> > + uint16_t AverageGfxActivity; //[centi]
> > + uint16_t AverageUvdActivity; //[centi]
> > +
> > + uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> > + uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> > + uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
> > + uint16_t CurrentSocketPower; //[mW]
> > +
> > + //3rd party tools in Windows need this info in the case of APUs
> > + uint16_t CoreFrequency[8]; //[MHz]
> > + uint16_t CorePower[8]; //[mW]
> > + uint16_t CoreTemperature[8]; //[centi-Celsius]
> > + uint16_t L3Frequency[2]; //[MHz]
> > + uint16_t L3Temperature[2]; //[centi-Celsius]
> > +
> > + uint16_t GfxTemperature; //[centi-Celsius]
> > + uint16_t SocTemperature; //[centi-Celsius]
> > + uint16_t EdgeTemperature;
> > + uint16_t ThrottlerStatus;
> > +} SmuMetrics_t;
> > +
> > +
> > +// Workload bits
> > +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
> > +#define WORKLOAD_PPLIB_VIDEO_BIT 2
> > +#define WORKLOAD_PPLIB_VR_BIT 3
> > +#define WORKLOAD_PPLIB_COMPUTE_BIT 4
> > +#define WORKLOAD_PPLIB_CUSTOM_BIT 5
> > +#define WORKLOAD_PPLIB_COUNT 6
> > +
> > +#define TABLE_BIOS_IF 0 // Called by BIOS
> > +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
> > +#define TABLE_CUSTOM_DPM 2 // Called by Driver
> > +#define TABLE_SPARE1 3
> > +#define TABLE_DPMCLOCKS 4 // Called by Driver
> > +#define TABLE_MOMENTARY_PM 5 // Called by Tools
> > +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
> > +#define TABLE_SMU_METRICS 7 // Called by Driver
> > +#define TABLE_COUNT 8
> > +
> > +//ISP tile definitions
> > +typedef enum {
> > + TILE_ISPX = 0, // ISPX
> > + TILE_ISPM, // ISPM
> > + TILE_ISPC, // ISPCORE
> > + TILE_ISPPRE, // ISPPRE
> > + TILE_ISPPOST, // ISPPOST
> > + TILE_MAX
> > +} TILE_NUM_e;
> > +
> > +// Tile Selection (Based on arguments)
> > +#define TILE_SEL_ISPX (1<<(TILE_ISPX))
> > +#define TILE_SEL_ISPM (1<<(TILE_ISPM))
> > +#define TILE_SEL_ISPC (1<<(TILE_ISPC))
> > +#define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE))
> > +#define TILE_SEL_ISPPOST (1<<(TILE_ISPPOST))
> > +
> > +// Mask for ISP tiles in PGFSM PWR Status Registers
> > +//Bit[1:0] maps to ISPX, (ISPX)
> > +//Bit[3:2] maps to ISPM, (ISPM)
> > +//Bit[5:4] maps to ISPCORE, (ISPCORE)
> > +//Bit[7:6] maps to ISPPRE, (ISPPRE)
> > +//Bit[9:8] maps to POST, (ISPPOST
> > +#define TILE_ISPX_MASK ((1<<0) | (1<<1))
> > +#define TILE_ISPM_MASK ((1<<2) | (1<<3))
> > +#define TILE_ISPC_MASK ((1<<4) | (1<<5))
> > +#define TILE_ISPPRE_MASK ((1<<6) | (1<<7))
> > +#define TILE_ISPPOST_MASK ((1<<8) | (1<<9))
> > +
> > +#endif
> >
>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (25 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh Alex Deucher
` (16 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add smu v11.5 firmware header for vangogh
v2: squash in updates
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 120 ++++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
new file mode 100644
index 000000000000..abf13abd3919
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU_V11_5_0_PMFW_H__
+#define __SMU_V11_5_0_PMFW_H__
+
+#include "smu11_driver_if_vangogh.h"
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+// Feature Control Defines
+#define FEATURE_CCLK_DPM_BIT 0
+#define FEATURE_FAN_CONTROLLER_BIT 1
+#define FEATURE_DATA_CALCULATION_BIT 2
+#define FEATURE_PPT_BIT 3
+#define FEATURE_TDC_BIT 4
+#define FEATURE_THERMAL_BIT 5
+#define FEATURE_FIT_BIT 6
+#define FEATURE_EDC_BIT 7
+#define FEATURE_PLL_POWER_DOWN_BIT 8
+#define FEATURE_ULV_BIT 9
+#define FEATURE_VDDOFF_BIT 10
+#define FEATURE_VCN_DPM_BIT 11
+#define FEATURE_CSTATE_BOOST_BIT 12
+#define FEATURE_FCLK_DPM_BIT 13
+#define FEATURE_SOCCLK_DPM_BIT 14
+#define FEATURE_MP0CLK_DPM_BIT 15
+#define FEATURE_LCLK_DPM_BIT 16
+#define FEATURE_SHUBCLK_DPM_BIT 17
+#define FEATURE_DCFCLK_DPM_BIT 18
+#define FEATURE_GFX_DPM_BIT 19
+#define FEATURE_DS_GFXCLK_BIT 20
+#define FEATURE_DS_SOCCLK_BIT 21
+#define FEATURE_DS_LCLK_BIT 22
+#define FEATURE_DS_DCFCLK_BIT 23
+#define FEATURE_DS_SHUBCLK_BIT 24
+#define FEATURE_GFX_TEMP_VMIN_BIT 25
+#define FEATURE_S0I2_BIT 26
+#define FEATURE_WHISPER_MODE_BIT 27
+#define FEATURE_DS_FCLK_BIT 28
+#define FEATURE_DS_SMNCLK_BIT 29
+#define FEATURE_DS_MP1CLK_BIT 30
+#define FEATURE_DS_MP0CLK_BIT 31
+#define FEATURE_SMU_LOW_POWER_BIT 32
+#define FEATURE_FUSE_PG_BIT 33
+#define FEATURE_GFX_DEM_BIT 34
+#define FEATURE_PSI_BIT 35
+#define FEATURE_PROCHOT_BIT 36
+#define FEATURE_CPUOFF_BIT 37
+#define FEATURE_STAPM_BIT 38
+#define FEATURE_S0I3_BIT 39
+#define FEATURE_DF_CSTATES_BIT 40
+#define FEATURE_PERF_LIMIT_BIT 41
+#define FEATURE_CORE_DLDO_BIT 42
+#define FEATURE_RSMU_LOW_POWER_BIT 43
+#define FEATURE_SMN_LOW_POWER_BIT 44
+#define FEATURE_THM_LOW_POWER_BIT 45
+#define FEATURE_SMUIO_LOW_POWER_BIT 46
+#define FEATURE_MP1_LOW_POWER_BIT 47
+#define FEATURE_DS_VCN_BIT 48
+#define FEATURE_CPPC_BIT 49
+#define FEATURE_OS_CSTATES_BIT 50
+#define FEATURE_ISP_DPM_BIT 51
+#define FEATURE_A55_DPM_BIT 52
+#define FEATURE_CVIP_DSP_DPM_BIT 53
+#define FEATURE_MSMU_LOW_POWER_BIT 54
+#define FEATURE_SOC_VOLTAGE_MON_BIT 55
+#define FEATURE_ATHUB_PG_BIT 56
+#define FEATURE_ECO_DEEPCSTATE_BIT 57
+#define FEATURE_CC6 58
+#define NUM_FEATURES 59
+
+typedef struct {
+ // MP1_EXT_SCRATCH0
+ uint32_t DpmHandlerID : 8;
+ uint32_t ActivityMonitorID : 8;
+ uint32_t DpmTimerID : 8;
+ uint32_t spare0 : 8;
+ // MP1_EXT_SCRATCH1
+ uint32_t GfxStatus : 2;
+ uint32_t GfxoffStatus : 8;
+ uint32_t CpuOff : 1;
+ uint32_t VddOff : 1;
+ uint32_t InUlv : 1;
+ uint32_t InS0i2 : 2;
+ uint32_t InWhisperMode : 1;
+ uint32_t spare1 : 16;
+ // MP1_EXT_SCRATCH2
+ uint32_t P2JobHandler : 32;
+ // MP1_EXT_SCRATCH3
+// uint32_t spare2 : 32;
+ // MP1_EXT_SCRATCH4:6 are used by Kernel
+} FwStatus_t;
+
+
+#pragma pack(pop)
+
+#endif
--
2.25.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (26 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) Alex Deucher
` (15 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add smu v11.5 smc header for vangogh.
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 86 ++++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
new file mode 100644
index 000000000000..55c1b151a68d
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_11_5_0_PPSMC_H
+#define SMU_11_5_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_EnableGfxOff 0x4
+#define PPSMC_MSG_DisableGfxOff 0x5
+#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile 0x7
+#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn 0x9
+#define PPSMC_MSG_spare 0xA
+#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
+#define PPSMC_MSG_SetMinVideoGfxclkFreq 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
+#define PPSMC_MSG_ActiveProcessNotify 0xD
+#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
+#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
+#define PPSMC_MSG_SetDriverDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
+#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
+#define PPSMC_MSG_spare1 0x16
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
+#define PPSMC_MSG_SetMinVideoFclkFreq 0x18
+#define PPSMC_MSG_SetSoftMinVcn 0x19
+#define PPSMC_MSG_EnablePostCode 0x1A
+#define PPSMC_MSG_GetGfxclkFrequency 0x1B
+#define PPSMC_MSG_GetFclkFrequency 0x1C
+#define PPSMC_MSG_AllowGfxOff 0x1D
+#define PPSMC_MSG_DisallowGfxOff 0x1E
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
+#define PPSMC_MSG_SetHardMinGfxClk 0x20
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
+#define PPSMC_MSG_SetSoftMaxVcn 0x23
+#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM
+#define PPSMC_MSG_SetPowerLimitPercentage 0x25
+#define PPSMC_MSG_PowerDownJpeg 0x26
+#define PPSMC_MSG_PowerUpJpeg 0x27
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
+#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
+#define PPSMC_MSG_PowerUpCvip 0x2A
+#define PPSMC_MSG_PowerDownCvip 0x2B
+#define PPSMC_Message_Count 0x2C
+
+//Argument for PPSMC_MSG_GpuChangeState
+enum {
+ GpuChangeState_D0Entry = 1,
+ GpuChangeState_D3Entry,
+};
+
+#endif
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (27 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2) Alex Deucher
` (14 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add vangogh asic name in smu v11.
v2: drop smu firmware name (N/A for VG)
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 03198d214bba..f57dc586649a 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -32,6 +32,7 @@
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
+#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
/* MP Apertures */
#define MP0_Public 0x03800000
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index d8ca6d968813..effa4391b577 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -244,6 +244,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case CHIP_NAVY_FLOUNDER:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break;
+ case CHIP_VANGOGH:
+ smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
+ break;
default:
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (28 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh Alex Deucher
` (13 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Kevin Wang, Huang Rui, Xiaojian Du
From: Xiaojian Du <xiaojian.du@amd.com>
This patch is to add smu initialize functions for vangogh.
v2: squash in updates
Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 355 ++++++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 30 ++
2 files changed, 385 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
new file mode 100644
index 000000000000..a06495126a8c
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v11_0.h"
+#include "smu11_driver_if_vangogh.h"
+#include "vangogh_ppt.h"
+#include "smu_v11_5_ppsmc.h"
+#include "smu_v11_5_pmfw.h"
+#include "smu_cmn.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+ FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_A55_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_CVIP_DSP_DPM_BIT))
+
+static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
+ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
+ MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
+ MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
+ MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
+ MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
+ MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
+ MSG_MAP(Spare, PPSMC_MSG_spare, 1),
+ MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
+ MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
+ MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
+ MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 1),
+ MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 1),
+ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
+ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
+ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
+ MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
+ MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
+ MSG_MAP(Spare1, PPSMC_MSG_spare1, 1),
+ MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
+ MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
+ MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
+ MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
+ MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
+ MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
+ MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
+ MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
+ MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
+ MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
+ MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
+ MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
+ MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
+ MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
+ MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
+ MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
+ MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
+ MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
+ MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 1),
+ MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 1),
+};
+
+static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
+ FEA_MAP(PPT),
+ FEA_MAP(TDC),
+ FEA_MAP(THERMAL),
+ FEA_MAP(DS_GFXCLK),
+ FEA_MAP(DS_SOCCLK),
+ FEA_MAP(DS_LCLK),
+ FEA_MAP(DS_FCLK),
+ FEA_MAP(DS_MP1CLK),
+ FEA_MAP(DS_MP0CLK),
+ FEA_MAP(ATHUB_PG),
+ FEA_MAP(CCLK_DPM),
+ FEA_MAP(FAN_CONTROLLER),
+ FEA_MAP(ULV),
+ FEA_MAP(VCN_DPM),
+ FEA_MAP(FCLK_DPM),
+ FEA_MAP(SOCCLK_DPM),
+ FEA_MAP(MP0CLK_DPM),
+ FEA_MAP(LCLK_DPM),
+ FEA_MAP(SHUBCLK_DPM),
+ FEA_MAP(DCFCLK_DPM),
+ FEA_MAP(GFX_DPM),
+ FEA_MAP(DS_DCFCLK),
+ FEA_MAP(S0I2),
+ FEA_MAP(SMU_LOW_POWER),
+ FEA_MAP(GFX_DEM),
+ FEA_MAP(PSI),
+ FEA_MAP(PROCHOT),
+ FEA_MAP(CPUOFF),
+ FEA_MAP(STAPM),
+ FEA_MAP(S0I3),
+ FEA_MAP(DF_CSTATES),
+ FEA_MAP(PERF_LIMIT),
+ FEA_MAP(CORE_DLDO),
+ FEA_MAP(RSMU_LOW_POWER),
+ FEA_MAP(SMN_LOW_POWER),
+ FEA_MAP(THM_LOW_POWER),
+ FEA_MAP(SMUIO_LOW_POWER),
+ FEA_MAP(MP1_LOW_POWER),
+ FEA_MAP(DS_VCN),
+ FEA_MAP(CPPC),
+ FEA_MAP(OS_CSTATES),
+ FEA_MAP(ISP_DPM),
+ FEA_MAP(A55_DPM),
+ FEA_MAP(CVIP_DSP_DPM),
+ FEA_MAP(MSMU_LOW_POWER),
+};
+
+static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP_VALID(WATERMARKS),
+ TAB_MAP_VALID(SMU_METRICS),
+ TAB_MAP_VALID(CUSTOM_DPM),
+ TAB_MAP_VALID(DPMCLOCKS),
+};
+
+static int vangogh_tables_init(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = smu_table->tables;
+
+ SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ if (!smu_table->metrics_table)
+ goto err0_out;
+ smu_table->metrics_time = 0;
+
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
+ smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
+ if (!smu_table->gpu_metrics_table)
+ goto err1_out;
+
+ smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
+ if (!smu_table->watermarks_table)
+ goto err2_out;
+
+ return 0;
+
+err2_out:
+ kfree(smu_table->gpu_metrics_table);
+err1_out:
+ kfree(smu_table->metrics_table);
+err0_out:
+ return -ENOMEM;
+}
+
+static int vangogh_allocate_dpm_context(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
+ GFP_KERNEL);
+ if (!smu_dpm->dpm_context)
+ return -ENOMEM;
+
+ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
+
+ return 0;
+}
+
+static int vangogh_init_smc_tables(struct smu_context *smu)
+{
+ int ret = 0;
+
+ ret = vangogh_tables_init(smu);
+ if (ret)
+ return ret;
+
+ ret = vangogh_allocate_dpm_context(smu);
+ if (ret)
+ return ret;
+
+ return smu_v11_0_init_smc_tables(smu);
+}
+
+static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+{
+ int ret = 0;
+
+ if (enable) {
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
+ if (ret)
+ return ret;
+ }
+ } else {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+ int ret = 0;
+
+ if (enable) {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
+ if (ret)
+ return ret;
+ }
+ } else {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int vangogh_set_default_dpm_table(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+}
+
+static int vangogh_get_allowed_feature_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ if (num > 2)
+ return -EINVAL;
+
+ memset(feature_mask, 0, sizeof(uint32_t) * num);
+
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT)
+ | FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)
+ | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_PPT_BIT)
+ | FEATURE_MASK(FEATURE_TDC_BIT)
+ | FEATURE_MASK(FEATURE_FAN_CONTROLLER_BIT)
+ | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
+
+ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT);
+
+ if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT);
+
+ if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+
+ return 0;
+}
+
+static bool vangogh_is_dpm_running(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ /*
+ * Until now, the pmfw hasn't exported the interface of SMU
+ * feature mask to APU SKU so just force on all the feature
+ * at early initial stage.
+ */
+ if (adev->in_suspend)
+ return false;
+ else
+ return true;
+
+}
+
+static const struct pptable_funcs vangogh_ppt_funcs = {
+ .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
+ .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
+ .check_fw_status = smu_v11_0_check_fw_status,
+ .check_fw_version = smu_v11_0_check_fw_version,
+ .init_smc_tables = vangogh_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
+ .register_irq_handler = smu_v11_0_register_irq_handler,
+ .get_allowed_feature_mask = vangogh_get_allowed_feature_mask,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
+ .send_smc_msg = smu_cmn_send_smc_msg,
+ .set_default_dpm_table = vangogh_set_default_dpm_table,
+ .is_dpm_running = vangogh_is_dpm_running,
+ .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+ .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
+ .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
+};
+
+void vangogh_set_ppt_funcs(struct smu_context *smu)
+{
+ smu->ppt_funcs = &vangogh_ppt_funcs;
+ smu->message_map = vangogh_message_map;
+ smu->feature_map = vangogh_feature_mask_map;
+ smu->table_map = vangogh_table_map;
+ smu->is_apu = true;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
new file mode 100644
index 000000000000..29929b360db8
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_PPT_H__
+#define __VANGOGH_PPT_H__
+
+
+extern void vangogh_set_ppt_funcs(struct smu_context *smu);
+
+#endif
\ No newline at end of file
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (29 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU Alex Deucher
` (12 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Huang Rui <ray.huang@amd.com>
This patch is to partially enable swSMU for vangogh for the moment.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3010cb31324a..5534125f1df3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -466,6 +466,9 @@ static int smu_late_init(void *handle)
struct smu_context *smu = &adev->smu;
int ret = 0;
+ if (adev->asic_type == CHIP_VANGOGH)
+ return 0;
+
if (!smu->pm_enabled)
return 0;
@@ -1090,6 +1093,9 @@ static int smu_hw_init(void *handle)
smu_set_gfx_cgpg(&adev->smu, true);
}
+ if (adev->asic_type == CHIP_VANGOGH)
+ return 0;
+
if (!smu->pm_enabled)
return 0;
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (30 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 34/45] drm/amdgpu: add smu ip block for vangogh Alex Deucher
` (11 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add vangogh ppt funcions into swSMU block.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5534125f1df3..d4cc2825d364 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -33,6 +33,7 @@
#include "navi10_ppt.h"
#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
+#include "vangogh_ppt.h"
#include "amd_pcie.h"
/*
@@ -401,6 +402,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
case CHIP_RENOIR:
renoir_set_ppt_funcs(smu);
break;
+ case CHIP_VANGOGH:
+ vangogh_set_ppt_funcs(smu);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
index f98d97192635..0138c982dfd3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
@@ -26,6 +26,7 @@
SMU11_MGR = arcturus_ppt.o \
navi10_ppt.o \
sienna_cichlid_ppt.o \
+ vangogh_ppt.o \
smu_v11_0.o
AMD_SWSMU_SMU11MGR = $(addprefix $(AMD_SWSMU_PATH)/smu11/,$(SMU11_MGR))
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 34/45] drm/amdgpu: add smu ip block for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (31 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 35/45] drm/amdgpu: add TOC firmware definition Alex Deucher
` (10 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Huang Rui <ray.huang@amd.com>
This patch is to add ip block for vangogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 3ac89109ea3e..4fbf3f6640e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -644,6 +644,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 35/45] drm/amdgpu: add TOC firmware definition
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (32 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 34/45] drm/amdgpu: add smu ip block for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2) Alex Deucher
` (9 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add TOC firmware definition on uapi.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d98d4e6f311b..64ae821b01ef 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -727,6 +727,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_TA 0x13
/* Subquery id: Query DMCUB firmware version */
#define AMDGPU_INFO_FW_DMCUB 0x14
+ /* Subquery id: Query TOC firmware version */
+ #define AMDGPU_INFO_FW_TOC 0x15
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (33 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 35/45] drm/amdgpu: add TOC firmware definition Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-28 22:26 ` Luben Tuikov
2020-09-25 20:10 ` [PATCH 37/45] drm/amdgpu: enable psp support for vangogh Alex Deucher
` (8 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
APU needs load toc firmware for gfx10 series on psp front door loading.
v2: rebase against latest code
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 ++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +++++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ++++++++++++++++-------
4 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bd0d14419841..26caa8d43483 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->dm.dmcub_fw_version;
fw_info->feature = 0;
break;
+ case AMDGPU_INFO_FW_TOC:
+ fw_info->ver = adev->psp.toc_fw_version;
+ fw_info->feature = adev->psp.toc_feature_version;
+ break;
default:
return -EINVAL;
}
@@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
fw_info.feature, fw_info.ver);
+ /* TOC */
+ query_fw.fw_type = AMDGPU_INFO_FW_TOC;
+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+ if (ret)
+ return ret;
+ seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 18be544d8c1e..c8cec7ab499d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
return err;
}
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name)
+{
+ struct amdgpu_device *adev = psp->adev;
+ char fw_name[30];
+ const struct psp_firmware_header_v1_0 *toc_hdr;
+ int err = 0;
+
+ if (!chip_name) {
+ dev_err(adev->dev, "invalid chip name for toc microcode\n");
+ return -EINVAL;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
+ err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = amdgpu_ucode_validate(adev->psp.toc_fw);
+ if (err)
+ goto out;
+
+ toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
+ adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
+ adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
+ adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
+ adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
+ le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
+ return 0;
+out:
+ dev_err(adev->dev, "fail to initialize toc microcode\n");
+ release_firmware(adev->psp.toc_fw);
+ adev->psp.toc_fw = NULL;
+ return err;
+}
+
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 919d2fb7427b..13f56618660a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -253,6 +253,11 @@ struct psp_context
uint32_t asd_ucode_size;
uint8_t *asd_start_addr;
+ /* toc firmware */
+ const struct firmware *toc_fw;
+ uint32_t toc_fw_version;
+ uint32_t toc_feature_version;
+
/* fence buffer */
struct amdgpu_bo *fence_buf_bo;
uint64_t fence_buf_mc_addr;
@@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
int index);
int psp_init_asd_microcode(struct psp_context *psp,
const char *chip_name);
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name);
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name);
int psp_init_ta_microcode(struct psp_context *psp,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c5d9612abcb..f2d6b2518eee 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -109,20 +109,16 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
BUG();
}
- err = psp_init_sos_microcode(psp, chip_name);
- if (err)
- return err;
-
- if (adev->asic_type != CHIP_SIENNA_CICHLID &&
- adev->asic_type != CHIP_NAVY_FLOUNDER) {
- err = psp_init_asd_microcode(psp, chip_name);
- if (err)
- return err;
- }
switch (adev->asic_type) {
case CHIP_VEGA20:
case CHIP_ARCTURUS:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
if (err) {
@@ -150,6 +146,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
if (amdgpu_sriov_vf(adev))
break;
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
@@ -180,10 +182,21 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
err = psp_init_ta_microcode(&adev->psp, chip_name);
if (err)
return err;
break;
+ case CHIP_VANGOGH:
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_toc_microcode(psp, chip_name);
+ if (err)
+ return err;
+ break;
default:
BUG();
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2)
2020-09-25 20:10 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2) Alex Deucher
@ 2020-09-28 22:26 ` Luben Tuikov
2020-09-29 15:09 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 22:26 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> APU needs load toc firmware for gfx10 series on psp front door loading.
>
> v2: rebase against latest code
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 ++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +++++
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ++++++++++++++++-------
> 4 files changed, 77 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index bd0d14419841..26caa8d43483 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
> fw_info->ver = adev->dm.dmcub_fw_version;
> fw_info->feature = 0;
> break;
> + case AMDGPU_INFO_FW_TOC:
> + fw_info->ver = adev->psp.toc_fw_version;
> + fw_info->feature = adev->psp.toc_feature_version;
> + break;
> default:
> return -EINVAL;
> }
> @@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
> seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
> fw_info.feature, fw_info.ver);
>
> + /* TOC */
> + query_fw.fw_type = AMDGPU_INFO_FW_TOC;
> + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
> + if (ret)
> + return ret;
> + seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
> + fw_info.feature, fw_info.ver);
>
> seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 18be544d8c1e..c8cec7ab499d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
> return err;
> }
>
> +int psp_init_toc_microcode(struct psp_context *psp,
> + const char *chip_name)
> +{
> + struct amdgpu_device *adev = psp->adev;
> + char fw_name[30];
> + const struct psp_firmware_header_v1_0 *toc_hdr;
> + int err = 0;
> +
> + if (!chip_name) {
> + dev_err(adev->dev, "invalid chip name for toc microcode\n");
> + return -EINVAL;
> + }
> +
> + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
> + err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
> + if (err)
> + goto out;
> +
> + err = amdgpu_ucode_validate(adev->psp.toc_fw);
> + if (err)
> + goto out;
> +
> + toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
> + adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
> + adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
> + adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
> + adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
> + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
> + return 0;
> +out:
I'd rather this label be "Err:".
Regardless of whether there already is a variable "err",
(there is!), capitalizing goto labels is good practice, since
it distinguishes them from variables (which are all lowercase),
and macros (which are all caps). Plus, you also avoid conflict
with the eponymous variable.
> + dev_err(adev->dev, "fail to initialize toc microcode\n");
That's a very misleading message. Please print this instead:
dev_err(adev->dev,
"Failed to load/validate firmware for %s\n",
fw_name);
To make it clear what was being loaded and validated and failed.
Regards,
Luben
> + release_firmware(adev->psp.toc_fw);
> + adev->psp.toc_fw = NULL;
> + return err;
> +}
> +
> int psp_init_sos_microcode(struct psp_context *psp,
> const char *chip_name)
> {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 919d2fb7427b..13f56618660a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -253,6 +253,11 @@ struct psp_context
> uint32_t asd_ucode_size;
> uint8_t *asd_start_addr;
>
> + /* toc firmware */
> + const struct firmware *toc_fw;
> + uint32_t toc_fw_version;
> + uint32_t toc_feature_version;
> +
> /* fence buffer */
> struct amdgpu_bo *fence_buf_bo;
> uint64_t fence_buf_mc_addr;
> @@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
> int index);
> int psp_init_asd_microcode(struct psp_context *psp,
> const char *chip_name);
> +int psp_init_toc_microcode(struct psp_context *psp,
> + const char *chip_name);
> int psp_init_sos_microcode(struct psp_context *psp,
> const char *chip_name);
> int psp_init_ta_microcode(struct psp_context *psp,
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 6c5d9612abcb..f2d6b2518eee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -109,20 +109,16 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> BUG();
> }
>
> - err = psp_init_sos_microcode(psp, chip_name);
> - if (err)
> - return err;
> -
> - if (adev->asic_type != CHIP_SIENNA_CICHLID &&
> - adev->asic_type != CHIP_NAVY_FLOUNDER) {
> - err = psp_init_asd_microcode(psp, chip_name);
> - if (err)
> - return err;
> - }
>
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> case CHIP_ARCTURUS:
> + err = psp_init_sos_microcode(psp, chip_name);
> + if (err)
> + return err;
> + err = psp_init_asd_microcode(psp, chip_name);
> + if (err)
> + return err;
> snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
> err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
> if (err) {
> @@ -150,6 +146,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> case CHIP_NAVI10:
> case CHIP_NAVI14:
> case CHIP_NAVI12:
> + err = psp_init_sos_microcode(psp, chip_name);
> + if (err)
> + return err;
> + err = psp_init_asd_microcode(psp, chip_name);
> + if (err)
> + return err;
> if (amdgpu_sriov_vf(adev))
> break;
> snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
> @@ -180,10 +182,21 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> break;
> case CHIP_SIENNA_CICHLID:
> case CHIP_NAVY_FLOUNDER:
> + err = psp_init_sos_microcode(psp, chip_name);
> + if (err)
> + return err;
> err = psp_init_ta_microcode(&adev->psp, chip_name);
> if (err)
> return err;
> break;
> + case CHIP_VANGOGH:
> + err = psp_init_asd_microcode(psp, chip_name);
> + if (err)
> + return err;
> + err = psp_init_toc_microcode(psp, chip_name);
> + if (err)
> + return err;
> + break;
> default:
> BUG();
> }
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2)
2020-09-28 22:26 ` Luben Tuikov
@ 2020-09-29 15:09 ` Alex Deucher
2020-09-29 19:02 ` Luben Tuikov
0 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 15:09 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 6:26 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > APU needs load toc firmware for gfx10 series on psp front door loading.
> >
> > v2: rebase against latest code
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 ++++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +++++
> > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ++++++++++++++++-------
> > 4 files changed, 77 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index bd0d14419841..26caa8d43483 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
> > fw_info->ver = adev->dm.dmcub_fw_version;
> > fw_info->feature = 0;
> > break;
> > + case AMDGPU_INFO_FW_TOC:
> > + fw_info->ver = adev->psp.toc_fw_version;
> > + fw_info->feature = adev->psp.toc_feature_version;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > @@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
> > seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
> > fw_info.feature, fw_info.ver);
> >
> > + /* TOC */
> > + query_fw.fw_type = AMDGPU_INFO_FW_TOC;
> > + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
> > + if (ret)
> > + return ret;
> > + seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
> > + fw_info.feature, fw_info.ver);
> >
> > seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > index 18be544d8c1e..c8cec7ab499d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > @@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
> > return err;
> > }
> >
> > +int psp_init_toc_microcode(struct psp_context *psp,
> > + const char *chip_name)
> > +{
> > + struct amdgpu_device *adev = psp->adev;
> > + char fw_name[30];
> > + const struct psp_firmware_header_v1_0 *toc_hdr;
> > + int err = 0;
> > +
> > + if (!chip_name) {
> > + dev_err(adev->dev, "invalid chip name for toc microcode\n");
> > + return -EINVAL;
> > + }
> > +
> > + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
> > + err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
> > + if (err)
> > + goto out;
> > +
> > + err = amdgpu_ucode_validate(adev->psp.toc_fw);
> > + if (err)
> > + goto out;
> > +
> > + toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
> > + adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
> > + adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
> > + adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
> > + adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
> > + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
> > + return 0;
> > +out:
>
> I'd rather this label be "Err:".
>
> Regardless of whether there already is a variable "err",
> (there is!), capitalizing goto labels is good practice, since
> it distinguishes them from variables (which are all lowercase),
> and macros (which are all caps). Plus, you also avoid conflict
> with the eponymous variable.
>
I see your point, but I find random caps in code hard to read.
> > + dev_err(adev->dev, "fail to initialize toc microcode\n");
>
> That's a very misleading message. Please print this instead:
>
> dev_err(adev->dev,
> "Failed to load/validate firmware for %s\n",
> fw_name);
>
> To make it clear what was being loaded and validated and failed.
>
Updated.
Thanks,
Alex
> Regards,
> Luben
>
> > + release_firmware(adev->psp.toc_fw);
> > + adev->psp.toc_fw = NULL;
> > + return err;
> > +}
> > +
> > int psp_init_sos_microcode(struct psp_context *psp,
> > const char *chip_name)
> > {
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> > index 919d2fb7427b..13f56618660a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> > @@ -253,6 +253,11 @@ struct psp_context
> > uint32_t asd_ucode_size;
> > uint8_t *asd_start_addr;
> >
> > + /* toc firmware */
> > + const struct firmware *toc_fw;
> > + uint32_t toc_fw_version;
> > + uint32_t toc_feature_version;
> > +
> > /* fence buffer */
> > struct amdgpu_bo *fence_buf_bo;
> > uint64_t fence_buf_mc_addr;
> > @@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
> > int index);
> > int psp_init_asd_microcode(struct psp_context *psp,
> > const char *chip_name);
> > +int psp_init_toc_microcode(struct psp_context *psp,
> > + const char *chip_name);
> > int psp_init_sos_microcode(struct psp_context *psp,
> > const char *chip_name);
> > int psp_init_ta_microcode(struct psp_context *psp,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > index 6c5d9612abcb..f2d6b2518eee 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > @@ -109,20 +109,16 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> > BUG();
> > }
> >
> > - err = psp_init_sos_microcode(psp, chip_name);
> > - if (err)
> > - return err;
> > -
> > - if (adev->asic_type != CHIP_SIENNA_CICHLID &&
> > - adev->asic_type != CHIP_NAVY_FLOUNDER) {
> > - err = psp_init_asd_microcode(psp, chip_name);
> > - if (err)
> > - return err;
> > - }
> >
> > switch (adev->asic_type) {
> > case CHIP_VEGA20:
> > case CHIP_ARCTURUS:
> > + err = psp_init_sos_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > + err = psp_init_asd_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
> > err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
> > if (err) {
> > @@ -150,6 +146,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> > case CHIP_NAVI10:
> > case CHIP_NAVI14:
> > case CHIP_NAVI12:
> > + err = psp_init_sos_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > + err = psp_init_asd_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > if (amdgpu_sriov_vf(adev))
> > break;
> > snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
> > @@ -180,10 +182,21 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> > break;
> > case CHIP_SIENNA_CICHLID:
> > case CHIP_NAVY_FLOUNDER:
> > + err = psp_init_sos_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > err = psp_init_ta_microcode(&adev->psp, chip_name);
> > if (err)
> > return err;
> > break;
> > + case CHIP_VANGOGH:
> > + err = psp_init_asd_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > + err = psp_init_toc_microcode(psp, chip_name);
> > + if (err)
> > + return err;
> > + break;
> > default:
> > BUG();
> > }
> >
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2)
2020-09-29 15:09 ` Alex Deucher
@ 2020-09-29 19:02 ` Luben Tuikov
2020-09-30 1:15 ` gfx timeout and GPU reset while hundreds apps run on AMD GPU wales wang
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-29 19:02 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On 2020-09-29 11:09 a.m., Alex Deucher wrote:
> On Mon, Sep 28, 2020 at 6:26 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>>
>> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
>>> From: Huang Rui <ray.huang@amd.com>
>>>
>>> APU needs load toc firmware for gfx10 series on psp front door loading.
>>>
>>> v2: rebase against latest code
>>>
>>> Signed-off-by: Huang Rui <ray.huang@amd.com>
>>> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 ++++++++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +++++
>>> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ++++++++++++++++-------
>>> 4 files changed, 77 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index bd0d14419841..26caa8d43483 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
>>> fw_info->ver = adev->dm.dmcub_fw_version;
>>> fw_info->feature = 0;
>>> break;
>>> + case AMDGPU_INFO_FW_TOC:
>>> + fw_info->ver = adev->psp.toc_fw_version;
>>> + fw_info->feature = adev->psp.toc_feature_version;
>>> + break;
>>> default:
>>> return -EINVAL;
>>> }
>>> @@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
>>> seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
>>> fw_info.feature, fw_info.ver);
>>>
>>> + /* TOC */
>>> + query_fw.fw_type = AMDGPU_INFO_FW_TOC;
>>> + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
>>> + if (ret)
>>> + return ret;
>>> + seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
>>> + fw_info.feature, fw_info.ver);
>>>
>>> seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> index 18be544d8c1e..c8cec7ab499d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> @@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
>>> return err;
>>> }
>>>
>>> +int psp_init_toc_microcode(struct psp_context *psp,
>>> + const char *chip_name)
>>> +{
>>> + struct amdgpu_device *adev = psp->adev;
>>> + char fw_name[30];
>>> + const struct psp_firmware_header_v1_0 *toc_hdr;
>>> + int err = 0;
>>> +
>>> + if (!chip_name) {
>>> + dev_err(adev->dev, "invalid chip name for toc microcode\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
>>> + err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
>>> + if (err)
>>> + goto out;
>>> +
>>> + err = amdgpu_ucode_validate(adev->psp.toc_fw);
>>> + if (err)
>>> + goto out;
>>> +
>>> + toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
>>> + adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
>>> + adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
>>> + adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
>>> + adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
>>> + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
>>> + return 0;
>>> +out:
>>
>> I'd rather this label be "Err:".
>>
>> Regardless of whether there already is a variable "err",
>> (there is!), capitalizing goto labels is good practice, since
>> it distinguishes them from variables (which are all lowercase),
>> and macros (which are all caps). Plus, you also avoid conflict
>> with the eponymous variable.
>>
>
> I see your point, but I find random caps in code hard to read.
They wouldn't be random. They're only the names of goto labels,
kind of like when chapters of books or sections of papers are
capitalized. I think it would be good and visually distinctive.
FWIW, I've picked this capitalization of goto labels only,
*from the Linux kernel.* I liked it and I think it makes sense.
I certainly didn't come up with it myself.
Regards,
Luben
>
>>> + dev_err(adev->dev, "fail to initialize toc microcode\n");
>>
>> That's a very misleading message. Please print this instead:
>>
>> dev_err(adev->dev,
>> "Failed to load/validate firmware for %s\n",
>> fw_name);
>>
>> To make it clear what was being loaded and validated and failed.
>>
>
> Updated.
>
> Thanks,
>
> Alex
>
>> Regards,
>> Luben
>>
>>> + release_firmware(adev->psp.toc_fw);
>>> + adev->psp.toc_fw = NULL;
>>> + return err;
>>> +}
>>> +
>>> int psp_init_sos_microcode(struct psp_context *psp,
>>> const char *chip_name)
>>> {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>>> index 919d2fb7427b..13f56618660a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>>> @@ -253,6 +253,11 @@ struct psp_context
>>> uint32_t asd_ucode_size;
>>> uint8_t *asd_start_addr;
>>>
>>> + /* toc firmware */
>>> + const struct firmware *toc_fw;
>>> + uint32_t toc_fw_version;
>>> + uint32_t toc_feature_version;
>>> +
>>> /* fence buffer */
>>> struct amdgpu_bo *fence_buf_bo;
>>> uint64_t fence_buf_mc_addr;
>>> @@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
>>> int index);
>>> int psp_init_asd_microcode(struct psp_context *psp,
>>> const char *chip_name);
>>> +int psp_init_toc_microcode(struct psp_context *psp,
>>> + const char *chip_name);
>>> int psp_init_sos_microcode(struct psp_context *psp,
>>> const char *chip_name);
>>> int psp_init_ta_microcode(struct psp_context *psp,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> index 6c5d9612abcb..f2d6b2518eee 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> @@ -109,20 +109,16 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>>> BUG();
>>> }
>>>
>>> - err = psp_init_sos_microcode(psp, chip_name);
>>> - if (err)
>>> - return err;
>>> -
>>> - if (adev->asic_type != CHIP_SIENNA_CICHLID &&
>>> - adev->asic_type != CHIP_NAVY_FLOUNDER) {
>>> - err = psp_init_asd_microcode(psp, chip_name);
>>> - if (err)
>>> - return err;
>>> - }
>>>
>>> switch (adev->asic_type) {
>>> case CHIP_VEGA20:
>>> case CHIP_ARCTURUS:
>>> + err = psp_init_sos_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> + err = psp_init_asd_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
>>> err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
>>> if (err) {
>>> @@ -150,6 +146,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>>> case CHIP_NAVI10:
>>> case CHIP_NAVI14:
>>> case CHIP_NAVI12:
>>> + err = psp_init_sos_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> + err = psp_init_asd_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> if (amdgpu_sriov_vf(adev))
>>> break;
>>> snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
>>> @@ -180,10 +182,21 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>>> break;
>>> case CHIP_SIENNA_CICHLID:
>>> case CHIP_NAVY_FLOUNDER:
>>> + err = psp_init_sos_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> err = psp_init_ta_microcode(&adev->psp, chip_name);
>>> if (err)
>>> return err;
>>> break;
>>> + case CHIP_VANGOGH:
>>> + err = psp_init_asd_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> + err = psp_init_toc_microcode(psp, chip_name);
>>> + if (err)
>>> + return err;
>>> + break;
>>> default:
>>> BUG();
>>> }
>>>
>>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* gfx timeout and GPU reset while hundreds apps run on AMD GPU
2020-09-29 19:02 ` Luben Tuikov
@ 2020-09-30 1:15 ` wales wang
0 siblings, 0 replies; 64+ messages in thread
From: wales wang @ 2020-09-30 1:15 UTC (permalink / raw)
To: amd-gfx
gfx timeout and GPU reset while hundreds apps run on AMD GPU, the error happen about weekly.
Env:
Linux version 5.3.15-050315.2020063001-generic (root@k8snode) (gcc version 7.5.0 (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04)) #appstream SMP PREEMPT Sat Jul 4 10:28:24 CST 2020
vainfo: VA-API version: 1.5 (libva 2.5.0)
vainfo: Driver version: Mesa Gallium driver 19.0.5 for AMD Radeon (TM) RX 480 Graphics (POLARIS10, DRM 3.33.0, 5.3.15-050315.2020063001-generic, LLVM 7.0.0)
vainfo: Supported profile and entrypoints
ii libdrm-dev 2.4.97-1ubuntu1~18.04.1 Userspace interface to kernel DRM services -- development files
log:
Sep 29 17:42:25 k8snode244 kernel: [952607.136002] amdgpu 0005:01:00.0: GPU fault detected: 146 0x0000480c for process Media42797 pid 637190 thread appstream:cs0 pid 637206
Sep 29 17:42:25 k8snode244 kernel: [952607.136007] amdgpu 0005:01:00.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x00000000
Sep 29 17:42:25 k8snode244 kernel: [952607.136009] amdgpu 0005:01:00.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0E04800C
Sep 29 17:42:25 k8snode244 kernel: [952607.136013] amdgpu 0005:01:00.0: VM fault (0x0c, vmid 7, pasid 32774) at page 0, read from 'TC4' (0x54433400) (72)
Sep 29 17:42:35 k8snode244 kernel: [952617.235478] [drm:amdgpu_job_timedout [amdgpu]]*ERROR* ring gfx timeout, signaled seq=313011137, emitted seq=313011140
Sep 29 17:42:35 k8snode244 kernel: [952617.235560] [drm:amdgpu_job_timedout [amdgpu]]*ERROR* Process information: process Media42797 pid 637190 thread appstream:cs0 pid 637206
Sep 29 17:42:35 k8snode244 kernel: [952617.235578] amdgpu 0005:01:00.0: GPU reset begin!
Sep 29 17:42:35 k8snode244 kernel: [952617.236276] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]]*ERROR* suspend of IP block <vce_v3_0> failed -22
Sep 29 17:42:36 k8snode244 kernel: [952617.842417] amdgpu 0005:01:00.0: [drm:amdgpu_ring_test_helper [amdgpu]]*ERROR* ring kiq_2.1.0 test failed (-110)
Sep 29 17:42:36 k8snode244 kernel: [952617.842500] [drm:gfx_v8_0_hw_fini [amdgpu]]*ERROR* KCQ disable failed
Sep 29 17:42:36 k8snode244 kernel: [952618.098569] cp is busy, skip halt cp
Sep 29 17:42:36 k8snode244 kernel: [952618.356730] rlc is busy, skip halt rlc
Sep 29 17:42:36 k8snode244 kernel: [952618.357783] amdgpu 0005:01:00.0: GPU pci config reset
Sep 29 17:42:36 k8snode244 kernel: [952618.476296] amdgpu 0005:01:00.0: GPU reset succeeded, trying to resume
Sep 29 17:42:36 k8snode244 kernel: [952618.478750] [drm] PCIE GART of 256M enabled (table at 0x000000F400000000).
Sep 29 17:42:36 k8snode244 kernel: [952618.478770] [drm] VRAM is lost due to GPU reset!
Sep 29 17:42:37 k8snode244 kernel: [952618.610145] [drm] UVD and UVD ENC initialized successfully.
Sep 29 17:42:37 k8snode244 kernel: [952618.765301] [drm] VCE initialized successfully.
Sep 29 17:42:37 k8snode244 kernel: [952618.785034] [drm] recover vram bo from shadow start
Sep 29 17:42:37 k8snode244 kernel: [952618.849311] [drm] recover vram bo from shadow done
Sep 29 17:42:37 k8snode244 kernel: [952618.849319] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.849321] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.849386] WARNING: CPU: 14 PID: 681455 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849387] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.849440] CPU: 14 PID: 681455 Comm: kworker/14:0 Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.849442] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.849450] Workqueue: events drm_sched_job_timedout [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849454] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.849458] pc : drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849461] lr : drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849462] sp : ffff00009c873c20
Sep 29 17:42:37 k8snode244 kernel: [952618.849464] x29: ffff00009c873c20 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849466] x27: ffff808e72af2300 x26: 00000000ffffff83
Sep 29 17:42:37 k8snode244 kernel: [952618.849469] x25: ffff0000094c66b8 x24: 00000000001fb320
Sep 29 17:42:37 k8snode244 kernel: [952618.849471] x23: 0000000000000001 x22: ffff801fd37a6bb8
Sep 29 17:42:37 k8snode244 kernel: [952618.849473] x21: ffff801fd37a6a30 x20: ffff80188be5ec00
Sep 29 17:42:37 k8snode244 kernel: [952618.849476] x19: ffff801f7dcc9400 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849478] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.849480] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.849481] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.849484] x11: 0000000000078918 x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849486] x9 : 0000000000000001 x8 : 000000000001a8ff
Sep 29 17:42:37 k8snode244 kernel: [952618.849488] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.849490] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.849492] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.849494] x1 : 0000000000000000 x0 : 0000000000000024
Sep 29 17:42:37 k8snode244 kernel: [952618.849496] Call trace:
Sep 29 17:42:37 k8snode244 kernel: [952618.849500] drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849591] amdgpu_device_gpu_recover+0x460/0xb58 [amdgpu]
Sep 29 17:42:37 k8snode244 kernel: [952618.849671] amdgpu_job_timedout+0xe4/0x108 [amdgpu]
Sep 29 17:42:37 k8snode244 kernel: [952618.849676] drm_sched_job_timedout+0x84/0xf8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849682] process_one_work+0x1ec/0x470
Sep 29 17:42:37 k8snode244 kernel: [952618.849684] worker_thread+0x48/0x458
Sep 29 17:42:37 k8snode244 kernel: [952618.849687] kthread+0x110/0x118
Sep 29 17:42:37 k8snode244 kernel: [952618.849691] ret_from_fork+0x10/0x18
Sep 29 17:42:37 k8snode244 kernel: [952618.849692] ---[ end trace 5b779f1dd4a6e6cf ]---
Sep 29 17:42:37 k8snode244 kernel: [952618.849697] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.849698] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.849723] WARNING: CPU: 14 PID: 681455 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849724] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.849759] CPU: 14 PID: 681455 Comm: kworker/14:0 Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.849760] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.849767] Workqueue: events drm_sched_job_timedout [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849770] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.849774] pc : drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849777] lr : drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849778] sp : ffff00009c873c20
Sep 29 17:42:37 k8snode244 kernel: [952618.849779] x29: ffff00009c873c20 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849782] x27: ffff80901dc28000 x26: 00000000ffffff83
Sep 29 17:42:37 k8snode244 kernel: [952618.849784] x25: ffff0000094c66b8 x24: 00000000001fb320
Sep 29 17:42:37 k8snode244 kernel: [952618.849786] x23: 0000000000000001 x22: ffff801fd37a6bb8
Sep 29 17:42:37 k8snode244 kernel: [952618.849788] x21: ffff801fd37a6a30 x20: ffff801fd37a6b88
Sep 29 17:42:37 k8snode244 kernel: [952618.849790] x19: ffff80188be5ec00 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849792] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.849794] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.849796] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.849798] x11: 00000000000794fc x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.849800] x9 : 0000000000000001 x8 : 000000000001a923
Sep 29 17:42:37 k8snode244 kernel: [952618.849802] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.849804] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.849806] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.849808] x1 : 0000000000000000 x0 : 0000000000000024
Sep 29 17:42:37 k8snode244 kernel: [952618.849810] Call trace:
Sep 29 17:42:37 k8snode244 kernel: [952618.849813] drm_sched_resubmit_jobs+0x188/0x1a8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849894] amdgpu_device_gpu_recover+0x460/0xb58 [amdgpu]
Sep 29 17:42:37 k8snode244 kernel: [952618.849973] amdgpu_job_timedout+0xe4/0x108 [amdgpu]
Sep 29 17:42:37 k8snode244 kernel: [952618.849977] drm_sched_job_timedout+0x84/0xf8 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.849980] process_one_work+0x1ec/0x470
Sep 29 17:42:37 k8snode244 kernel: [952618.849982] worker_thread+0x48/0x458
Sep 29 17:42:37 k8snode244 kernel: [952618.849984] kthread+0x110/0x118
Sep 29 17:42:37 k8snode244 kernel: [952618.849986] ret_from_fork+0x10/0x18
Sep 29 17:42:37 k8snode244 kernel: [952618.849988] ---[ end trace 5b779f1dd4a6e6d0 ]---
Sep 29 17:42:37 k8snode244 kernel: [952618.850034] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.850036] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.850061] WARNING: CPU: 14 PID: 903 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850063] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.850098] CPU: 14 PID: 903 Comm: gfx Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.850099] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.850101] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.850104] pc : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850107] lr : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850108] sp : ffff00001c883dd0
Sep 29 17:42:37 k8snode244 kernel: [952618.850109] x29: ffff00001c883dd0 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850111] x27: 0000000000000000 x26: ffff801fd37a6bc8
Sep 29 17:42:37 k8snode244 kernel: [952618.850113] x25: ffff000011b79000 x24: ffff8019e70e0858
Sep 29 17:42:37 k8snode244 kernel: [952618.850115] x23: ffff801fd37a6b18 x22: ffff801f14a45000
Sep 29 17:42:37 k8snode244 kernel: [952618.850116] x21: 0000000000000000 x20: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850118] x19: ffff801fd37a6a30 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850120] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.850122] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.850123] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.850125] x11: 000000000007a0e4 x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850127] x9 : 0000000000000001 x8 : 000000000001a947
Sep 29 17:42:37 k8snode244 kernel: [952618.850129] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.850131] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.850133] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.850135] x1 : 0000000000000000 x0 : 0000000000000024
Sep 29 17:42:37 k8snode244 kernel: [952618.850138] Call trace:
Sep 29 17:42:37 k8snode244 kernel: [952618.850142] drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850144] kthread+0x110/0x118
Sep 29 17:42:37 k8snode244 kernel: [952618.850146] ret_from_fork+0x10/0x18
Sep 29 17:42:37 k8snode244 kernel: [952618.850149] ---[ end trace 5b779f1dd4a6e6d1 ]---
Sep 29 17:42:37 k8snode244 kernel: [952618.850168] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.850170] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.850190] WARNING: CPU: 14 PID: 903 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850191] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.850224] CPU: 14 PID: 903 Comm: gfx Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.850226] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.850228] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.850231] pc : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850234] lr : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850235] sp : ffff00001c883dd0
Sep 29 17:42:37 k8snode244 kernel: [952618.850237] x29: ffff00001c883dd0 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850239] x27: 0000000000000000 x26: ffff801fd37a6bc8
Sep 29 17:42:37 k8snode244 kernel: [952618.850241] x25: ffff000011b79000 x24: ffff8017d1ae2c58
Sep 29 17:42:37 k8snode244 kernel: [952618.850243] x23: ffff801fd37a6b18 x22: ffff8011c9bcea00
Sep 29 17:42:37 k8snode244 kernel: [952618.850245] x21: 0000000000000000 x20: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850247] x19: ffff801fd37a6a30 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850248] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.850250] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.850252] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.850253] x11: 000000000007ab84 x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850255] x9 : 0000000000000001 x8 : 000000000001a965
Sep 29 17:42:37 k8snode244 kernel: [952618.850257] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.850259] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.850261] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.850263] x1 : 0000000000000000 x0 : 0000000000000024
Sep 29 17:42:37 k8snode244 kernel: [952618.850265] Call trace:
Sep 29 17:42:37 k8snode244 kernel: [952618.850269] drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850271] kthread+0x110/0x118
Sep 29 17:42:37 k8snode244 kernel: [952618.850274] ret_from_fork+0x10/0x18
Sep 29 17:42:37 k8snode244 kernel: [952618.850275] ---[ end trace 5b779f1dd4a6e6d2 ]---
Sep 29 17:42:37 k8snode244 kernel: [952618.850298] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.850299] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.850320] WARNING: CPU: 14 PID: 903 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850321] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.850355] CPU: 14 PID: 903 Comm: gfx Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.850356] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.850358] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.850361] pc : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850364] lr : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850366] sp : ffff00001c883dd0
Sep 29 17:42:37 k8snode244 kernel: [952618.850367] x29: ffff00001c883dd0 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850369] x27: 0000000000000000 x26: ffff801fd37a6bc8
Sep 29 17:42:37 k8snode244 kernel: [952618.850371] x25: ffff000011b79000 x24: ffff80196cad9c58
Sep 29 17:42:37 k8snode244 kernel: [952618.850373] x23: ffff801fd37a6b18 x22: ffff8017cb683900
Sep 29 17:42:37 k8snode244 kernel: [952618.850375] x21: 0000000000000000 x20: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850377] x19: ffff801fd37a6a30 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850379] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.850380] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.850382] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.850384] x11: 000000000007b5d0 x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850386] x9 : 0000000000000001 x8 : 000000000001a983
Sep 29 17:42:37 k8snode244 kernel: [952618.850388] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.850390] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.850392] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.850395] x1 : 0000000000000000 x0 : 0000000000000024
Sep 29 17:42:37 k8snode244 kernel: [952618.850397] Call trace:
Sep 29 17:42:37 k8snode244 kernel: [952618.850400] drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850403] kthread+0x110/0x118
Sep 29 17:42:37 k8snode244 kernel: [952618.850405] ret_from_fork+0x10/0x18
Sep 29 17:42:37 k8snode244 kernel: [952618.850406] ---[ end trace 5b779f1dd4a6e6d3 ]---
Sep 29 17:42:37 k8snode244 kernel: [952618.850461] [drm] Skip scheduling IBs!
Sep 29 17:42:37 k8snode244 kernel: [952618.850463] ------------[ cut here ]------------
Sep 29 17:42:37 k8snode244 kernel: [952618.850483] WARNING: CPU: 14 PID: 903 at /home/lwj/build/kernel/include/linux/dma-fence.h:513 drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850484] Modules linked in: sch_tbf veth xt_recent br_netfilter bridge stp llc xt_addrtype bpfilter ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs overlay nls_iso8859_1 ipmi_ssif snd_hda_intel snd_hda_codec joydev snd_hda_core input_leds snd_hwdep snd_pcm snd_timer snd ipmi_si soundcore ipmi_devintf ipmi_msghandler tcp_bbr sch_fq binder_dkms(OE) autofs4 btrfs zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor xor_neon raid6_pq raid1 raid0 multipath linear ses enclosure hibmc_drm hid_generic usbhid hid marvell aes_ce_blk aes_ce_cipher amdgpu i2c_algo_bit crct10dif_ce gpu_sched drm_vram_helper ttm ghash_ce sha2_ce drm_kms_helper syscopyarea sha256_arm64 sysfillrect sysimgblt fb_sys_fops sha1_ce drm hisi_sas_v2_hw hisi_sas_main libsas ehci_platform scsi_transport_sas hns_dsaf hns_enet_drv hns_mdio hnae aes_neon_bs aes_neon_blk crypto_simd cryptd aes_arm64
Sep 29 17:42:37 k8snode244 kernel: [952618.850519] CPU: 14 PID: 903 Comm: gfx Kdump: loaded Tainted: G W OE 5.3.15-050315.2020063001-generic #appstream
Sep 29 17:42:37 k8snode244 kernel: [952618.850520] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.63 09/19/2019
Sep 29 17:42:37 k8snode244 kernel: [952618.850522] pstate: 40400005 (nZcv daif +PAN -UAO)
Sep 29 17:42:37 k8snode244 kernel: [952618.850525] pc : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850528] lr : drm_sched_main+0x2d4/0x2e0 [gpu_sched]
Sep 29 17:42:37 k8snode244 kernel: [952618.850529] sp : ffff00001c883dd0
Sep 29 17:42:37 k8snode244 kernel: [952618.850530] x29: ffff00001c883dd0 x28: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850531] x27: 0000000000000000 x26: ffff801fd37a6bc8
Sep 29 17:42:37 k8snode244 kernel: [952618.850533] x25: ffff000011b79000 x24: ffff808ca5534458
Sep 29 17:42:37 k8snode244 kernel: [952618.850535] x23: ffff801fd37a6b18 x22: ffff80161a411200
Sep 29 17:42:37 k8snode244 kernel: [952618.850536] x21: 0000000000000000 x20: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850538] x19: ffff801fd37a6a30 x18: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850540] x17: 0000000000000001 x16: 0000000000000007
Sep 29 17:42:37 k8snode244 kernel: [952618.850541] x15: 0000000000000000 x14: 0000000000002400
Sep 29 17:42:37 k8snode244 kernel: [952618.850543] x13: 0000000000000000 x12: ffff000011ba7000
Sep 29 17:42:37 k8snode244 kernel: [952618.850546] x11: 000000000007c018 x10: 0000000000000000
Sep 29 17:42:37 k8snode244 kernel: [952618.850548] x9 : 0000000000000001 x8 : 000000000001a9a1
Sep 29 17:42:37 k8snode244 kernel: [952618.850550] x7 : ffff000011ba7000 x6 : 00002b369e3d3bcd
Sep 29 17:42:37 k8snode244 kernel: [952618.850552] x5 : 0000000000000001 x4 : ffff8017dbbc2248
Sep 29 17:42:37 k8snode244 kernel: [952618.850553] x3 : ffff8017dbbc2248 x2 : b5be5ef7ef51a000
Sep 29 17:42:37 k8snode244 kernel: [952618.850555] x1 : 0000000000000000 x0 : 0000000000000024
+++++++++++keylog++++++++++++++++++
Sep 29 17:42:35 k8snode244 kernel: [952617.235578] amdgpu 0005:01:00.0: GPU reset begin!
Sep 29 17:42:35 k8snode244 kernel: [952617.236276] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]]*ERROR* suspend of IP block <vce_v3_0> failed -22
Sep 29 17:42:36 k8snode244 kernel: [952617.842417] amdgpu 0005:01:00.0: [drm:amdgpu_ring_test_helper [amdgpu]]*ERROR* ring kiq_2.1.0 test failed (-110)
Sep 29 17:42:36 k8snode244 kernel: [952617.842500] [drm:gfx_v8_0_hw_fini [amdgpu]]*ERROR* KCQ disable failed
Sep 29 17:42:36 k8snode244 kernel: [952618.098569] cp is busy, skip halt cp
Sep 29 17:42:36 k8snode244 kernel: [952618.356730] rlc is busy, skip halt rlc
Sep 29 17:42:36 k8snode244 kernel: [952618.357783] amdgpu 0005:01:00.0: GPU pci config reset
Sep 29 17:42:36 k8snode244 kernel: [952618.476296] amdgpu 0005:01:00.0: GPU reset succeeded, trying to resume
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 37/45] drm/amdgpu: enable psp support for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (34 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2) Alex Deucher
` (7 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to enable psp support for vangogh
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 5 +++++
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c8cec7ab499d..574392fcd503 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -100,6 +100,7 @@ static int psp_early_init(void *handle)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 3f791ca73ff7..676405171a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -391,12 +391,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
- case CHIP_VANGOGH:
- return AMDGPU_FW_LOAD_DIRECT;
default:
DRM_ERROR("Unknown firmware load type\n");
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4fbf3f6640e6..568e33b7fda8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -644,6 +644,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index f2d6b2518eee..d6ba6ea9a8fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -59,6 +59,8 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
@@ -105,6 +107,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2)
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (35 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 37/45] drm/amdgpu: enable psp support for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG Alex Deucher
` (6 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Huang Rui <ray.huang@amd.com>
GFXOFF will be enabled once it's verified on real asic.
v2: move check into gfx10 module.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 83183541865f..fd29a6d7285b 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3666,6 +3666,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
+ case CHIP_VANGOGH:
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ break;
default:
break;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (36 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2) Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub Alex Deucher
` (5 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Fallback to legacy path for now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 568e33b7fda8..4bd2e2f35fa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -484,6 +484,10 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
{
int r;
+ /* IP discovery table is not available yet */
+ if (adev->asic_type == CHIP_VANGOGH)
+ goto legacy_init;
+
if (amdgpu_discovery) {
r = amdgpu_discovery_reg_base_init(adev);
if (r) {
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (37 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10 Alex Deucher
` (4 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Print the name of the client rather than the number. This
makes it easier to debug what block is causing the fault.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 49 ++++++++++++++++++++++---
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index b39dc2023b5f..3a248c8cd0b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -31,6 +31,30 @@
#include "soc15_common.h"
+static const char *mmhub_client_ids_vangogh[][2] = {
+ [0][0] = "MP0",
+ [1][0] = "MP1",
+ [2][0] = "DCEDMC",
+ [3][0] = "DCEVGA",
+ [13][0] = "UTCL2",
+ [26][0] = "OSS",
+ [27][0] = "HDP",
+ [28][0] = "VCN",
+ [29][0] = "VCNU",
+ [30][0] = "JPEG",
+ [0][1] = "MP0",
+ [1][1] = "MP1",
+ [2][1] = "DCEDMC",
+ [3][1] = "DCEVGA",
+ [4][1] = "DCEDWB",
+ [5][1] = "XDP",
+ [26][1] = "OSS",
+ [27][1] = "HDP",
+ [28][1] = "VCN",
+ [29][1] = "VCNU",
+ [30][1] = "JPEG",
+};
+
static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
uint32_t flush_type)
{
@@ -55,12 +79,27 @@ static void
mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
uint32_t status)
{
+ uint32_t cid, rw;
+ const char *mmhub_cid = NULL;
+
+ cid = REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, CID);
+ rw = REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, RW);
+
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
- REG_GET_FIELD(status,
- MMVM_L2_PROTECTION_FAULT_STATUS, CID));
+ switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
+ break;
+ default:
+ mmhub_cid = NULL;
+ break;
+ }
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+ mmhub_cid ? mmhub_cid : "unknown", cid);
dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
REG_GET_FIELD(status,
MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
@@ -73,9 +112,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
REG_GET_FIELD(status,
MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
- dev_err(adev->dev, "\t RW: 0x%lx\n",
- REG_GET_FIELD(status,
- MMVM_L2_PROTECTION_FAULT_STATUS, RW));
+ dev_err(adev->dev, "\t RW: 0x%x\n", rw);
}
static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (38 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-28 22:48 ` Luben Tuikov
2020-09-25 20:10 ` [PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh Alex Deucher
` (3 subsequent siblings)
43 siblings, 1 reply; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to add power gating handle for gfx10.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fd29a6d7285b..f2849f180c91 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7583,6 +7583,30 @@ static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offse
return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
}
+static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
+{
+ int data;
+
+ if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ } else {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ }
+}
+
+static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
+{
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+ gfx_v10_cntl_power_gating(adev, enable);
+
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+}
+
static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
.set_safe_mode = gfx_v10_0_set_safe_mode,
@@ -7630,6 +7654,9 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case CHIP_NAVY_FLOUNDER:
amdgpu_gfx_off_ctrl(adev, enable);
break;
+ case CHIP_VANGOGH:
+ gfx_v10_cntl_pg(adev, enable);
+ break;
default:
break;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10
2020-09-25 20:10 ` [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10 Alex Deucher
@ 2020-09-28 22:48 ` Luben Tuikov
2020-09-29 15:13 ` Alex Deucher
0 siblings, 1 reply; 64+ messages in thread
From: Luben Tuikov @ 2020-09-28 22:48 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> This patch is to add power gating handle for gfx10.
Ray, you can just say:
"This patch adds power gating handler for gfx10."
You can drop "is to" and just use "adds".
And similarly for all other patches where you use that.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fd29a6d7285b..f2849f180c91 100755
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7583,6 +7583,30 @@ static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offse
> return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
> }
>
> +static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> +{
> + int data;
> +
> + if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> + data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
> + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> + WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> + } else {
> + data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
> + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> + WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> + }
> +}
So here, you can just do:
static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
{
data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG))
data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
else
data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
}
Regards,
Luben
> +
> +static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
> +{
> + amdgpu_gfx_rlc_enter_safe_mode(adev);
> +
> + gfx_v10_cntl_power_gating(adev, enable);
> +
> + amdgpu_gfx_rlc_exit_safe_mode(adev);
> +}
> +
> static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
> .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
> .set_safe_mode = gfx_v10_0_set_safe_mode,
> @@ -7630,6 +7654,9 @@ static int gfx_v10_0_set_powergating_state(void *handle,
> case CHIP_NAVY_FLOUNDER:
> amdgpu_gfx_off_ctrl(adev, enable);
> break;
> + case CHIP_VANGOGH:
> + gfx_v10_cntl_pg(adev, enable);
> + break;
> default:
> break;
> }
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10
2020-09-28 22:48 ` Luben Tuikov
@ 2020-09-29 15:13 ` Alex Deucher
0 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-29 15:13 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 6:48 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > This patch is to add power gating handle for gfx10.
>
> Ray, you can just say:
>
> "This patch adds power gating handler for gfx10."
>
> You can drop "is to" and just use "adds".
> And similarly for all other patches where you use that.
>
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index fd29a6d7285b..f2849f180c91 100755
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -7583,6 +7583,30 @@ static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offse
> > return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
> > }
> >
> > +static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> > +{
> > + int data;
> > +
> > + if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> > + data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
> > + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> > + WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> > + } else {
> > + data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
> > + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> > + WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> > + }
> > +}
>
> So here, you can just do:
>
> static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> {
> data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
> if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG))
> data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> else
> data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> }
>
Updated. Thanks!
Alex
> Regards,
> Luben
>
> > +
> > +static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
> > +{
> > + amdgpu_gfx_rlc_enter_safe_mode(adev);
> > +
> > + gfx_v10_cntl_power_gating(adev, enable);
> > +
> > + amdgpu_gfx_rlc_exit_safe_mode(adev);
> > +}
> > +
> > static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
> > .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
> > .set_safe_mode = gfx_v10_0_set_safe_mode,
> > @@ -7630,6 +7654,9 @@ static int gfx_v10_0_set_powergating_state(void *handle,
> > case CHIP_NAVY_FLOUNDER:
> > amdgpu_gfx_off_ctrl(adev, enable);
> > break;
> > + case CHIP_VANGOGH:
> > + gfx_v10_cntl_pg(adev, enable);
> > + break;
> > default:
> > break;
> > }
> >
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (39 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10 Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 43/45] drm/amd/display: Add dcn3.01 support to DC Alex Deucher
` (2 subsequent siblings)
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch is to enable the gfx cg and pg for vangogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4bd2e2f35fa4..67b6067f2bd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -919,8 +919,11 @@ static int nv_common_early_init(void *handle)
break;
case CHIP_VANGOGH:
- adev->cg_flags = 0;
- adev->pg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS;
+ adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
adev->external_rev_id = adev->rev_id + 0x01;
break;
default:
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 43/45] drm/amd/display: Add dcn3.01 support to DC
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (40 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM Alex Deucher
2020-09-25 20:10 ` [PATCH 45/45] drm/amdgpu: add van gogh pci id Alex Deucher
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Roman Li
From: Roman Li <Roman.Li@amd.com>
Update dc for vangogh support.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/Kconfig | 9 +
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
.../drm/amd/display/dc/bios/bios_parser2.c | 187 ++
.../display/dc/bios/command_table_helper2.c | 6 +-
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 21 +-
.../display/dc/clk_mgr/dcn301/dcn301_smu.c | 241 ++
.../display/dc/clk_mgr/dcn301/dcn301_smu.h | 164 ++
.../display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 834 +++++++
.../display/dc/clk_mgr/dcn301/vg_clk_mgr.h | 43 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 18 +-
.../drm/amd/display/dc/dce/dce_clock_source.c | 18 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 29 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 191 +-
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 18 +
.../drm/amd/display/dc/dcn30/dcn30_hubbub.c | 11 +
.../drm/amd/display/dc/dcn30/dcn30_hubbub.h | 3 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 5 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 5 +
.../gpu/drm/amd/display/dc/dcn301/Makefile | 47 +
.../drm/amd/display/dc/dcn301/dcn301_dccg.c | 75 +
.../drm/amd/display/dc/dcn301/dcn301_dccg.h | 65 +
.../dc/dcn301/dcn301_dio_link_encoder.c | 192 ++
.../dc/dcn301/dcn301_dio_link_encoder.h | 82 +
.../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 81 +
.../drm/amd/display/dc/dcn301/dcn301_hubbub.h | 60 +
.../drm/amd/display/dc/dcn301/dcn301_hwseq.c | 42 +
.../drm/amd/display/dc/dcn301/dcn301_hwseq.h | 32 +
.../drm/amd/display/dc/dcn301/dcn301_init.c | 145 ++
.../drm/amd/display/dc/dcn301/dcn301_init.h | 33 +
.../amd/display/dc/dcn301/dcn301_panel_cntl.c | 218 ++
.../amd/display/dc/dcn301/dcn301_panel_cntl.h | 97 +
.../amd/display/dc/dcn301/dcn301_resource.c | 2011 +++++++++++++++++
.../amd/display/dc/dcn301/dcn301_resource.h | 42 +
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 26 +-
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 3 +
.../drm/amd/display/dc/gpio/hw_translate.c | 3 +
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 33 +
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 4 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 5 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 +
drivers/gpu/drm/amd/display/dmub/src/Makefile | 2 +-
.../drm/amd/display/dmub/src/dmub_dcn301.c | 55 +
.../drm/amd/display/dmub/src/dmub_dcn301.h | 37 +
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 14 +
.../gpu/drm/amd/display/include/dal_asic_id.h | 10 +
.../gpu/drm/amd/display/include/dal_types.h | 5 +
.../display/include/grph_object_ctrl_defs.h | 17 +
50 files changed, 5238 insertions(+), 34 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index f24abf428534..c2283e6ea734 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -25,6 +25,15 @@ config DRM_AMD_DC_DCN3_0
Choose this option if you want to have
sienna_cichlid support for display engine
+config DRM_AMD_DC_DCN3_01
+ bool "DCN 3.01 family"
+ depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC_DCN
+ depends on DRM_AMD_DC_DCN3_0
+ help
+ Choose this option if you want to have
+ Van Gogh support for display engine
+
config DRM_AMD_DC_HDCP
bool "Enable HDCP support in DC"
depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 047b1e2dd8f1..6e6ec1d92488 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ ifdef CONFIG_DRM_AMD_DC_DCN3_0
DC_LIBS += dcn30
endif
+ifdef CONFIG_DRM_AMD_DC_DCN3_01
+DC_LIBS += dcn301
+endif
+
DC_LIBS += dce120
DC_LIBS += dce112
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 29d64e7e304f..8fa002ec6969 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1743,6 +1743,167 @@ static enum bp_result get_integrated_info_v11(
return BP_RESULT_OK;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+static enum bp_result get_integrated_info_v2_1(
+ struct bios_parser *bp,
+ struct integrated_info *info)
+{
+ struct atom_integrated_system_info_v2_1 *info_v2_1;
+ uint32_t i;
+
+ info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
+ DATA_TABLES(integratedsysteminfo));
+
+ if (info_v2_1 == NULL)
+ return BP_RESULT_BADBIOSTABLE;
+
+ info->gpu_cap_info =
+ le32_to_cpu(info_v2_1->gpucapinfo);
+ /*
+ * system_config: Bit[0] = 0 : PCIE power gating disabled
+ * = 1 : PCIE power gating enabled
+ * Bit[1] = 0 : DDR-PLL shut down disabled
+ * = 1 : DDR-PLL shut down enabled
+ * Bit[2] = 0 : DDR-PLL power down disabled
+ * = 1 : DDR-PLL power down enabled
+ */
+ info->system_config = le32_to_cpu(info_v2_1->system_config);
+ info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
+ info->memory_type = info_v2_1->memorytype;
+ info->ma_channel_number = info_v2_1->umachannelnumber;
+ info->dp_ss_control =
+ le16_to_cpu(info_v2_1->reserved1);
+
+ for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
+ info->ext_disp_conn_info.gu_id[i] =
+ info_v2_1->extdispconninfo.guid[i];
+ }
+
+ for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
+ info->ext_disp_conn_info.path[i].device_connector_id =
+ object_id_from_bios_object_id(
+ le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
+
+ info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
+ object_id_from_bios_object_id(
+ le16_to_cpu(
+ info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
+
+ info->ext_disp_conn_info.path[i].device_tag =
+ le16_to_cpu(
+ info_v2_1->extdispconninfo.path[i].device_tag);
+ info->ext_disp_conn_info.path[i].device_acpi_enum =
+ le16_to_cpu(
+ info_v2_1->extdispconninfo.path[i].device_acpi_enum);
+ info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
+ info_v2_1->extdispconninfo.path[i].auxddclut_index;
+ info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
+ info_v2_1->extdispconninfo.path[i].hpdlut_index;
+ info->ext_disp_conn_info.path[i].channel_mapping.raw =
+ info_v2_1->extdispconninfo.path[i].channelmapping;
+ info->ext_disp_conn_info.path[i].caps =
+ le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
+ }
+
+ info->ext_disp_conn_info.checksum =
+ info_v2_1->extdispconninfo.checksum;
+ info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
+ info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
+ for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+ info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
+ for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
+ info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+ info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
+ info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
+ for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+ info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
+ for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
+ info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+ info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
+ info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
+ for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+ info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
+ for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
+ info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+ info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
+ info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
+ for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+ info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
+ for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
+ info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+ info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+
+ info->edp1_info.edp_backlight_pwm_hz =
+ le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
+ info->edp1_info.edp_ss_percentage =
+ le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
+ info->edp1_info.edp_ss_rate_10hz =
+ le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
+ info->edp1_info.edp_pwr_on_off_delay =
+ info_v2_1->edp1_info.edp_pwr_on_off_delay;
+ info->edp1_info.edp_pwr_on_vary_bl_to_blon =
+ info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
+ info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
+ info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
+ info->edp1_info.edp_panel_bpc =
+ info_v2_1->edp1_info.edp_panel_bpc;
+ info->edp1_info.edp_bootup_bl_level =
+
+ info->edp2_info.edp_backlight_pwm_hz =
+ le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
+ info->edp2_info.edp_ss_percentage =
+ le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
+ info->edp2_info.edp_ss_rate_10hz =
+ le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
+ info->edp2_info.edp_pwr_on_off_delay =
+ info_v2_1->edp2_info.edp_pwr_on_off_delay;
+ info->edp2_info.edp_pwr_on_vary_bl_to_blon =
+ info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
+ info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
+ info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
+ info->edp2_info.edp_panel_bpc =
+ info_v2_1->edp2_info.edp_panel_bpc;
+ info->edp2_info.edp_bootup_bl_level =
+ info_v2_1->edp2_info.edp_bootup_bl_level;
+
+ return BP_RESULT_OK;
+}
+#endif
/*
* construct_integrated_info
@@ -1775,6 +1936,31 @@ static enum bp_result construct_integrated_info(
get_atom_data_table_revision(header, &revision);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ switch (revision.major) {
+ case 1:
+ switch (revision.minor) {
+ case 11:
+ case 12:
+ result = get_integrated_info_v11(bp, info);
+ break;
+ default:
+ return result;
+ }
+ break;
+ case 2:
+ switch (revision.minor) {
+ case 1:
+ result = get_integrated_info_v2_1(bp, info);
+ break;
+ default:
+ return result;
+ }
+ break;
+ default:
+ return result;
+ }
+#else
/* Don't need to check major revision as they are all 1 */
switch (revision.minor) {
case 11:
@@ -1784,6 +1970,7 @@ static enum bp_result construct_integrated_info(
default:
return result;
}
+#endif
}
if (result != BP_RESULT_OK)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 74c498b6774d..515dac743ae0 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -78,7 +78,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#endif
-
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case DCN_VERSION_3_01:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+#endif
default:
/* Unsupported DCE */
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 1a495759a034..8c6d0a2acba4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -125,3 +125,13 @@ AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DC
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
endif
+ifdef CONFIG_DRM_AMD_DC_DCN3_01
+###############################################################################
+# DCN301
+###############################################################################
+CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
+
+AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index efb909ef7a0f..270a8182682d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -42,6 +42,9 @@
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#include "dcn30/dcn30_clk_mgr.h"
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#include "dcn301/vg_clk_mgr.h"
+#endif
int clk_mgr_helper_get_active_display_cnt(
@@ -188,6 +191,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
break;
#endif /* Family RV and NV*/
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case FAMILY_VGH:
+ if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev))
+ vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ break;
+#endif
default:
ASSERT(0); /* Unknown Asic */
break;
@@ -205,8 +214,18 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
case FAMILY_NV:
if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
dcn3_clk_mgr_destroy(clk_mgr);
- break;
}
+ break;
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case FAMILY_VGH:
+ if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
+ vg_clk_mgr_destroy(clk_mgr);
+ break;
+#endif
+
+ default:
+ break;
}
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
new file mode 100644
index 000000000000..cfa8e02cf103
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+#include <linux/delay.h>
+
+#include "dcn301_smu.h"
+
+#include "vangogh_ip_offset.h"
+
+#include "mp/mp_11_5_0_offset.h"
+#include "mp/mp_11_5_0_sh_mask.h"
+
+#define REG(reg_name) \
+ (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+#define FN(reg_name, field) \
+ FD(reg_name##__##field)
+
+#define VBIOSSMC_MSG_GetSmuVersion 0x2
+#define VBIOSSMC_MSG_SetDispclkFreq 0x4
+#define VBIOSSMC_MSG_SetDprefclkFreq 0x5
+#define VBIOSSMC_MSG_SetDppclkFreq 0x6
+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7
+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8
+//#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA
+#define VBIOSSMC_MSG_GetFclkFrequency 0xA
+//#define VBIOSSMC_MSG_SetDisplayCount 0xC
+//#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
+#define VBIOSSMC_MSG_UpdatePmeRestore 0xD
+#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr
+#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF
+#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10
+#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11
+#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12
+
+#define VBIOSSMC_Status_BUSY 0x0
+#define VBIOSSMC_Result_OK 0x1
+#define VBIOSSMC_Result_Failed 0xFF
+#define VBIOSSMC_Result_UnknownCmd 0xFE
+#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
+#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+ uint32_t res_val = VBIOSSMC_Status_BUSY;
+
+ do {
+ res_val = REG_READ(MP1_SMN_C2PMSG_91);
+ if (res_val != VBIOSSMC_Status_BUSY)
+ break;
+
+ if (delay_us >= 1000)
+ msleep(delay_us/1000);
+ else if (delay_us > 0)
+ udelay(delay_us);
+ } while (max_retries--);
+
+ return res_val;
+}
+
+int dcn301_smu_send_msg_with_param(
+ struct clk_mgr_internal *clk_mgr,
+ unsigned int msg_id, unsigned int param)
+{
+ uint32_t result;
+
+ /* First clear response register */
+ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+ /* Set the parameter register for the SMU message, unit is Mhz */
+ REG_WRITE(MP1_SMN_C2PMSG_83, param);
+
+ /* Trigger the message transaction by writing the message ID */
+ REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
+
+ result = dcn301_smu_wait_for_response(clk_mgr, 10, 1000);
+
+ ASSERT(result == VBIOSSMC_Result_OK);
+
+ /* Actual dispclk set is returned in the parameter register */
+ return REG_READ(MP1_SMN_C2PMSG_83);
+}
+
+int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+{
+ return dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_GetSmuVersion,
+ 0);
+}
+
+
+int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+{
+ int actual_dispclk_set_mhz = -1;
+
+ /* Unit of SMU msg parameter is Mhz */
+ actual_dispclk_set_mhz = dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDispclkFreq,
+ requested_dispclk_khz / 1000);
+
+ return actual_dispclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
+{
+ int actual_dprefclk_set_mhz = -1;
+
+ actual_dprefclk_set_mhz = dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDprefclkFreq,
+ clk_mgr->base.dprefclk_khz / 1000);
+
+ /* TODO: add code for programing DP DTO, currently this is down by command table */
+
+ return actual_dprefclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
+{
+ int actual_dcfclk_set_mhz = -1;
+
+ actual_dcfclk_set_mhz = dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ requested_dcfclk_khz / 1000);
+
+ return actual_dcfclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
+{
+ int actual_min_ds_dcfclk_mhz = -1;
+
+ actual_min_ds_dcfclk_mhz = dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
+ requested_min_ds_dcfclk_khz / 1000);
+
+ return actual_min_ds_dcfclk_mhz * 1000;
+}
+
+int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
+{
+ int actual_dppclk_set_mhz = -1;
+
+ actual_dppclk_set_mhz = dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDppclkFreq,
+ requested_dpp_khz / 1000);
+
+ return actual_dppclk_set_mhz * 1000;
+}
+
+void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
+{
+ //TODO: Work with smu team to define optimization options.
+
+ dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+ idle_info);
+}
+
+void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+ union display_idle_optimization_u idle_info = { 0 };
+
+ if (enable) {
+ idle_info.idle_info.df_request_disabled = 1;
+ idle_info.idle_info.phy_ref_clk_off = 1;
+ }
+
+ dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+ idle_info.data);
+}
+
+void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
+{
+ dcn301_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_UpdatePmeRestore,
+ 0);
+}
+
+void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
+{
+ dcn301_smu_send_msg_with_param(clk_mgr,
+ VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
+}
+
+void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
+{
+ dcn301_smu_send_msg_with_param(clk_mgr,
+ VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
+}
+
+void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
+{
+ dcn301_smu_send_msg_with_param(clk_mgr,
+ VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
+}
+
+void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+ dcn301_smu_send_msg_with_param(clk_mgr,
+ VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
new file mode 100644
index 000000000000..b640df85a17f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_301_SMU_H_
+#define DAL_DC_301_SMU_H_
+
+#define SMU13_DRIVER_IF_VERSION 2
+
+typedef struct {
+ uint32_t fclk;
+ uint32_t memclk;
+ uint32_t voltage;
+} df_pstate_t;
+
+typedef struct {
+ uint32_t vclk;
+ uint32_t dclk;
+} vcn_clk_t;
+
+typedef enum {
+ DSPCLK_DCFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq; // in MHz
+ uint16_t Vid; // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t WmType; // Used for normal pstate change or memory retraining
+ uint8_t Padding[2];
+} WatermarkRowGeneric_t;
+
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+
+#define TABLE_WATERMARKS 1
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+
+
+#define VG_NUM_DCFCLK_DPM_LEVELS 7
+#define VG_NUM_DISPCLK_DPM_LEVELS 7
+#define VG_NUM_DPPCLK_DPM_LEVELS 7
+#define VG_NUM_SOCCLK_DPM_LEVELS 7
+#define VG_NUM_ISPICLK_DPM_LEVELS 7
+#define VG_NUM_ISPXCLK_DPM_LEVELS 7
+#define VG_NUM_VCN_DPM_LEVELS 5
+#define VG_NUM_FCLK_DPM_LEVELS 4
+#define VG_NUM_SOC_VOLTAGE_LEVELS 8
+
+// copy from vgh/vangogh/pmfw_driver_if.h
+struct vg_dpm_clocks {
+ uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS];
+ uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS];
+ uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];
+ uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS];
+ uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS];
+ uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS];
+ vcn_clk_t VcnClocks[VG_NUM_VCN_DPM_LEVELS];
+
+ uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS];
+
+ df_pstate_t DfPstateTable[VG_NUM_FCLK_DPM_LEVELS];
+
+ uint32_t MinGfxClk;
+ uint32_t MaxGfxClk;
+
+ uint8_t NumDfPstatesEnabled;
+ uint8_t NumDcfclkLevelsEnabled;
+ uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk
+ uint8_t NumSocClkLevelsEnabled;
+
+ uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk
+ uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
+ uint8_t spare[2];
+};
+
+struct smu_dpm_clks {
+ struct vg_dpm_clocks *dpm_clks;
+ union large_integer mc_address;
+};
+
+struct watermarks {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+};
+
+
+struct display_idle_optimization {
+ unsigned int df_request_disabled : 1;
+ unsigned int phy_ref_clk_off : 1;
+ unsigned int s0i2_rdy : 1;
+ unsigned int reserved : 29;
+};
+
+union display_idle_optimization_u {
+ struct display_idle_optimization idle_info;
+ uint32_t data;
+};
+
+
+int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
+int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
+int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
+int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
+int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
+int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
+void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
+void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
+void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
+void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
+void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+
+#endif /* DAL_DC_301_SMU_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
new file mode 100644
index 000000000000..98cbb0ac095c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -0,0 +1,834 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+// For dce12_get_dp_ref_freq_khz
+#include "dce100/dce_clk_mgr.h"
+
+// For dcn20_update_clocks_update_dpp_dto
+#include "dcn20/dcn20_clk_mgr.h"
+
+#include "vg_clk_mgr.h"
+
+#include "dcn301_smu.h"
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dm_helpers.h"
+
+#include "atomfirmware.h"
+#include "vangogh_ip_offset.h"
+#include "clk/clk_11_5_0_offset.h"
+#include "clk/clk_11_5_0_sh_mask.h"
+
+/* Constants */
+
+#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
+
+/* Macros */
+
+#define REG(reg_name) \
+ (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+/* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
+int vg_get_active_display_cnt_wa(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ int i, display_count;
+ bool tmds_present = false;
+
+ display_count = 0;
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_stream_state *stream = context->streams[i];
+
+ if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+ stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+ stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+ tmds_present = true;
+ }
+
+ for (i = 0; i < dc->link_count; i++) {
+ const struct dc_link *link = dc->links[i];
+
+ /*
+ * Only notify active stream or virtual stream.
+ * Need to notify virtual stream to work around
+ * headless case. HPD does not fire when system is in
+ * S0i2.
+ */
+ /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
+ if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
+ link->link_enc->funcs->is_dig_enabled(link->link_enc))
+ display_count++;
+ }
+
+ /* WA for hang on HDMI after display off back back on*/
+ if (display_count == 0 && tmds_present)
+ display_count = 1;
+
+ return display_count;
+}
+
+void vg_update_clocks(struct clk_mgr *clk_mgr_base,
+ struct dc_state *context,
+ bool safe_to_lower)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+ struct dc *dc = clk_mgr_base->ctx->dc;
+ int display_count;
+ bool update_dppclk = false;
+ bool update_dispclk = false;
+ bool dpp_clock_lowered = false;
+
+ if (dc->work_arounds.skip_clock_update)
+ return;
+
+ /*
+ * if it is safe to lower, but we are already in the lower state, we don't have to do anything
+ * also if safe to lower is false, we just go in the higher state
+ */
+ if (safe_to_lower) {
+ /* check that we're not already in lower */
+ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+
+ display_count = vg_get_active_display_cnt_wa(dc, context);
+ /* if we can go lower, go lower */
+ if (display_count == 0) {
+ union display_idle_optimization_u idle_info = { 0 };
+
+ idle_info.idle_info.df_request_disabled = 1;
+ idle_info.idle_info.phy_ref_clk_off = 1;
+
+ dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+ /* update power state */
+ clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+ }
+ }
+ } else {
+ /* check that we're not already in D0 */
+ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
+ union display_idle_optimization_u idle_info = { 0 };
+
+ dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+ /* update power state */
+ clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+ }
+ }
+
+ if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+ clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+ dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
+ }
+
+ if (should_set_clock(safe_to_lower,
+ new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+ clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+ dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+ }
+
+ // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
+ if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ if (new_clocks->dppclk_khz < 100000)
+ new_clocks->dppclk_khz = 100000;
+ }
+
+ if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
+ if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
+ dpp_clock_lowered = true;
+ clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+ update_dppclk = true;
+ }
+
+ if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+ clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+ dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+
+ update_dispclk = true;
+ }
+
+ if (dpp_clock_lowered) {
+ // increase per DPP DTO before lowering global dppclk
+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+ } else {
+ // increase global DPPCLK before lowering per DPP DTO
+ if (update_dppclk || update_dispclk)
+ dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+ // always update dtos unless clock is lowered and not safe to lower
+ if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ }
+}
+
+
+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+ /* get FbMult value */
+ struct fixed31_32 pll_req;
+ unsigned int fbmult_frac_val = 0;
+ unsigned int fbmult_int_val = 0;
+
+
+ /*
+ * Register value of fbmult is in 8.16 format, we are converting to 31.32
+ * to leverage the fix point operations available in driver
+ */
+
+ REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
+ REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
+
+ pll_req = dc_fixpt_from_int(fbmult_int_val);
+
+ /*
+ * since fractional part is only 16 bit in register definition but is 32 bit
+ * in our fix point definiton, need to shift left by 16 to obtain correct value
+ */
+ pll_req.value |= fbmult_frac_val << 16;
+
+ /* multiply by REFCLK period */
+ pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
+
+ /* integer part is now VCO frequency in kHz */
+ return dc_fixpt_floor(pll_req);
+}
+
+static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+ internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
+ internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
+
+ internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
+ internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
+
+ internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
+ internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
+
+ internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
+ internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
+
+ internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
+ internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
+}
+
+/* This function collect raw clk register values */
+static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+ struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+ struct dcn301_clk_internal internal = {0};
+ char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
+ unsigned int chars_printed = 0;
+ unsigned int remaining_buffer = log_info->bufSize;
+
+ vg_dump_clk_registers_internal(&internal, clk_mgr_base);
+
+ regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
+ regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
+ regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
+ regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
+ regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
+ regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
+
+ regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
+ if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+ regs_and_bypass->dppclk_bypass = 0;
+ regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
+ if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+ regs_and_bypass->dcfclk_bypass = 0;
+ regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
+ if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+ regs_and_bypass->dispclk_bypass = 0;
+ regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
+ if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+ regs_and_bypass->dprefclk_bypass = 0;
+
+ if (log_info->enabled) {
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
+ regs_and_bypass->dcfclk,
+ regs_and_bypass->dcf_deep_sleep_divider,
+ regs_and_bypass->dcf_deep_sleep_allow,
+ bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
+ regs_and_bypass->dprefclk,
+ bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
+ regs_and_bypass->dispclk,
+ bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ //split
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ // REGISTER VALUES
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
+ internal.CLK1_CLK3_CURRENT_CNT);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
+ internal.CLK1_CLK3_DS_CNTL);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
+ internal.CLK1_CLK3_ALLOW_DS);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
+ internal.CLK1_CLK2_CURRENT_CNT);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
+ internal.CLK1_CLK0_CURRENT_CNT);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
+ internal.CLK1_CLK1_CURRENT_CNT);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
+ internal.CLK1_CLK3_BYPASS_CNTL);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
+ internal.CLK1_CLK2_BYPASS_CNTL);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
+ internal.CLK1_CLK0_BYPASS_CNTL);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+
+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
+ internal.CLK1_CLK1_BYPASS_CNTL);
+ remaining_buffer -= chars_printed;
+ *log_info->sum_chars_printed += chars_printed;
+ log_info->pBuf += chars_printed;
+ }
+}
+
+/* This function produce translated logical clk state values*/
+void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
+{
+
+ struct clk_state_registers_and_bypass sb = { 0 };
+ struct clk_log_info log_info = { 0 };
+
+ vg_dump_clk_registers(&sb, clk_mgr_base, &log_info);
+
+ s->dprefclk_khz = sb.dprefclk * 1000;
+}
+
+void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+ dcn301_smu_enable_pme_wa(clk_mgr);
+}
+
+void vg_init_clocks(struct clk_mgr *clk_mgr)
+{
+ memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+ // Assumption is that boot state always supports pstate
+ clk_mgr->clks.p_state_change_support = true;
+ clk_mgr->clks.prev_p_state_change_support = true;
+ clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+}
+
+static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
+{
+ int i, num_valid_sets;
+
+ num_valid_sets = 0;
+
+ for (i = 0; i < WM_SET_COUNT; i++) {
+ /* skip empty entries, the smu array has no holes*/
+ if (!bw_params->wm_table.entries[i].valid)
+ continue;
+
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+ /* We will not select WM based on fclk, so leave it as unconstrained */
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+ if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
+ if (i == 0)
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
+ else {
+ /* add 1 to make it non-overlapping with next lvl */
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
+ bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+ }
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
+ bw_params->clk_table.entries[i].dcfclk_mhz;
+
+ } else {
+ /* unconstrained for memory retraining */
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+ /* Modify previous watermark range to cover up to max */
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+ }
+ num_valid_sets++;
+ }
+
+ ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+
+ /* modify the min and max to make sure we cover the whole range*/
+ table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
+ table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+
+ /* This is for writeback only, does not matter currently as no writeback support*/
+ table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
+ table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
+ table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
+ table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
+ table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
+}
+
+
+void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct watermarks *table = clk_mgr_base->smu_wm_set.wm_set;
+
+ if (!clk_mgr->smu_ver)
+ return;
+
+ if (!table || clk_mgr_base->smu_wm_set.mc_address.quad_part == 0)
+ return;
+
+ memset(table, 0, sizeof(*table));
+
+ vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
+
+ dcn301_smu_set_dram_addr_high(clk_mgr,
+ clk_mgr_base->smu_wm_set.mc_address.high_part);
+ dcn301_smu_set_dram_addr_low(clk_mgr,
+ clk_mgr_base->smu_wm_set.mc_address.low_part);
+ dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+static bool vg_are_clock_states_equal(struct dc_clocks *a,
+ struct dc_clocks *b)
+{
+ if (a->dispclk_khz != b->dispclk_khz)
+ return false;
+ else if (a->dppclk_khz != b->dppclk_khz)
+ return false;
+ else if (a->dcfclk_khz != b->dcfclk_khz)
+ return false;
+ else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+ return false;
+
+ return true;
+}
+
+
+static struct clk_mgr_funcs vg_funcs = {
+ .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ .update_clocks = vg_update_clocks,
+ .init_clocks = vg_init_clocks,
+ .enable_pme_wa = vg_enable_pme_wa,
+ .are_clock_states_equal = vg_are_clock_states_equal,
+ .notify_wm_ranges = vg_notify_wm_ranges
+};
+
+static struct clk_bw_params vg_bw_params = {
+ .vram_type = Ddr4MemType,
+ .num_channels = 1,
+ .clk_table = {
+ .entries = {
+ {
+ .voltage = 0,
+ .dcfclk_mhz = 400,
+ .fclk_mhz = 400,
+ .memclk_mhz = 800,
+ .socclk_mhz = 0,
+ },
+ {
+ .voltage = 0,
+ .dcfclk_mhz = 483,
+ .fclk_mhz = 800,
+ .memclk_mhz = 1600,
+ .socclk_mhz = 0,
+ },
+ {
+ .voltage = 0,
+ .dcfclk_mhz = 602,
+ .fclk_mhz = 1067,
+ .memclk_mhz = 1067,
+ .socclk_mhz = 0,
+ },
+ {
+ .voltage = 0,
+ .dcfclk_mhz = 738,
+ .fclk_mhz = 1333,
+ .memclk_mhz = 1600,
+ .socclk_mhz = 0,
+ },
+ },
+
+ .num_entries = 4,
+ },
+
+};
+
+static struct wm_table ddr4_wm_table = {
+ .entries = {
+ {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.72,
+ .sr_exit_time_us = 6.09,
+ .sr_enter_plus_exit_time_us = 7.14,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.72,
+ .sr_exit_time_us = 10.12,
+ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.72,
+ .sr_exit_time_us = 10.12,
+ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.72,
+ .sr_exit_time_us = 10.12,
+ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ }
+};
+
+static struct wm_table lpddr5_wm_table = {
+ .entries = {
+ {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 5.32,
+ .sr_enter_plus_exit_time_us = 6.38,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.82,
+ .sr_enter_plus_exit_time_us = 11.196,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.89,
+ .sr_enter_plus_exit_time_us = 11.24,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.748,
+ .sr_enter_plus_exit_time_us = 11.102,
+ .valid = true,
+ },
+ }
+};
+
+
+static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
+ unsigned int voltage)
+{
+ int i;
+
+ for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
+ if (clock_table->SocVoltage[i] == voltage)
+ return clock_table->DcfClocks[i];
+ }
+
+ ASSERT(0);
+ return 0;
+}
+
+static void vg_clk_mgr_helper_populate_bw_params(
+ struct clk_mgr_internal *clk_mgr,
+ struct integrated_info *bios_info,
+ const struct vg_dpm_clocks *clock_table)
+{
+ int i, j;
+ struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
+
+ j = -1;
+
+ ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+
+ /* Find lowest DPM, FCLK is filled in reverse order*/
+
+ for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
+ if (clock_table->DfPstateTable[i].fclk != 0) {
+ j = i;
+ break;
+ }
+ }
+
+ if (j == -1) {
+ /* clock table is all 0s, just use our own hardcode */
+ ASSERT(0);
+ return;
+ }
+
+ bw_params->clk_table.num_entries = j + 1;
+
+ for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+ bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
+ bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
+ bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
+ bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
+ }
+
+ bw_params->vram_type = bios_info->memory_type;
+ bw_params->num_channels = bios_info->ma_channel_number;
+
+ for (i = 0; i < WM_SET_COUNT; i++) {
+ bw_params->wm_table.entries[i].wm_inst = i;
+
+ if (i >= bw_params->clk_table.num_entries) {
+ bw_params->wm_table.entries[i].valid = false;
+ continue;
+ }
+
+ bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
+ bw_params->wm_table.entries[i].valid = true;
+ }
+
+ if (bw_params->vram_type == LpDdr4MemType) {
+ /*
+ * WM set D will be re-purposed for memory retraining
+ */
+ bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
+ bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
+ bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
+ bw_params->wm_table.entries[WM_D].valid = true;
+ }
+
+}
+
+/* Temporary Place holder until we can get them from fuse */
+static struct vg_dpm_clocks dummy_clocks = {
+ .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
+ .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
+ .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
+ .DfPstateTable = {
+ { .fclk = 400, .memclk = 400, .voltage = 2800 },
+ { .fclk = 400, .memclk = 400, .voltage = 2800 },
+ { .fclk = 400, .memclk = 400, .voltage = 2800 },
+ { .fclk = 400, .memclk = 400, .voltage = 2800 }
+ }
+};
+
+static struct watermarks dummy_wms = { 0 };
+
+static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
+ struct smu_dpm_clks *smu_dpm_clks)
+{
+ struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
+
+ if (!clk_mgr->smu_ver)
+ return;
+
+ if (!table || smu_dpm_clks->mc_address.quad_part == 0)
+ return;
+
+ memset(table, 0, sizeof(*table));
+
+ dcn301_smu_set_dram_addr_high(clk_mgr,
+ smu_dpm_clks->mc_address.high_part);
+ dcn301_smu_set_dram_addr_low(clk_mgr,
+ smu_dpm_clks->mc_address.low_part);
+ dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
+}
+
+void vg_clk_mgr_construct(
+ struct dc_context *ctx,
+ struct clk_mgr_internal *clk_mgr,
+ struct pp_smu_funcs *pp_smu,
+ struct dccg *dccg)
+{
+ struct smu_dpm_clks smu_dpm_clks = { 0 };
+
+ clk_mgr->base.ctx = ctx;
+ clk_mgr->base.funcs = &vg_funcs;
+
+ clk_mgr->pp_smu = pp_smu;
+
+ clk_mgr->dccg = dccg;
+ clk_mgr->dfs_bypass_disp_clk = 0;
+
+ clk_mgr->dprefclk_ss_percentage = 0;
+ clk_mgr->dprefclk_ss_divider = 1000;
+ clk_mgr->ss_on_dprefclk = false;
+ clk_mgr->dfs_ref_freq_khz = 48000;
+
+ clk_mgr->base.smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
+ clk_mgr->base.ctx,
+ DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+ sizeof(struct watermarks),
+ &clk_mgr->base.smu_wm_set.mc_address.quad_part);
+
+ if (clk_mgr->base.smu_wm_set.wm_set == 0) {
+ clk_mgr->base.smu_wm_set.wm_set = &dummy_wms;
+ clk_mgr->base.smu_wm_set.mc_address.quad_part = 0;
+ }
+ ASSERT(clk_mgr->base.smu_wm_set.wm_set);
+
+ smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
+ clk_mgr->base.ctx,
+ DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+ sizeof(struct vg_dpm_clocks),
+ &smu_dpm_clks.mc_address.quad_part);
+
+ if (smu_dpm_clks.dpm_clks == NULL) {
+ smu_dpm_clks.dpm_clks = &dummy_clocks;
+ smu_dpm_clks.mc_address.quad_part = 0;
+ }
+
+ ASSERT(smu_dpm_clks.dpm_clks);
+
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ vg_funcs.update_clocks = dcn2_update_clocks_fpga;
+ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ } else {
+ struct clk_log_info log_info = {0};
+
+ clk_mgr->smu_ver = dcn301_smu_get_smu_version(clk_mgr);
+
+ if (clk_mgr->smu_ver)
+ clk_mgr->smu_present = true;
+
+ /* TODO: Check we get what we expect during bringup */
+ clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
+
+ /* in case we don't get a value from the register, use default */
+ if (clk_mgr->base.dentist_vco_freq_khz == 0)
+ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+
+ if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+ vg_bw_params.wm_table = lpddr5_wm_table;
+ } else {
+ vg_bw_params.wm_table = ddr4_wm_table;
+ }
+ /* Saved clocks configured at boot for debug purposes */
+ vg_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
+ }
+
+ clk_mgr->base.dprefclk_khz = 600000;
+ dce_clock_read_ss_info(clk_mgr);
+
+ clk_mgr->base.bw_params = &vg_bw_params;
+
+ vg_get_dpm_table_from_smu(clk_mgr, &smu_dpm_clks);
+ if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+ vg_clk_mgr_helper_populate_bw_params(
+ clk_mgr,
+ ctx->dc_bios->integrated_info,
+ smu_dpm_clks.dpm_clks);
+ }
+
+ if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
+ dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+ smu_dpm_clks.dpm_clks);
+/*
+ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver) {
+ enable powerfeatures when displaycount goes to 0
+ dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+ }
+*/
+}
+
+void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
+{
+ if (clk_mgr->base.smu_wm_set.wm_set && clk_mgr->base.smu_wm_set.mc_address.quad_part != 0)
+ dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+ clk_mgr->base.smu_wm_set.wm_set);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
new file mode 100644
index 000000000000..80497df20ba7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __VG_CLK_MGR_H__
+#define __VG_CLK_MGR_H__
+
+int vg_get_active_display_cnt_wa(
+ struct dc *dc,
+ struct dc_state *context);
+
+void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base);
+
+void vg_clk_mgr_construct(struct dc_context *ctx,
+ struct clk_mgr_internal *clk_mgr,
+ struct pp_smu_funcs *pp_smu,
+ struct dccg *dccg);
+
+void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
+
+void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base);
+#endif //__VG_CLK_MGR_H__
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index e430148e47cf..f240576a87a2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -58,6 +58,9 @@
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#include "../dcn30/dcn30_resource.h"
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#include "../dcn301/dcn301_resource.h"
+#endif
#define DC_LOGGER_INIT(logger)
@@ -130,6 +133,12 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
dc_version = DCN_VERSION_3_0;
#endif
break;
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case FAMILY_VGH:
+ dc_version = DCN_VERSION_3_01;
+ break;
+#endif
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
@@ -210,6 +219,11 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
break;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case DCN_VERSION_3_01:
+ res_pool = dcn301_create_resource_pool(init_data, dc);
+ break;
+#endif
default:
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e84d21605854..389ca0d54d1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -82,6 +82,22 @@
SR(DC_ABM1_ACE_THRES_12), \
NBIO_SR(BIOS_SCRATCH_2)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define ABM_DCN301_REG_LIST(id)\
+ ABM_COMMON_REG_LIST_DCE_BASE(), \
+ SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+ SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+ SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+ SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+ SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+ SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+ SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+ SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+ SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+ SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+ NBIO_SR(BIOS_SCRATCH_2)
+#endif
+
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define ABM_DCN30_REG_LIST(id)\
ABM_COMMON_REG_LIST_DCE_BASE(), \
@@ -173,7 +189,7 @@
#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
#define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 9cc65dc1970f..512b26b3e3fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1554,3 +1554,21 @@ bool dcn3_clk_src_construct(
return ret;
}
#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+bool dcn301_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask)
+{
+ bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
+
+ clk_src->base.funcs = &dcn3_clk_src_funcs;
+
+ return ret;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 69b904ab8151..41e6f7ea2138 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -108,6 +108,23 @@
SRII(PIXEL_RATE_CNTL, OTG, 3)
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
+ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+ SRII(PHASE, DP_DTO, 0),\
+ SRII(PHASE, DP_DTO, 1),\
+ SRII(PHASE, DP_DTO, 2),\
+ SRII(PHASE, DP_DTO, 3),\
+ SRII(MODULO, DP_DTO, 0),\
+ SRII(MODULO, DP_DTO, 1),\
+ SRII(MODULO, DP_DTO, 2),\
+ SRII(MODULO, DP_DTO, 3),\
+ SRII(PIXEL_RATE_CNTL, OTG, 0),\
+ SRII(PIXEL_RATE_CNTL, OTG, 1),\
+ SRII(PIXEL_RATE_CNTL, OTG, 2),\
+ SRII(PIXEL_RATE_CNTL, OTG, 3)
+#endif
+
#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
@@ -232,6 +249,17 @@ bool dcn3_clk_src_construct(
const struct dce110_clk_src_mask *cs_mask);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+bool dcn301_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask);
+#endif
+
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
struct pixel_rate_range_table_entry {
unsigned int range_min_khz;
@@ -246,4 +274,5 @@ extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
unsigned int pixel_rate_khz);
#endif
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 70bbc1311327..49e1a4c72684 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -224,28 +224,6 @@
SR(VGA_TEST_CONTROL), \
SR(DC_IP_REQUEST_CNTL)
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define HWSEQ_DCN30_REG_LIST()\
- HWSEQ_DCN2_REG_LIST(),\
- HWSEQ_DCN_REG_LIST(), \
- HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
- HWSEQ_PHYPLL_REG_LIST_3(OTG), \
- SR(MICROSECOND_TIME_BASE_DIV), \
- SR(MILLISECOND_TIME_BASE_DIV), \
- SR(DISPCLK_FREQ_CHANGE_CNTL), \
- SR(RBBMIF_TIMEOUT_DIS), \
- SR(RBBMIF_TIMEOUT_DIS_2), \
- SR(DCHUBBUB_CRC_CTRL), \
- SR(DPP_TOP0_DPP_CRC_CTRL), \
- SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
- SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
- SR(MPC_CRC_CTRL), \
- SR(MPC_CRC_RESULT_GB), \
- SR(MPC_CRC_RESULT_C), \
- SR(MPC_CRC_RESULT_AR), \
- SR(AZALIA_AUDIO_DTO), \
- SR(AZALIA_CONTROLLER_CLOCK_GATING)
-#endif
#define HWSEQ_DCN2_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
@@ -361,6 +339,93 @@
SR(D6VGA_CONTROL), \
SR(DC_IP_REQUEST_CNTL)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define HWSEQ_DCN30_REG_LIST()\
+ HWSEQ_DCN2_REG_LIST(),\
+ HWSEQ_DCN_REG_LIST(), \
+ HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
+ HWSEQ_PHYPLL_REG_LIST_3(OTG), \
+ SR(MICROSECOND_TIME_BASE_DIV), \
+ SR(MILLISECOND_TIME_BASE_DIV), \
+ SR(DISPCLK_FREQ_CHANGE_CNTL), \
+ SR(RBBMIF_TIMEOUT_DIS), \
+ SR(RBBMIF_TIMEOUT_DIS_2), \
+ SR(DCHUBBUB_CRC_CTRL), \
+ SR(DPP_TOP0_DPP_CRC_CTRL), \
+ SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+ SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+ SR(MPC_CRC_CTRL), \
+ SR(MPC_CRC_RESULT_GB), \
+ SR(MPC_CRC_RESULT_C), \
+ SR(MPC_CRC_RESULT_AR), \
+ SR(AZALIA_AUDIO_DTO), \
+ SR(AZALIA_CONTROLLER_CLOCK_GATING)
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define HWSEQ_DCN301_REG_LIST()\
+ SR(REFCLK_CNTL), \
+ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+ SR(DIO_MEM_PWR_CTRL), \
+ SR(DCCG_GATE_DISABLE_CNTL), \
+ SR(DCCG_GATE_DISABLE_CNTL2), \
+ SR(DCFCLK_CNTL),\
+ SR(DCFCLK_CNTL), \
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+ SRII(PIXEL_RATE_CNTL, OTG, 0), \
+ SRII(PIXEL_RATE_CNTL, OTG, 1),\
+ SRII(PIXEL_RATE_CNTL, OTG, 2),\
+ SRII(PIXEL_RATE_CNTL, OTG, 3),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+ SR(MICROSECOND_TIME_BASE_DIV), \
+ SR(MILLISECOND_TIME_BASE_DIV), \
+ SR(DISPCLK_FREQ_CHANGE_CNTL), \
+ SR(RBBMIF_TIMEOUT_DIS), \
+ SR(RBBMIF_TIMEOUT_DIS_2), \
+ SR(DCHUBBUB_CRC_CTRL), \
+ SR(DPP_TOP0_DPP_CRC_CTRL), \
+ SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+ SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+ SR(MPC_CRC_CTRL), \
+ SR(MPC_CRC_RESULT_GB), \
+ SR(MPC_CRC_RESULT_C), \
+ SR(MPC_CRC_RESULT_AR), \
+ SR(DOMAIN0_PG_CONFIG), \
+ SR(DOMAIN1_PG_CONFIG), \
+ SR(DOMAIN2_PG_CONFIG), \
+ SR(DOMAIN3_PG_CONFIG), \
+ SR(DOMAIN4_PG_CONFIG), \
+ SR(DOMAIN5_PG_CONFIG), \
+ SR(DOMAIN6_PG_CONFIG), \
+ SR(DOMAIN7_PG_CONFIG), \
+ SR(DOMAIN16_PG_CONFIG), \
+ SR(DOMAIN17_PG_CONFIG), \
+ SR(DOMAIN18_PG_CONFIG), \
+ SR(DOMAIN0_PG_STATUS), \
+ SR(DOMAIN1_PG_STATUS), \
+ SR(DOMAIN2_PG_STATUS), \
+ SR(DOMAIN3_PG_STATUS), \
+ SR(DOMAIN4_PG_STATUS), \
+ SR(DOMAIN5_PG_STATUS), \
+ SR(DOMAIN6_PG_STATUS), \
+ SR(DOMAIN7_PG_STATUS), \
+ SR(DOMAIN16_PG_STATUS), \
+ SR(DOMAIN17_PG_STATUS), \
+ SR(DOMAIN18_PG_STATUS), \
+ SR(D1VGA_CONTROL), \
+ SR(D2VGA_CONTROL), \
+ SR(D3VGA_CONTROL), \
+ SR(D4VGA_CONTROL), \
+ SR(D5VGA_CONTROL), \
+ SR(D6VGA_CONTROL), \
+ SR(DC_IP_REQUEST_CNTL), \
+ SR(AZALIA_AUDIO_DTO), \
+ SR(AZALIA_CONTROLLER_CLOCK_GATING)
+#endif
+
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
uint32_t DCFEV_CLOCK_CONTROL;
@@ -598,12 +663,6 @@ struct dce_hwseq_registers {
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
- HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
- HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
-#endif
-
#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
@@ -703,6 +762,57 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
+ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+ HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
+ HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+ HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
+ HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
+ HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
+ HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\
+ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+#endif
+
#define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \
type DCFEV_CLOCK_ENABLE; \
@@ -817,14 +927,39 @@ struct dce_hwseq_registers {
type D4VGA_MODE_ENABLE; \
type AZALIA_AUDIO_DTO_MODULE;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
+ type HPO_HDMISTREAMCLK_GATE_DIS;
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define HWSEQ_DCN301_REG_FIELD_LIST(type) \
+ type PANEL_BLON;\
+ type PANEL_DIGON;\
+ type PANEL_DIGON_OVRD;\
+ type PANEL_PWRSEQ_TARGET_STATE_R;
+#endif
+
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
+#endif
};
struct dce_hwseq_mask {
HWSEQ_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
+#endif
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 04dabed5f1c5..1ac734d0d5e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -449,14 +449,32 @@ struct dcn10_link_enc_registers {
type AUX_RX_TIMEOUT_LEN;\
type AUX_RX_TIMEOUT_LEN_MUL
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+
+#define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
+ type TMDS_SYNC_DCBAL_EN;\
+ type PHY_HPO_DIG_SRC_SEL;\
+ type PHY_HPO_ENC_SRC_SEL;\
+ type DPCS_TX_HDMI_FRL_MODE;\
+ type DPCS_TX_DATA_SWAP_10_BIT;\
+ type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
+ type RDPCS_TX_CLK_EN
+#endif
+
struct dcn10_link_enc_shift {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+#endif
};
struct dcn10_link_enc_mask {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+#endif
};
struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
index 982732dec133..2c68a246fa83 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
@@ -384,6 +384,16 @@ void hubbub3_force_wm_propagate_to_pipes(struct hubbub *hubbub)
DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
}
+void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
+ bool force, bool allow)
+{
+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+
+ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, allow,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);
+}
+
static const struct hubbub_funcs hubbub30_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
@@ -397,6 +407,7 @@ static const struct hubbub_funcs hubbub30_funcs = {
.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
+ .force_pstate_change_control = hubbub3_force_pstate_change_control,
};
void hubbub3_construct(struct dcn20_hubbub *hubbub3,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
index 790baa00672b..38f1d2fd939b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
@@ -116,4 +116,7 @@ bool hubbub3_program_watermarks(
unsigned int refclk_mhz,
bool safe_to_lower);
+void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
+ bool force, bool allow);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
index fd1fb3c531d1..67f5776b5f3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
@@ -251,6 +251,11 @@ bool hubp3_construct(
const struct dcn_hubp2_shift *hubp_shift,
const struct dcn_hubp2_mask *hubp_mask);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
+ struct vm_system_aperture_param *apt);
+#endif
+
bool hubp3_program_surface_flip_and_addr(
struct hubp *hubp,
const struct dc_plane_address *address,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index dde87baf1370..ac57c3b14bc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2127,7 +2127,7 @@ static bool dcn30_internal_validate_bw(
return out;
}
-static void dcn30_calculate_wm(
+void dcn30_calculate_wm(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index c9d5f94092a0..1773df07e30a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -55,6 +55,11 @@ unsigned int dcn30_calc_max_scaled_time(
bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
bool fast_validate);
+void dcn30_calculate_wm(
+ struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel);
void dcn30_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
new file mode 100644
index 000000000000..2fd5d34e4ba6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
@@ -0,0 +1,47 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+# All rights reserved. This notice is intended as a precaution against
+# inadvertent publication and does not imply publication or any waiver
+# of confidentiality. The year included in the foregoing notice is the
+# year of creation of the work.
+#
+# Authors: AMD
+#
+# Makefile for dcn30.
+
+DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
+ dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mgeneral-regs-only
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN301)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
new file mode 100644
index 000000000000..420da414929c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn301_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+ container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+ (dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+ dccg_dcn->base.ctx
+#define DC_LOGGER \
+ dccg->ctx->logger
+
+static const struct dccg_funcs dccg301_funcs = {
+ .update_dpp_dto = dccg2_update_dpp_dto,
+ .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+ .dccg_init = dccg2_init
+};
+
+struct dccg *dccg301_create(
+ struct dc_context *ctx,
+ const struct dccg_registers *regs,
+ const struct dccg_shift *dccg_shift,
+ const struct dccg_mask *dccg_mask)
+{
+ struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+ struct dccg *base;
+
+ if (dccg_dcn == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ base = &dccg_dcn->base;
+ base->ctx = ctx;
+ base->funcs = &dccg301_funcs;
+
+ dccg_dcn->regs = regs;
+ dccg_dcn->dccg_shift = dccg_shift;
+ dccg_dcn->dccg_mask = dccg_mask;
+
+ return &dccg_dcn->base;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h
new file mode 100644
index 000000000000..73db962dbc03
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN301_DCCG_H__
+#define __DCN301_DCCG_H__
+
+#include "dcn20/dcn20_dccg.h"
+
+#define DCCG_REG_LIST_DCN301() \
+ SR(DPPCLK_DTO_CTRL),\
+ DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+ DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+ DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+ DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+ SR(REFCLK_CNTL)
+
+#define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+ DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
+ DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+
+struct dccg *dccg301_create(
+ struct dc_context *ctx,
+ const struct dccg_registers *regs,
+ const struct dccg_shift *dccg_shift,
+ const struct dccg_mask *dccg_mask);
+
+struct dccg *dccg301_create(
+ struct dc_context *ctx,
+ const struct dccg_registers *regs,
+ const struct dccg_shift *dccg_shift,
+ const struct dccg_mask *dccg_mask);
+
+#endif //__DCN301_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
new file mode 100644
index 000000000000..c9fbaed23965
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn301_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+#include "gpio_service_interface.h"
+
+#define CTX \
+ enc10->base.ctx
+#define DC_LOGGER \
+ enc10->base.ctx->logger
+
+#define REG(reg)\
+ (enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define IND_REG(index) \
+ (enc10->link_regs->index)
+
+static const struct link_encoder_funcs dcn301_link_enc_funcs = {
+ .read_state = link_enc2_read_state,
+ .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream,
+ .hw_init = enc3_hw_init,
+ .setup = dcn10_link_encoder_setup,
+ .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+ .enable_dp_output = dcn20_link_encoder_enable_dp_output,
+ .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+ .disable_output = dcn10_link_encoder_disable_output,
+ .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+ .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+ .update_mst_stream_allocation_table = dcn10_link_encoder_update_mst_stream_allocation_table,
+ .psr_program_dp_dphy_fast_training = dcn10_psr_program_dp_dphy_fast_training,
+ .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+ .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+ .enable_hpd = dcn10_link_encoder_enable_hpd,
+ .disable_hpd = dcn10_link_encoder_disable_hpd,
+ .is_dig_enabled = dcn10_is_dig_enabled,
+ .destroy = dcn10_link_encoder_destroy,
+ .fec_set_enable = enc2_fec_set_enable,
+ .fec_set_ready = enc2_fec_set_ready,
+ .fec_is_active = enc2_fec_is_active,
+ .get_dig_frontend = dcn10_get_dig_frontend,
+ .get_dig_mode = dcn10_get_dig_mode,
+ .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+ .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+};
+
+void dcn301_link_encoder_construct(
+ struct dcn20_link_encoder *enc20,
+ const struct encoder_init_data *init_data,
+ const struct encoder_feature_support *enc_features,
+ const struct dcn10_link_enc_registers *link_regs,
+ const struct dcn10_link_enc_aux_registers *aux_regs,
+ const struct dcn10_link_enc_hpd_registers *hpd_regs,
+ const struct dcn10_link_enc_shift *link_shift,
+ const struct dcn10_link_enc_mask *link_mask)
+{
+ struct bp_encoder_cap_info bp_cap_info = {0};
+ const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+ enum bp_result result = BP_RESULT_OK;
+ struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+ enc10->base.funcs = &dcn301_link_enc_funcs;
+ enc10->base.ctx = init_data->ctx;
+ enc10->base.id = init_data->encoder;
+
+ enc10->base.hpd_source = init_data->hpd_source;
+ enc10->base.connector = init_data->connector;
+
+ enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+ enc10->base.features = *enc_features;
+
+ enc10->base.transmitter = init_data->transmitter;
+
+ /* set the flag to indicate whether driver poll the I2C data pin
+ * while doing the DP sink detect
+ */
+
+/* if (dal_adapter_service_is_feature_supported(as,
+ FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+ enc10->base.features.flags.bits.
+ DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+ enc10->base.output_signals =
+ SIGNAL_TYPE_DVI_SINGLE_LINK |
+ SIGNAL_TYPE_DVI_DUAL_LINK |
+ SIGNAL_TYPE_LVDS |
+ SIGNAL_TYPE_DISPLAY_PORT |
+ SIGNAL_TYPE_DISPLAY_PORT_MST |
+ SIGNAL_TYPE_EDP |
+ SIGNAL_TYPE_HDMI_TYPE_A;
+
+ /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
+ * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
+ * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
+ * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
+ * Prefer DIG assignment is decided by board design.
+ * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
+ * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
+ * By this, adding DIGG should not hurt DCE 8.0.
+ * This will let DCE 8.1 share DCE 8.0 as much as possible
+ */
+
+ enc10->link_regs = link_regs;
+ enc10->aux_regs = aux_regs;
+ enc10->hpd_regs = hpd_regs;
+ enc10->link_shift = link_shift;
+ enc10->link_mask = link_mask;
+
+ switch (enc10->base.transmitter) {
+ case TRANSMITTER_UNIPHY_A:
+ enc10->base.preferred_engine = ENGINE_ID_DIGA;
+ break;
+ case TRANSMITTER_UNIPHY_B:
+ enc10->base.preferred_engine = ENGINE_ID_DIGB;
+ break;
+ case TRANSMITTER_UNIPHY_C:
+ enc10->base.preferred_engine = ENGINE_ID_DIGC;
+ break;
+ case TRANSMITTER_UNIPHY_D:
+ enc10->base.preferred_engine = ENGINE_ID_DIGD;
+ break;
+ case TRANSMITTER_UNIPHY_E:
+ enc10->base.preferred_engine = ENGINE_ID_DIGE;
+ break;
+ case TRANSMITTER_UNIPHY_F:
+ enc10->base.preferred_engine = ENGINE_ID_DIGF;
+ break;
+ case TRANSMITTER_UNIPHY_G:
+ enc10->base.preferred_engine = ENGINE_ID_DIGG;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+ }
+
+ /* default to one to mirror Windows behavior */
+ enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+ result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
+ enc10->base.id, &bp_cap_info);
+
+ /* Override features with DCE-specific values */
+ if (result == BP_RESULT_OK) {
+ enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+ bp_cap_info.DP_HBR2_EN;
+ enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+ bp_cap_info.DP_HBR3_EN;
+ enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+ enc10->base.features.flags.bits.DP_IS_USB_C =
+ bp_cap_info.DP_IS_USB_C;
+ } else {
+ DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+ __func__,
+ result);
+ }
+ if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+ enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
new file mode 100644
index 000000000000..49f8d91d4951
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN301_H__
+#define __DC_LINK_ENCODER__DCN301_H__
+
+#include "dcn20/dcn20_link_encoder.h"
+
+
+#define LE_DCN301_REG_LIST(id)\
+ SRI(DIG_BE_CNTL, DIG, id), \
+ SRI(DIG_BE_EN_CNTL, DIG, id), \
+ SRI(TMDS_CTL_BITS, DIG, id), \
+ SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
+ SRI(DP_CONFIG, DP, id), \
+ SRI(DP_DPHY_CNTL, DP, id), \
+ SRI(DP_DPHY_PRBS_CNTL, DP, id), \
+ SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
+ SRI(DP_DPHY_SYM0, DP, id), \
+ SRI(DP_DPHY_SYM1, DP, id), \
+ SRI(DP_DPHY_SYM2, DP, id), \
+ SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
+ SRI(DP_LINK_CNTL, DP, id), \
+ SRI(DP_LINK_FRAMING_CNTL, DP, id), \
+ SRI(DP_MSE_SAT0, DP, id), \
+ SRI(DP_MSE_SAT1, DP, id), \
+ SRI(DP_MSE_SAT2, DP, id), \
+ SRI(DP_MSE_SAT_UPDATE, DP, id), \
+ SRI(DP_SEC_CNTL, DP, id), \
+ SRI(DP_VID_STREAM_CNTL, DP, id), \
+ SRI(DP_DPHY_FAST_TRAINING, DP, id), \
+ SRI(DP_SEC_CNTL1, DP, id), \
+ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN301(mask_sh) \
+ LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
+ LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
+
+#define DPCS_DCN301_MASK_SH_LIST(mask_sh)\
+ DPCS_DCN2_MASK_SH_LIST(mask_sh),\
+ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_HDMI_FRL_MODE, mask_sh),\
+ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP_10_BIT, mask_sh),\
+ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
+ LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
+ LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh)
+
+void dcn301_link_encoder_construct(
+ struct dcn20_link_encoder *enc20,
+ const struct encoder_init_data *init_data,
+ const struct encoder_feature_support *enc_features,
+ const struct dcn10_link_enc_registers *link_regs,
+ const struct dcn10_link_enc_aux_registers *aux_regs,
+ const struct dcn10_link_enc_hpd_registers *hpd_regs,
+ const struct dcn10_link_enc_shift *link_shift,
+ const struct dcn10_link_enc_mask *link_mask);
+
+void enc3_hw_init(struct link_encoder *enc);
+
+#endif /* __DC_LINK_ENCODER__DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
new file mode 100644
index 000000000000..a0b96b3c083f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
@@ -0,0 +1,81 @@
+/*
+* Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dcn301_hubbub.h"
+#include "reg_helper.h"
+
+#define REG(reg)\
+ hubbub1->regs->reg
+#define DC_LOGGER \
+ hubbub1->base.ctx->logger
+#define CTX \
+ hubbub1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ hubbub1->shifts->field_name, hubbub1->masks->field_name
+
+#define REG(reg)\
+ hubbub1->regs->reg
+
+#define CTX \
+ hubbub1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ hubbub1->shifts->field_name, hubbub1->masks->field_name
+
+
+static const struct hubbub_funcs hubbub301_funcs = {
+ .update_dchub = hubbub2_update_dchub,
+ .init_dchub_sys_ctx = hubbub21_init_dchub,
+ .init_vm_ctx = hubbub2_init_vm_ctx,
+ .dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+ .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+ .get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
+ .wm_read_state = hubbub21_wm_read_state,
+ .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+ .program_watermarks = hubbub3_program_watermarks,
+ .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+ .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+ .force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
+ .force_pstate_change_control = hubbub3_force_pstate_change_control,
+};
+
+void hubbub301_construct(struct dcn20_hubbub *hubbub3,
+ struct dc_context *ctx,
+ const struct dcn_hubbub_registers *hubbub_regs,
+ const struct dcn_hubbub_shift *hubbub_shift,
+ const struct dcn_hubbub_mask *hubbub_mask)
+{
+ hubbub3->base.ctx = ctx;
+ hubbub3->base.funcs = &hubbub301_funcs;
+ hubbub3->regs = hubbub_regs;
+ hubbub3->shifts = hubbub_shift;
+ hubbub3->masks = hubbub_mask;
+
+ hubbub3->debug_test_index_pstate = 0xB;
+ hubbub3->detile_buf_size = 184 * 1024; /* 184KB for DCN3 */
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h
new file mode 100644
index 000000000000..b599f4475479
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef DAL_DC_DCN301_DCN301_HUBBUB_H_
+#define DAL_DC_DCN301_DCN301_HUBBUB_H_
+
+#include "dcn30/dcn30_hubbub.h"
+
+
+#define HUBBUB_REG_LIST_DCN301(id)\
+ HUBBUB_REG_LIST_DCN30(id), \
+ HUBBUB_HVM_REG_LIST()
+
+
+#define HUBBUB_MASK_SH_LIST_DCN301(mask_sh)\
+ HUBBUB_MASK_SH_LIST_DCN30(mask_sh), \
+ HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \
+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \
+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \
+ HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \
+ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \
+ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \
+ HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \
+ HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh)
+
+void hubbub301_construct(struct dcn20_hubbub *hubbub3,
+ struct dc_context *ctx,
+ const struct dcn_hubbub_registers *hubbub_regs,
+ const struct dcn_hubbub_shift *hubbub_shift,
+ const struct dcn_hubbub_mask *hubbub_mask);
+
+
+#endif /* DAL_DC_DCN301_DCN301_HUBBUB_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c
new file mode 100644
index 000000000000..10bedb2ea62a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "dce/dce_hwseq.h"
+#include "dcn301_hwseq.h"
+#include "reg_helper.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+ hws->ctx
+#define REG(reg)\
+ hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+ hws->shifts->field_name, hws->masks->field_name
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h
new file mode 100644
index 000000000000..aa3df3f77108
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h
@@ -0,0 +1,32 @@
+/*
+* Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN301_H__
+#define __DC_HWSS_DCN301_H__
+
+#include "hw_sequencer_private.h"
+
+
+#endif /* __DC_HWSS_DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
new file mode 100644
index 000000000000..d4bebb3a52e4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn301_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn301_funcs = {
+ .program_gamut_remap = dcn10_program_gamut_remap,
+ .init_hw = dcn10_init_hw,
+ .power_down_on_boot = dcn10_power_down_on_boot,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = NULL,
+ .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .disconnect_pipes = dcn10_disconnect_pipes,
+ .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+ .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+ .update_plane_addr = dcn20_update_plane_addr,
+ .update_dchub = dcn10_update_dchub,
+ .update_pending_status = dcn10_update_pending_status,
+ .program_output_csc = dcn20_program_output_csc,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+ .update_info_frame = dcn30_update_info_frame,
+ .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+ .enable_stream = dcn20_enable_stream,
+ .disable_stream = dce110_disable_stream,
+ .unblank_stream = dcn20_unblank_stream,
+#ifdef FREESYNC_POWER_OPTIMIZE
+ .are_streams_coarse_grain_aligned = dcn20_are_streams_coarse_grain_aligned,
+#endif
+ .blank_stream = dce110_blank_stream,
+ .enable_audio_stream = dce110_enable_audio_stream,
+ .disable_audio_stream = dce110_disable_audio_stream,
+ .disable_plane = dcn20_disable_plane,
+ .pipe_control_lock = dcn20_pipe_control_lock,
+ .interdependent_update_lock = dcn10_lock_all_pipes,
+ .cursor_lock = dcn10_cursor_lock,
+ .prepare_bandwidth = dcn20_prepare_bandwidth,
+ .optimize_bandwidth = dcn20_optimize_bandwidth,
+ .update_bandwidth = dcn20_update_bandwidth,
+ .set_drr = dcn10_set_drr,
+ .get_position = dcn10_get_position,
+ .set_static_screen_control = dcn10_set_static_screen_control,
+ .setup_stereo = dcn10_setup_stereo,
+ .set_avmute = dcn30_set_avmute,
+ .log_hw_state = dcn10_log_hw_state,
+ .get_hw_state = dcn10_get_hw_state,
+ .clear_status_bits = dcn10_clear_status_bits,
+ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_power_control = dce110_edp_power_control,
+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .set_cursor_position = dcn10_set_cursor_position,
+ .set_cursor_attribute = dcn10_set_cursor_attribute,
+ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+ .set_clock = dcn10_set_clock,
+ .get_clock = dcn10_get_clock,
+ .program_triplebuffer = dcn20_program_triple_buffer,
+ .enable_writeback = dcn30_enable_writeback,
+ .disable_writeback = dcn30_disable_writeback,
+ .update_writeback = dcn30_update_writeback,
+ .mmhubbub_warmup = dcn30_mmhubbub_warmup,
+ .dmdata_status_done = dcn20_dmdata_status_done,
+ .program_dmdata_engine = dcn30_program_dmdata_engine,
+ .set_dmdata_attributes = dcn20_set_dmdata_attributes,
+ .init_sys_ctx = dcn20_init_sys_ctx,
+ .init_vm_ctx = dcn20_init_vm_ctx,
+ .set_flip_control_gsl = dcn20_set_flip_control_gsl,
+ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ .calc_vupdate_position = dcn10_calc_vupdate_position,
+ .set_backlight_level = dcn21_set_backlight_level,
+ .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+ .set_pipe = dcn21_set_pipe,
+};
+
+static const struct hwseq_private_funcs dcn301_private_funcs = {
+ .init_pipes = dcn10_init_pipes,
+ .update_plane_addr = dcn20_update_plane_addr,
+ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+ .update_mpcc = dcn20_update_mpcc,
+ .set_input_transfer_func = dcn30_set_input_transfer_func,
+ .set_output_transfer_func = dcn30_set_output_transfer_func,
+ .power_down = dce110_power_down,
+ .enable_display_power_gating = dcn10_dummy_display_power_gating,
+ .blank_pixel_data = dcn20_blank_pixel_data,
+ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+ .enable_stream_timing = dcn20_enable_stream_timing,
+ .edp_backlight_control = dce110_edp_backlight_control,
+ .disable_stream_gating = dcn20_disable_stream_gating,
+ .enable_stream_gating = dcn20_enable_stream_gating,
+ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ .did_underflow_occur = dcn10_did_underflow_occur,
+ .init_blank = dcn20_init_blank,
+ .disable_vga = dcn20_disable_vga,
+ .bios_golden_init = dcn10_bios_golden_init,
+ .plane_atomic_disable = dcn20_plane_atomic_disable,
+ .plane_atomic_power_down = dcn10_plane_atomic_power_down,
+ .enable_power_gating_plane = dcn20_enable_power_gating_plane,
+ .dpp_pg_control = dcn20_dpp_pg_control,
+ .hubp_pg_control = dcn20_hubp_pg_control,
+ .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+ .update_odm = dcn20_update_odm,
+ .dsc_pg_control = dcn20_dsc_pg_control,
+ .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
+ .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
+ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
+ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+ .wait_for_blank_complete = dcn20_wait_for_blank_complete,
+ .dccg_init = dcn20_dccg_init,
+ .set_blend_lut = dcn30_set_blend_lut,
+ .set_shaper_3dlut = dcn20_set_shaper_3dlut,
+};
+
+void dcn301_hw_sequencer_construct(struct dc *dc)
+{
+ dc->hwss = dcn301_funcs;
+ dc->hwseq->funcs = dcn301_private_funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h
new file mode 100644
index 000000000000..0bca48ccbfa2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN30_INIT_H__
+#define __DC_DCN30_INIT_H__
+
+struct dc;
+
+void dcn301_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN30_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
new file mode 100644
index 000000000000..736bda30abc3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
+#include "dcn301_panel_cntl.h"
+#include "atom.h"
+
+#define TO_DCN301_PANEL_CNTL(panel_cntl)\
+ container_of(panel_cntl, struct dcn301_panel_cntl, base)
+
+#define CTX \
+ dcn301_panel_cntl->base.ctx
+
+#define DC_LOGGER \
+ dcn301_panel_cntl->base.ctx->logger
+
+#define REG(reg)\
+ dcn301_panel_cntl->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+ dcn301_panel_cntl->shift->field_name, dcn301_panel_cntl->mask->field_name
+
+static unsigned int dcn301_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
+{
+ uint64_t current_backlight;
+ uint32_t round_result;
+ uint32_t bl_period, bl_int_count;
+ uint32_t bl_pwm, fractional_duty_cycle_en;
+ uint32_t bl_period_mask, bl_pwm_mask;
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+
+ REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
+ REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
+
+ REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm);
+ REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
+
+ if (bl_int_count == 0)
+ bl_int_count = 16;
+
+ bl_period_mask = (1 << bl_int_count) - 1;
+ bl_period &= bl_period_mask;
+
+ bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
+
+ if (fractional_duty_cycle_en == 0)
+ bl_pwm &= bl_pwm_mask;
+ else
+ bl_pwm &= 0xFFFF;
+
+ current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
+
+ if (bl_period == 0)
+ bl_period = 0xFFFF;
+
+ current_backlight = div_u64(current_backlight, bl_period);
+ current_backlight = (current_backlight + 1) >> 1;
+
+ current_backlight = (uint64_t)(current_backlight) * bl_period;
+
+ round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
+
+ round_result = (round_result >> (bl_int_count-1)) & 1;
+
+ current_backlight >>= bl_int_count;
+ current_backlight += round_result;
+
+ return (uint32_t)(current_backlight);
+}
+
+uint32_t dcn301_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
+{
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+ uint32_t value;
+ uint32_t current_backlight;
+
+ /* It must not be 0, so we have to restore them
+ * Bios bug w/a - period resets to zero,
+ * restoring to cache values which is always correct
+ */
+ REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
+
+ if (value == 0 || value == 1) {
+ if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
+ REG_WRITE(BL_PWM_CNTL,
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
+ REG_WRITE(BL_PWM_CNTL2,
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
+ REG_WRITE(BL_PWM_PERIOD_CNTL,
+ panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
+ REG_UPDATE(PWRSEQ_REF_DIV,
+ BL_PWM_REF_DIV,
+ panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+ } else {
+ /* TODO: Note: This should not really happen since VBIOS
+ * should have initialized PWM registers on boot.
+ */
+ REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
+ REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
+ }
+ } else {
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
+ REG_READ(BL_PWM_CNTL);
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
+ REG_READ(BL_PWM_CNTL2);
+ panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+ REG_READ(BL_PWM_PERIOD_CNTL);
+
+ REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
+ &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+ }
+
+ // Enable the backlight output
+ REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
+
+ // Unlock group 2 backlight registers
+ REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
+ BL_PWM_GRP1_REG_LOCK, 0);
+
+ current_backlight = dcn301_get_16_bit_backlight_from_pwm(panel_cntl);
+
+ return current_backlight;
+}
+
+void dcn301_panel_cntl_destroy(struct panel_cntl **panel_cntl)
+{
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(*panel_cntl);
+
+ kfree(dcn301_panel_cntl);
+ *panel_cntl = NULL;
+}
+
+bool dcn301_is_panel_backlight_on(struct panel_cntl *panel_cntl)
+{
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+ uint32_t value;
+
+ REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value);
+
+ return value;
+}
+
+bool dcn301_is_panel_powered_on(struct panel_cntl *panel_cntl)
+{
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+ uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
+
+ REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
+
+ REG_GET_2(PWRSEQ_CNTL, PANEL_DIGON, &dig_on, PANEL_DIGON_OVRD, &dig_on_ovrd);
+
+ return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
+}
+
+void dcn301_store_backlight_level(struct panel_cntl *panel_cntl)
+{
+ struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
+ REG_READ(BL_PWM_CNTL);
+ panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
+ REG_READ(BL_PWM_CNTL2);
+ panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+ REG_READ(BL_PWM_PERIOD_CNTL);
+
+ REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
+ &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+}
+
+static const struct panel_cntl_funcs dcn301_link_panel_cntl_funcs = {
+ .destroy = dcn301_panel_cntl_destroy,
+ .hw_init = dcn301_panel_cntl_hw_init,
+ .is_panel_backlight_on = dcn301_is_panel_backlight_on,
+ .is_panel_powered_on = dcn301_is_panel_powered_on,
+ .store_backlight_level = dcn301_store_backlight_level,
+ .get_current_backlight = dcn301_get_16_bit_backlight_from_pwm,
+};
+
+void dcn301_panel_cntl_construct(
+ struct dcn301_panel_cntl *dcn301_panel_cntl,
+ const struct panel_cntl_init_data *init_data,
+ const struct dce_panel_cntl_registers *regs,
+ const struct dcn301_panel_cntl_shift *shift,
+ const struct dcn301_panel_cntl_mask *mask)
+{
+ dcn301_panel_cntl->regs = regs;
+ dcn301_panel_cntl->shift = shift;
+ dcn301_panel_cntl->mask = mask;
+
+ dcn301_panel_cntl->base.funcs = &dcn301_link_panel_cntl_funcs;
+ dcn301_panel_cntl->base.ctx = init_data->ctx;
+ dcn301_panel_cntl->base.inst = init_data->inst;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h
new file mode 100644
index 000000000000..ffc875da7467
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_PANEL_CNTL__DCN301_H__
+#define __DC_PANEL_CNTL__DCN301_H__
+
+#include "panel_cntl.h"
+#include "dce/dce_panel_cntl.h"
+
+
+#define DCN301_PANEL_CNTL_REG_LIST(id)\
+ SRIR(PWRSEQ_CNTL, CNTL, PANEL_PWRSEQ, id), \
+ SRIR(PWRSEQ_STATE, STATE, PANEL_PWRSEQ, id), \
+ SRIR(PWRSEQ_REF_DIV, REF_DIV, PANEL_PWRSEQ, id), \
+ SRIR(BL_PWM_CNTL, CNTL, BL_PWM, id), \
+ SRIR(BL_PWM_CNTL2, CNTL2, BL_PWM, id), \
+ SRIR(BL_PWM_PERIOD_CNTL, PERIOD_CNTL, BL_PWM, id), \
+ SRIR(BL_PWM_GRP1_REG_LOCK, GRP1_REG_LOCK, BL_PWM, id)
+
+#define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define DCN301_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
+ DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
+ DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
+ DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
+ DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh), \
+ DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_EN, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
+ DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
+
+#define DCN301_PANEL_CNTL_REG_FIELD_LIST(type) \
+ type PANEL_BLON;\
+ type PANEL_DIGON;\
+ type PANEL_DIGON_OVRD;\
+ type PANEL_PWRSEQ_TARGET_STATE_R; \
+ type BL_PWM_EN; \
+ type BL_ACTIVE_INT_FRAC_CNT; \
+ type BL_PWM_FRACTIONAL_EN; \
+ type BL_PWM_PERIOD; \
+ type BL_PWM_PERIOD_BITCNT; \
+ type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
+ type BL_PWM_GRP1_REG_LOCK; \
+ type BL_PWM_GRP1_REG_UPDATE_PENDING; \
+ type BL_PWM_REF_DIV
+
+struct dcn301_panel_cntl_shift {
+ DCN301_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn301_panel_cntl_mask {
+ DCN301_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn301_panel_cntl {
+ struct panel_cntl base;
+ const struct dce_panel_cntl_registers *regs;
+ const struct dcn301_panel_cntl_shift *shift;
+ const struct dcn301_panel_cntl_mask *mask;
+};
+
+void dcn301_panel_cntl_construct(
+ struct dcn301_panel_cntl *panel_cntl,
+ const struct panel_cntl_init_data *init_data,
+ const struct dce_panel_cntl_registers *regs,
+ const struct dcn301_panel_cntl_shift *shift,
+ const struct dcn301_panel_cntl_mask *mask);
+
+#endif /* __DC_PANEL_CNTL__DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
new file mode 100644
index 000000000000..9f0ca41ef1b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -0,0 +1,2011 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn301_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn30/dcn30_resource.h"
+#include "dcn301_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn301/dcn301_hubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_hubp.h"
+#include "irq/dcn30/irq_service_dcn30.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn30/dcn30_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dce110/dce110_resource.h"
+#include "dml/display_mode_vba.h"
+#include "dcn301/dcn301_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn301/dcn301_dio_link_encoder.h"
+#include "dcn301_panel_cntl.h"
+
+#include "vangogh_ip_offset.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+#include "dcn/dcn_3_0_1_offset.h"
+#include "dcn/dcn_3_0_1_sh_mask.h"
+
+#include "nbio/nbio_7_2_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+#include "amdgpu_socbb.h"
+
+#define TO_DCN301_RES_POOL(pool)\
+ container_of(pool, struct dcn301_resource_pool, base)
+
+#define DC_LOGGER_INIT(logger)
+
+struct _vcs_dpi_ip_params_st dcn3_01_ip = {
+ .odm_capable = 1,
+ .gpuvm_enable = 1,
+ .hostvm_enable = 1,
+ .gpuvm_max_page_table_levels = 1,
+ .hostvm_max_page_table_levels = 2,
+ .hostvm_cached_page_table_levels = 0,
+ .pte_group_size_bytes = 2048,
+ .num_dsc = 3,
+ .rob_buffer_size_kbytes = 184,
+ .det_buffer_size_kbytes = 184,
+ .dpte_buffer_size_in_pte_reqs_luma = 64,
+ .dpte_buffer_size_in_pte_reqs_chroma = 32,
+ .pde_proc_buffer_size_64k_reqs = 48,
+ .dpp_output_buffer_pixels = 2560,
+ .opp_output_buffer_lines = 1,
+ .pixel_chunk_size_kbytes = 8,
+ .meta_chunk_size_kbytes = 2,
+ .writeback_chunk_size_kbytes = 8,
+ .line_buffer_size_bits = 789504,
+ .is_line_buffer_bpp_fixed = 0, // ?
+ .line_buffer_fixed_bpp = 48, // ?
+ .dcc_supported = true,
+ .writeback_interface_buffer_size_kbytes = 90,
+ .writeback_line_buffer_buffer_size = 656640,
+ .max_line_buffer_lines = 12,
+ .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640
+ .writeback_chroma_buffer_size_kbytes = 8,
+ .writeback_chroma_line_buffer_width_pixels = 4,
+ .writeback_max_hscl_ratio = 1,
+ .writeback_max_vscl_ratio = 1,
+ .writeback_min_hscl_ratio = 1,
+ .writeback_min_vscl_ratio = 1,
+ .writeback_max_hscl_taps = 1,
+ .writeback_max_vscl_taps = 1,
+ .writeback_line_buffer_luma_buffer_size = 0,
+ .writeback_line_buffer_chroma_buffer_size = 14643,
+ .cursor_buffer_size = 8,
+ .cursor_chunk_size = 2,
+ .max_num_otg = 4,
+ .max_num_dpp = 4,
+ .max_num_wb = 1,
+ .max_dchub_pscl_bw_pix_per_clk = 4,
+ .max_pscl_lb_bw_pix_per_clk = 2,
+ .max_lb_vscl_bw_pix_per_clk = 4,
+ .max_vscl_hscl_bw_pix_per_clk = 4,
+ .max_hscl_ratio = 6,
+ .max_vscl_ratio = 6,
+ .hscl_mults = 4,
+ .vscl_mults = 4,
+ .max_hscl_taps = 8,
+ .max_vscl_taps = 8,
+ .dispclk_ramp_margin_percent = 1,
+ .underscan_factor = 1.11,
+ .min_vblank_lines = 32,
+ .dppclk_delay_subtotal = 46,
+ .dynamic_metadata_vm_enabled = true,
+ .dppclk_delay_scl_lb_only = 16,
+ .dppclk_delay_scl = 50,
+ .dppclk_delay_cnvc_formatter = 27,
+ .dppclk_delay_cnvc_cursor = 6,
+ .dispclk_delay_subtotal = 119,
+ .dcfclk_cstate_latency = 5.2, // SRExitTime
+ .max_inter_dcn_tile_repeaters = 8,
+ .max_num_hdmi_frl_outputs = 0,
+ .odm_combine_4to1_supported = true,
+
+ .xfc_supported = false,
+ .xfc_fill_bw_overhead_percent = 10.0,
+ .xfc_fill_constant_bytes = 0,
+ .gfx7_compat_tiling_supported = 0,
+ .number_of_cursors = 1,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
+ .clock_limits = {
+ /*TODO: fill out defaults once wm plociy is settled*/
+ {
+ .state = 0,
+ .dcfclk_mhz = 810.0,
+ .fabricclk_mhz = 1200.0,
+ .dispclk_mhz = 1015.0,
+ .dppclk_mhz = 1015.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 1000.0,
+ .dscclk_mhz = 338.0,
+ .dram_speed_mts = 4266.0,
+ },
+ {
+ .state = 1,
+ .dcfclk_mhz = 810.0,
+ .fabricclk_mhz = 1200.0,
+ .dispclk_mhz = 1015.0,
+ .dppclk_mhz = 1015.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 1000.0,
+ .dscclk_mhz = 338.0,
+ .dram_speed_mts = 4266.0,
+ }
+ },
+
+ .sr_exit_time_us = 9.0,
+ .sr_enter_plus_exit_time_us = 11.0,
+ .urgent_latency_us = 4.0,
+ .urgent_latency_pixel_data_only_us = 4.0,
+ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+ .urgent_latency_vm_data_only_us = 4.0,
+ .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+ .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+ .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
+ .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
+ .max_avg_sdp_bw_use_normal_percent = 60.0,
+ .max_avg_dram_bw_use_normal_percent = 60.0,
+ .writeback_latency_us = 12.0,
+ .max_request_size_bytes = 256,
+ .dram_channel_width_bytes = 4,
+ .fabric_datapath_to_dcn_data_return_bytes = 32,
+ .dcn_downspread_percent = 0.5,
+ .downspread_percent = 0.38,
+ .dram_page_open_time_ns = 50.0,
+ .dram_rw_turnaround_time_ns = 17.5,
+ .dram_return_buffer_per_channel_bytes = 8192,
+ .round_trip_ping_latency_dcfclk_cycles = 191,
+ .urgent_out_of_order_return_per_channel_bytes = 4096,
+ .channel_interleave_bytes = 256,
+ .num_banks = 8,
+ .num_chans = 4,
+ .gpuvm_min_page_size_bytes = 4096,
+ .hostvm_min_page_size_bytes = 4096,
+ .dram_clock_change_latency_us = 23.84,
+ .writeback_dram_clock_change_latency_us = 23.0,
+ .return_bus_width_bytes = 64,
+ .dispclk_dppclk_vco_speed_mhz = 3550,
+ .xfc_bus_transport_time_us = 20, // ?
+ .xfc_xbuf_latency_tolerance_us = 4, // ?
+ .use_urgent_burst_bw = 1, // ?
+ .num_states = 2,
+ .do_urgent_latency_adjustment = false,
+ .urgent_latency_adjustment_fabric_clock_component_us = 0,
+ .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
+};
+
+enum dcn301_clk_src_array_id {
+ DCN301_CLK_SRC_PLL0,
+ DCN301_CLK_SRC_PLL1,
+ DCN301_CLK_SRC_PLL2,
+ DCN301_CLK_SRC_PLL3,
+ DCN301_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+ .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+ .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \
+ ## id ## _ ## reg_name_post ## _BASE_IDX) + \
+ mm ## reg_name_pre ## id ## _ ## reg_name_post
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+ .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+ .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+ .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+ .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+ mm ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+ NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+ NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+ .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+ regBIF_BX0_ ## reg_name
+
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+ MMHUB_BASE__INST0_SEG ## seg
+
+#define MMHUB_BASE(seg) \
+ MMHUB_BASE_INNER(seg)
+
+#define MMHUB_SR(reg_name)\
+ .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
+ regMM ## reg_name
+
+/* CLOCK */
+#define CLK_BASE_INNER(seg) \
+ CLK_BASE__INST0_SEG ## seg
+
+#define CLK_BASE(seg) \
+ CLK_BASE_INNER(seg)
+
+#define CLK_SRI(reg_name, block, inst)\
+ .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## _ ## inst ## _ ## reg_name
+
+static const struct bios_registers bios_regs = {
+ NBIO_SR(BIOS_SCRATCH_3),
+ NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+ CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+ clk_src_regs(0, A),
+ clk_src_regs(1, B),
+ clk_src_regs(2, C),
+ clk_src_regs(3, D)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+ CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+ CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+ ABM_DCN301_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+ abm_regs(0),
+ abm_regs(1),
+ abm_regs(2),
+ abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+ ABM_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCN301(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+ AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+ audio_regs(0),
+ audio_regs(1),
+ audio_regs(2),
+ audio_regs(3),
+ audio_regs(4),
+ audio_regs(5),
+ audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+ AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+ DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+ DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+ VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+ vpg_regs(0),
+ vpg_regs(1),
+ vpg_regs(2),
+ vpg_regs(3),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+ DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+ DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+ AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+ afmt_regs(0),
+ afmt_regs(1),
+ afmt_regs(2),
+ afmt_regs(3),
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+ DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+ DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+ SE_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+ stream_enc_regs(0),
+ stream_enc_regs(1),
+ stream_enc_regs(2),
+ stream_enc_regs(3),
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+ DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+ aux_regs(0),
+ aux_regs(1),
+ aux_regs(2),
+ aux_regs(3),
+};
+
+#define hpd_regs(id)\
+[id] = {\
+ HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+ hpd_regs(0),
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+ LE_DCN301_REG_LIST(id), \
+ UNIPHY_DCN2_REG_LIST(phyid), \
+}
+
+static const struct dce110_aux_registers_shift aux_shift = {
+ DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+ DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+ link_regs(0, A),
+ link_regs(1, B),
+ link_regs(2, C),
+ link_regs(3, D),
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+ LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+ LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK)
+};
+
+#define panel_cntl_regs(id)\
+[id] = {\
+ DCN301_PANEL_CNTL_REG_LIST(id),\
+}
+
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
+ panel_cntl_regs(0),
+ panel_cntl_regs(1),
+};
+
+static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
+ DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
+ DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+ DPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+ dpp_regs(0),
+ dpp_regs(1),
+ dpp_regs(2),
+ dpp_regs(3),
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+ DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+ DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+ OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+ opp_regs(0),
+ opp_regs(1),
+ opp_regs(2),
+ opp_regs(3),
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+ OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+ OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+ AUX_COMMON_REG_LIST0(id), \
+ .AUXN_IMPCAL = 0, \
+ .AUXP_IMPCAL = 0, \
+ .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+ aux_engine_regs(0),
+ aux_engine_regs(1),
+ aux_engine_regs(2),
+ aux_engine_regs(3),
+};
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+ DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+ dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+ DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+ DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+ MCIF_WB_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+ mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+ DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+ dsc_regsDCN20(0),
+ dsc_regsDCN20(1),
+ dsc_regsDCN20(2),
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+ DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+ DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+ MPC_REG_LIST_DCN3_0(0),
+ MPC_REG_LIST_DCN3_0(1),
+ MPC_REG_LIST_DCN3_0(2),
+ MPC_REG_LIST_DCN3_0(3),
+ MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+ MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+ MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+ MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+ MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+ MPC_RMU_REG_LIST_DCN3AG(0),
+ MPC_RMU_REG_LIST_DCN3AG(1),
+ MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+ MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+ MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
+
+
+static const struct dcn_optc_registers optc_regs[] = {
+ optc_regs(0),
+ optc_regs(1),
+ optc_regs(2),
+ optc_regs(3),
+};
+
+static const struct dcn_optc_shift optc_shift = {
+ OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+ OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+ HUBP_REG_LIST_DCN30(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+ hubp_regs(0),
+ hubp_regs(1),
+ hubp_regs(2),
+ hubp_regs(3),
+};
+
+static const struct dcn_hubp2_shift hubp_shift = {
+ HUBP_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+ HUBP_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+ HUBBUB_REG_LIST_DCN301(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+ HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+ HUBBUB_MASK_SH_LIST_DCN301(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+ DCCG_REG_LIST_DCN301()
+};
+
+static const struct dccg_shift dccg_shift = {
+ DCCG_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+ DCCG_MASK_SH_LIST_DCN301(_MASK)
+};
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_DCN301_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_DCN301_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+ DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+ vmid_regs(0),
+ vmid_regs(1),
+ vmid_regs(2),
+ vmid_regs(3),
+ vmid_regs(4),
+ vmid_regs(5),
+ vmid_regs(6),
+ vmid_regs(7),
+ vmid_regs(8),
+ vmid_regs(9),
+ vmid_regs(10),
+ vmid_regs(11),
+ vmid_regs(12),
+ vmid_regs(13),
+ vmid_regs(14),
+ vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+ DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+ DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn301 = {
+ .num_timing_generator = 4,
+ .num_opp = 4,
+ .num_video_plane = 4,
+ .num_audio = 4,
+ .num_stream_encoder = 4,
+ .num_pll = 4,
+ .num_dwb = 1,
+ .num_ddc = 4,
+ .num_vmid = 16,
+ .num_mpc_3dlut = 2,
+ .num_dsc = 3,
+};
+
+static const struct dc_plane_cap plane_cap = {
+ .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+ .blends_with_above = true,
+ .blends_with_below = true,
+ .per_pixel_alpha = true,
+
+ .pixel_format_support = {
+ .argb8888 = true,
+ .nv12 = true,
+ .fp16 = true,
+ .p010 = false,
+ .ayuv = false,
+ },
+
+ .max_upscale_factor = {
+ .argb8888 = 16000,
+ .nv12 = 16000,
+ .fp16 = 16000
+ },
+
+ .max_downscale_factor = {
+ .argb8888 = 600,
+ .nv12 = 600,
+ .fp16 = 600
+ },
+ 64,
+ 64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+ .disable_dmcu = true,
+ .force_abm_enable = false,
+ .timing_trace = false,
+ .clock_trace = true,
+ .disable_dpp_power_gate = true,
+ .disable_hubp_power_gate = true,
+ .disable_clock_gate = true,
+ .disable_pplib_clock_request = true,
+ .disable_pplib_wm_range = true,
+ .disable_stutter = true,
+ .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+ .force_single_disp_pipe_split = false,
+ .disable_dcc = DCC_ENABLE,
+ .vsr_support = true,
+ .performance_trace = false,
+ .max_downscale_src_width = 7680,/*upto 8K*/
+ .scl_reset_length10 = true,
+ .sanity_checks = false,
+ .underflow_assert_delay_us = 0xFFFFFFFF,
+ .dwb_fi_phase = -1, // -1 = disable
+ .dmub_command_table = true,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+ .disable_dmcu = true,
+ .force_abm_enable = false,
+ .timing_trace = true,
+ .clock_trace = true,
+ .disable_dpp_power_gate = true,
+ .disable_hubp_power_gate = true,
+ .disable_clock_gate = true,
+ .disable_pplib_clock_request = true,
+ .disable_pplib_wm_range = true,
+ .disable_stutter = true,
+ .scl_reset_length10 = true,
+ .dwb_fi_phase = -1, // -1 = disable
+ .dmub_command_table = true,
+};
+
+void dcn301_dpp_destroy(struct dpp **dpp)
+{
+ kfree(TO_DCN20_DPP(*dpp));
+ *dpp = NULL;
+}
+
+struct dpp *dcn301_dpp_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn3_dpp *dpp =
+ kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+ if (!dpp)
+ return NULL;
+
+ if (dpp3_construct(dpp, ctx, inst,
+ &dpp_regs[inst], &tf_shift, &tf_mask))
+ return &dpp->base;
+
+ BREAK_TO_DEBUGGER();
+ kfree(dpp);
+ return NULL;
+}
+struct output_pixel_processor *dcn301_opp_create(
+ struct dc_context *ctx, uint32_t inst)
+{
+ struct dcn20_opp *opp =
+ kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+ if (!opp) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dcn20_opp_construct(opp, ctx, inst,
+ &opp_regs[inst], &opp_shift, &opp_mask);
+ return &opp->base;
+}
+
+struct dce_aux *dcn301_aux_engine_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct aux_engine_dce110 *aux_engine =
+ kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+ if (!aux_engine)
+ return NULL;
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+ &aux_shift,
+ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+ i2c_inst_regs(1),
+ i2c_inst_regs(2),
+ i2c_inst_regs(3),
+ i2c_inst_regs(4),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+ I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+ I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+};
+
+struct dce_i2c_hw *dcn301_i2c_hw_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dce_i2c_hw *dce_i2c_hw =
+ kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+ if (!dce_i2c_hw)
+ return NULL;
+
+ dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+ &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+ return dce_i2c_hw;
+}
+static struct mpc *dcn301_mpc_create(
+ struct dc_context *ctx,
+ int num_mpcc,
+ int num_rmu)
+{
+ struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+ GFP_KERNEL);
+
+ if (!mpc30)
+ return NULL;
+
+ dcn30_mpc_construct(mpc30, ctx,
+ &mpc_regs,
+ &mpc_shift,
+ &mpc_mask,
+ num_mpcc,
+ num_rmu);
+
+ return &mpc30->base;
+}
+
+struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
+{
+ int i;
+
+ struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
+ GFP_KERNEL);
+
+ if (!hubbub3)
+ return NULL;
+
+ hubbub301_construct(hubbub3, ctx,
+ &hubbub_reg,
+ &hubbub_shift,
+ &hubbub_mask);
+
+
+ for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
+ struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+ vmid->ctx = ctx;
+
+ vmid->regs = &vmid_regs[i];
+ vmid->shifts = &vmid_shifts;
+ vmid->masks = &vmid_masks;
+ }
+
+ hubbub3->num_vmid = res_cap_dcn301.num_vmid;
+
+ return &hubbub3->base;
+}
+
+struct timing_generator *dcn301_timing_generator_create(
+ struct dc_context *ctx,
+ uint32_t instance)
+{
+ struct optc *tgn10 =
+ kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+ if (!tgn10)
+ return NULL;
+
+ tgn10->base.inst = instance;
+ tgn10->base.ctx = ctx;
+
+ tgn10->tg_regs = &optc_regs[instance];
+ tgn10->tg_shift = &optc_shift;
+ tgn10->tg_mask = &optc_mask;
+
+ dcn30_timing_generator_init(tgn10);
+
+ return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+ .max_hdmi_deep_color = COLOR_DEPTH_121212,
+ .max_hdmi_pixel_clock = 600000,
+ .hdmi_ycbcr420_supported = true,
+ .dp_ycbcr420_supported = true,
+ .fec_supported = true,
+ .flags.bits.IS_HBR2_CAPABLE = true,
+ .flags.bits.IS_HBR3_CAPABLE = true,
+ .flags.bits.IS_TPS3_CAPABLE = true,
+ .flags.bits.IS_TPS4_CAPABLE = true
+};
+
+struct link_encoder *dcn301_link_encoder_create(
+ const struct encoder_init_data *enc_init_data)
+{
+ struct dcn20_link_encoder *enc20 =
+ kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+ if (!enc20)
+ return NULL;
+
+ dcn301_link_encoder_construct(enc20,
+ enc_init_data,
+ &link_enc_feature,
+ &link_enc_regs[enc_init_data->transmitter],
+ &link_enc_aux_regs[enc_init_data->channel - 1],
+ &link_enc_hpd_regs[enc_init_data->hpd_source],
+ &le_shift,
+ &le_mask);
+
+ return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+ struct dcn301_panel_cntl *panel_cntl =
+ kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
+
+ if (!panel_cntl)
+ return NULL;
+
+ dcn301_panel_cntl_construct(panel_cntl,
+ init_data,
+ &panel_cntl_regs[init_data->inst],
+ &panel_cntl_shift,
+ &panel_cntl_mask);
+
+ return &panel_cntl->base;
+}
+
+
+#define CTX ctx
+
+#define REG(reg_name) \
+ (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+ uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+ /* RV1 support max 4 pipes */
+ value = value & 0xf;
+ return value;
+}
+
+
+static void read_dce_straps(
+ struct dc_context *ctx,
+ struct resource_straps *straps)
+{
+ generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
+ FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn301_create_audio(
+ struct dc_context *ctx, unsigned int inst)
+{
+ return dce_audio_create(ctx, inst,
+ &audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn301_vpg_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+ if (!vpg3)
+ return NULL;
+
+ vpg3_construct(vpg3, ctx, inst,
+ &vpg_regs[inst],
+ &vpg_shift,
+ &vpg_mask);
+
+ return &vpg3->base;
+}
+
+static struct afmt *dcn301_afmt_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+ if (!afmt3)
+ return NULL;
+
+ afmt3_construct(afmt3, ctx, inst,
+ &afmt_regs[inst],
+ &afmt_shift,
+ &afmt_mask);
+
+ return &afmt3->base;
+}
+
+struct stream_encoder *dcn301_stream_encoder_create(
+ enum engine_id eng_id,
+ struct dc_context *ctx)
+{
+ struct dcn10_stream_encoder *enc1;
+ struct vpg *vpg;
+ struct afmt *afmt;
+ int vpg_inst;
+ int afmt_inst;
+
+ /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+ if (eng_id <= ENGINE_ID_DIGF) {
+ vpg_inst = eng_id;
+ afmt_inst = eng_id;
+ } else
+ return NULL;
+
+ enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+ vpg = dcn301_vpg_create(ctx, vpg_inst);
+ afmt = dcn301_afmt_create(ctx, afmt_inst);
+
+ if (!enc1 || !vpg || !afmt)
+ return NULL;
+
+ dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+ eng_id, vpg, afmt,
+ &stream_enc_regs[eng_id],
+ &se_shift, &se_mask);
+
+ return &enc1->base;
+}
+
+struct dce_hwseq *dcn301_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+ .read_dce_straps = read_dce_straps,
+ .create_audio = dcn301_create_audio,
+ .create_stream_encoder = dcn301_stream_encoder_create,
+ .create_hwseq = dcn301_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+ .read_dce_straps = NULL,
+ .create_audio = NULL,
+ .create_stream_encoder = NULL,
+ .create_hwseq = dcn301_hwseq_create,
+};
+
+static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+
+static void dcn301_destruct(struct dcn301_resource_pool *pool)
+{
+ unsigned int i;
+
+ for (i = 0; i < pool->base.stream_enc_count; i++) {
+ if (pool->base.stream_enc[i] != NULL) {
+ if (pool->base.stream_enc[i]->vpg != NULL) {
+ kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+ pool->base.stream_enc[i]->vpg = NULL;
+ }
+ if (pool->base.stream_enc[i]->afmt != NULL) {
+ kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+ pool->base.stream_enc[i]->afmt = NULL;
+ }
+ kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+ pool->base.stream_enc[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ if (pool->base.dscs[i] != NULL)
+ dcn20_dsc_destroy(&pool->base.dscs[i]);
+ }
+
+ if (pool->base.mpc != NULL) {
+ kfree(TO_DCN20_MPC(pool->base.mpc));
+ pool->base.mpc = NULL;
+ }
+ if (pool->base.hubbub != NULL) {
+ kfree(pool->base.hubbub);
+ pool->base.hubbub = NULL;
+ }
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ if (pool->base.dpps[i] != NULL)
+ dcn301_dpp_destroy(&pool->base.dpps[i]);
+
+ if (pool->base.ipps[i] != NULL)
+ pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+ if (pool->base.hubps[i] != NULL) {
+ kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+ pool->base.hubps[i] = NULL;
+ }
+
+ if (pool->base.irqs != NULL) {
+ dal_irq_service_destroy(&pool->base.irqs);
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ if (pool->base.engines[i] != NULL)
+ dce110_engine_destroy(&pool->base.engines[i]);
+ if (pool->base.hw_i2cs[i] != NULL) {
+ kfree(pool->base.hw_i2cs[i]);
+ pool->base.hw_i2cs[i] = NULL;
+ }
+ if (pool->base.sw_i2cs[i] != NULL) {
+ kfree(pool->base.sw_i2cs[i]);
+ pool->base.sw_i2cs[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ if (pool->base.opps[i] != NULL)
+ pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ if (pool->base.timing_generators[i] != NULL) {
+ kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+ pool->base.timing_generators[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ if (pool->base.dwbc[i] != NULL) {
+ kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+ pool->base.dwbc[i] = NULL;
+ }
+ if (pool->base.mcif_wb[i] != NULL) {
+ kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+ pool->base.mcif_wb[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.audio_count; i++) {
+ if (pool->base.audios[i])
+ dce_aud_destroy(&pool->base.audios[i]);
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] != NULL) {
+ dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+ pool->base.clock_sources[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ if (pool->base.mpc_lut[i] != NULL) {
+ dc_3dlut_func_release(pool->base.mpc_lut[i]);
+ pool->base.mpc_lut[i] = NULL;
+ }
+ if (pool->base.mpc_shaper[i] != NULL) {
+ dc_transfer_func_release(pool->base.mpc_shaper[i]);
+ pool->base.mpc_shaper[i] = NULL;
+ }
+ }
+
+ if (pool->base.dp_clock_source != NULL) {
+ dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+ pool->base.dp_clock_source = NULL;
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ if (pool->base.multiple_abms[i] != NULL)
+ dce_abm_destroy(&pool->base.multiple_abms[i]);
+ }
+
+ if (pool->base.dccg != NULL)
+ dcn_dccg_destroy(&pool->base.dccg);
+
+ if (pool->base.pp_smu != NULL)
+ dcn301_pp_smu_destroy(&pool->base.pp_smu);
+}
+
+struct hubp *dcn301_hubp_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn20_hubp *hubp2 =
+ kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+ if (!hubp2)
+ return NULL;
+
+ if (hubp3_construct(hubp2, ctx, inst,
+ &hubp_regs[inst], &hubp_shift, &hubp_mask))
+ return &hubp2->base;
+
+ BREAK_TO_DEBUGGER();
+ kfree(hubp2);
+ return NULL;
+}
+
+bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+ GFP_KERNEL);
+
+ if (!dwbc30) {
+ dm_error("DC: failed to create dwbc30!\n");
+ return false;
+ }
+
+ dcn30_dwbc_construct(dwbc30, ctx,
+ &dwbc30_regs[i],
+ &dwbc30_shift,
+ &dwbc30_mask,
+ i);
+
+ pool->dwbc[i] = &dwbc30->base;
+ }
+ return true;
+}
+
+bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+ GFP_KERNEL);
+
+ if (!mcif_wb30) {
+ dm_error("DC: failed to create mcif_wb30!\n");
+ return false;
+ }
+
+ dcn30_mmhubbub_construct(mcif_wb30, ctx,
+ &mcif_wb30_regs[i],
+ &mcif_wb30_shift,
+ &mcif_wb30_mask,
+ i);
+
+ pool->mcif_wb[i] = &mcif_wb30->base;
+ }
+ return true;
+}
+
+static struct display_stream_compressor *dcn301_dsc_create(
+ struct dc_context *ctx, uint32_t inst)
+{
+ struct dcn20_dsc *dsc =
+ kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+ if (!dsc) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+ return &dsc->base;
+}
+
+
+static void dcn301_destroy_resource_pool(struct resource_pool **pool)
+{
+ struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
+
+ dcn301_destruct(dcn301_pool);
+ kfree(dcn301_pool);
+ *pool = NULL;
+}
+
+static struct clock_source *dcn301_clock_source_create(
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ bool dp_clk_src)
+{
+ struct dce110_clk_src *clk_src =
+ kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+ if (!clk_src)
+ return NULL;
+
+ if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
+ regs, &cs_shift, &cs_mask)) {
+ clk_src->base.dp_clk_src = dp_clk_src;
+ return &clk_src->base;
+ }
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+static bool is_soc_bounding_box_valid(struct dc *dc)
+{
+ uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
+
+ if (ASICREV_IS_VANGOGH(hw_internal_rev))
+ return true;
+
+ return false;
+}
+
+static bool init_soc_bounding_box(struct dc *dc,
+ struct dcn301_resource_pool *pool)
+{
+ const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
+ struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
+ struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
+
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ if (!bb && !is_soc_bounding_box_valid(dc)) {
+ DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+ return false;
+ }
+
+ if (bb && !is_soc_bounding_box_valid(dc)) {
+ int i;
+
+ dcn3_01_soc.sr_exit_time_us =
+ fixed16_to_double_to_cpu(bb->sr_exit_time_us);
+ dcn3_01_soc.sr_enter_plus_exit_time_us =
+ fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
+ dcn3_01_soc.urgent_latency_us =
+ fixed16_to_double_to_cpu(bb->urgent_latency_us);
+ dcn3_01_soc.urgent_latency_pixel_data_only_us =
+ fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
+ dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us =
+ fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
+ dcn3_01_soc.urgent_latency_vm_data_only_us =
+ fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
+ dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
+ le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
+ dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
+ le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
+ dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
+ le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
+ dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
+ fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
+ dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
+ fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
+ dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
+ fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
+ dcn3_01_soc.max_avg_sdp_bw_use_normal_percent =
+ fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
+ dcn3_01_soc.max_avg_dram_bw_use_normal_percent =
+ fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
+ dcn3_01_soc.writeback_latency_us =
+ fixed16_to_double_to_cpu(bb->writeback_latency_us);
+ dcn3_01_soc.ideal_dram_bw_after_urgent_percent =
+ fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
+ dcn3_01_soc.max_request_size_bytes =
+ le32_to_cpu(bb->max_request_size_bytes);
+ dcn3_01_soc.dram_channel_width_bytes =
+ le32_to_cpu(bb->dram_channel_width_bytes);
+ dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes =
+ le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
+ dcn3_01_soc.dcn_downspread_percent =
+ fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
+ dcn3_01_soc.downspread_percent =
+ fixed16_to_double_to_cpu(bb->downspread_percent);
+ dcn3_01_soc.dram_page_open_time_ns =
+ fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
+ dcn3_01_soc.dram_rw_turnaround_time_ns =
+ fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
+ dcn3_01_soc.dram_return_buffer_per_channel_bytes =
+ le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
+ dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles =
+ le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
+ dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes =
+ le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
+ dcn3_01_soc.channel_interleave_bytes =
+ le32_to_cpu(bb->channel_interleave_bytes);
+ dcn3_01_soc.num_banks =
+ le32_to_cpu(bb->num_banks);
+ dcn3_01_soc.num_chans =
+ le32_to_cpu(bb->num_chans);
+ dcn3_01_soc.gpuvm_min_page_size_bytes =
+ le32_to_cpu(bb->vmm_page_size_bytes);
+ dcn3_01_soc.dram_clock_change_latency_us =
+ fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+ dcn3_01_soc.writeback_dram_clock_change_latency_us =
+ fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
+ dcn3_01_soc.return_bus_width_bytes =
+ le32_to_cpu(bb->return_bus_width_bytes);
+ dcn3_01_soc.dispclk_dppclk_vco_speed_mhz =
+ le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
+ dcn3_01_soc.xfc_bus_transport_time_us =
+ le32_to_cpu(bb->xfc_bus_transport_time_us);
+ dcn3_01_soc.xfc_xbuf_latency_tolerance_us =
+ le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
+ dcn3_01_soc.use_urgent_burst_bw =
+ le32_to_cpu(bb->use_urgent_burst_bw);
+ dcn3_01_soc.num_states =
+ le32_to_cpu(bb->num_states);
+
+ for (i = 0; i < dcn3_01_soc.num_states; i++) {
+ dcn3_01_soc.clock_limits[i].state =
+ le32_to_cpu(bb->clock_limits[i].state);
+ dcn3_01_soc.clock_limits[i].dcfclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
+ dcn3_01_soc.clock_limits[i].fabricclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
+ dcn3_01_soc.clock_limits[i].dispclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
+ dcn3_01_soc.clock_limits[i].dppclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
+ dcn3_01_soc.clock_limits[i].phyclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
+ dcn3_01_soc.clock_limits[i].socclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
+ dcn3_01_soc.clock_limits[i].dscclk_mhz =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
+ dcn3_01_soc.clock_limits[i].dram_speed_mts =
+ fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
+ }
+ }
+
+ if (pool->base.pp_smu) {
+ struct pp_smu_nv_clock_table max_clocks = {0};
+ unsigned int uclk_states[8] = {0};
+ unsigned int num_states = 0;
+ enum pp_smu_status status;
+ bool clock_limits_available = false;
+ bool uclk_states_available = false;
+
+ if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
+ status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
+ (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
+
+ uclk_states_available = (status == PP_SMU_RESULT_OK);
+ }
+
+ if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
+ status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
+ (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
+ /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
+ */
+ if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
+ max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
+ clock_limits_available = (status == PP_SMU_RESULT_OK);
+ }
+
+ if (clock_limits_available && uclk_states_available && num_states)
+ dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+ else if (clock_limits_available)
+ dcn20_cap_soc_clocks(loaded_bb, max_clocks);
+ }
+
+ loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
+ loaded_ip->max_num_dpp = pool->base.pipe_count;
+ dcn20_patch_bounding_box(dc, loaded_bb);
+
+ return true;
+}
+
+static void set_wm_ranges(
+ struct pp_smu_funcs *pp_smu,
+ struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
+{
+ struct pp_smu_wm_range_sets ranges = {0};
+ int i;
+
+ ranges.num_reader_wm_sets = 0;
+
+ if (loaded_bb->num_states == 1) {
+ ranges.reader_wm_sets[0].wm_inst = 0;
+ ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+ ranges.num_reader_wm_sets = 1;
+ } else if (loaded_bb->num_states > 1) {
+ for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
+ ranges.reader_wm_sets[i].wm_inst = i;
+ ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
+ ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
+
+ ranges.num_reader_wm_sets = i + 1;
+ }
+
+ ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ }
+
+ ranges.num_writer_wm_sets = 1;
+
+ ranges.writer_wm_sets[0].wm_inst = 0;
+ ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+ /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+ pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
+}
+
+static struct pp_smu_funcs *dcn301_pp_smu_create(struct dc_context *ctx)
+{
+ struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+
+ if (!pp_smu)
+ return pp_smu;
+
+ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && !IS_DIAG_DC(ctx->dce_environment)) {
+ dm_pp_get_funcs(ctx, pp_smu);
+
+ /* TODO: update once we have n21 smu*/
+ if (pp_smu->ctx.ver != PP_SMU_VER_NV)
+ pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
+ }
+
+ return pp_smu;
+}
+
+static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+{
+ if (pp_smu && *pp_smu) {
+ kfree(*pp_smu);
+ *pp_smu = NULL;
+ }
+}
+
+static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+ dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+ dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+}
+
+static struct resource_funcs dcn301_res_pool_funcs = {
+ .destroy = dcn301_destroy_resource_pool,
+ .link_enc_create = dcn301_link_encoder_create,
+ .panel_cntl_create = dcn301_panel_cntl_create,
+ .validate_bandwidth = dcn30_validate_bandwidth,
+ .calculate_wm = dcn30_calculate_wm,
+ .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
+ .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+ .add_stream_to_ctx = dcn30_add_stream_to_ctx,
+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+ .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+ .set_mcif_arb_params = dcn30_set_mcif_arb_params,
+ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+ .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+ .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+ .update_bw_bounding_box = dcn301_update_bw_bounding_box
+};
+
+static bool dcn301_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dcn301_resource_pool *pool)
+{
+ int i, j;
+ struct dc_context *ctx = dc->ctx;
+ struct irq_service_init_data init_data;
+ uint32_t pipe_fuses = read_pipe_fuses(ctx);
+ uint32_t num_pipes = 0;
+
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ ctx->dc_bios->regs = &bios_regs;
+
+ pool->base.res_cap = &res_cap_dcn301;
+
+ pool->base.funcs = &dcn301_res_pool_funcs;
+
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+ pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
+ dc->caps.max_downscale_ratio = 600;
+ dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.max_cursor_size = 256;
+ dc->caps.dmdata_alloc_size = 2048;
+ dc->caps.max_slave_planes = 1;
+ dc->caps.is_apu = true;
+ dc->caps.post_blend_color_processing = true;
+ dc->caps.force_dp_tps4_for_cp2520 = true;
+ dc->caps.extended_aux_timeout_support = true;
+#ifdef CONFIG_DRM_AMD_DC_DMUB
+ dc->caps.dmcub_support = true;
+#endif
+
+ /* Color pipeline capabilities */
+ dc->caps.color.dpp.dcn_arch = 1;
+ dc->caps.color.dpp.input_lut_shared = 0;
+ dc->caps.color.dpp.icsc = 1;
+ dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+ dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+ dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+ dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+ dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+ dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+ dc->caps.color.dpp.post_csc = 1;
+ dc->caps.color.dpp.gamma_corr = 1;
+
+ dc->caps.color.dpp.hw_3d_lut = 1;
+ dc->caps.color.dpp.ogam_ram = 1;
+ // no OGAM ROM on DCN301
+ dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+ dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+ dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+ dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+ dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+ dc->caps.color.dpp.ocsc = 0;
+
+ dc->caps.color.mpc.gamut_remap = 1;
+ dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.ogam_ram = 1;
+ dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+ dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+ dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+ dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+ dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+ dc->caps.color.mpc.ocsc = 1;
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ dc->debug = debug_defaults_drv;
+ else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+ dc->debug = debug_defaults_diags;
+ } else
+ dc->debug = debug_defaults_diags;
+ // Init the vm_helper
+ if (dc->vm_helper)
+ vm_helper_init(dc->vm_helper, 16);
+
+ /*************************************************
+ * Create resources *
+ *************************************************/
+
+ /* Clock Sources for Pixel Clock*/
+ pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
+ dcn301_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL0,
+ &clk_src_regs[0], false);
+ pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
+ dcn301_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL1,
+ &clk_src_regs[1], false);
+ pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
+ dcn301_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL2,
+ &clk_src_regs[2], false);
+ pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
+ dcn301_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL3,
+ &clk_src_regs[3], false);
+
+ pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
+
+ /* todo: not reuse phy_pll registers */
+ pool->base.dp_clock_source =
+ dcn301_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_ID_DP_DTO,
+ &clk_src_regs[0], true);
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] == NULL) {
+ dm_error("DC: failed to create clock sources!\n");
+ BREAK_TO_DEBUGGER();
+ goto create_fail;
+ }
+ }
+
+ /* DCCG */
+ pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+ if (pool->base.dccg == NULL) {
+ dm_error("DC: failed to create dccg!\n");
+ BREAK_TO_DEBUGGER();
+ goto create_fail;
+ }
+
+ /* PP Lib and SMU interfaces */
+ pool->base.pp_smu = dcn301_pp_smu_create(ctx);
+ init_soc_bounding_box(dc, pool);
+ if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
+ set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
+
+ num_pipes = dcn3_01_ip.max_num_dpp;
+
+ for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
+ if (pipe_fuses & 1 << i)
+ num_pipes--;
+ dcn3_01_ip.max_num_dpp = num_pipes;
+ dcn3_01_ip.max_num_otg = num_pipes;
+
+
+ dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
+
+ /* IRQ */
+ init_data.ctx = dc->ctx;
+ pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
+ if (!pool->base.irqs)
+ goto create_fail;
+
+ /* HUBBUB */
+ pool->base.hubbub = dcn301_hubbub_create(ctx);
+ if (pool->base.hubbub == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create hubbub!\n");
+ goto create_fail;
+ }
+
+ j = 0;
+ /* HUBPs, DPPs, OPPs and TGs */
+ for (i = 0; i < pool->base.pipe_count; i++) {
+
+ /* if pipe is disabled, skip instance of HW pipe,
+ * i.e, skip ASIC register instance
+ */
+ if ((pipe_fuses & (1 << i)) != 0) {
+ DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
+ continue;
+ }
+
+ pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
+ if (pool->base.hubps[j] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create hubps!\n");
+ goto create_fail;
+ }
+
+ pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
+ if (pool->base.dpps[j] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create dpps!\n");
+ goto create_fail;
+ }
+
+ pool->base.opps[j] = dcn301_opp_create(ctx, i);
+ if (pool->base.opps[j] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create output pixel processor!\n");
+ goto create_fail;
+ }
+
+ pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
+ if (pool->base.timing_generators[j] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create tg!\n");
+ goto create_fail;
+ }
+ j++;
+ }
+ pool->base.timing_generator_count = j;
+ pool->base.pipe_count = j;
+ pool->base.mpcc_count = j;
+
+ /* ABM (or ABMs for NV2x) */
+ /* TODO: */
+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ pool->base.multiple_abms[i] = dce_abm_create(ctx,
+ &abm_regs[i],
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.multiple_abms[i] == NULL) {
+ dm_error("DC: failed to create abm for pipe %d!\n", i);
+ BREAK_TO_DEBUGGER();
+ goto create_fail;
+ }
+ }
+
+ /* MPC and DSC */
+ pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
+ if (pool->base.mpc == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create mpc!\n");
+ goto create_fail;
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
+ if (pool->base.dscs[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create display stream compressor %d!\n", i);
+ goto create_fail;
+ }
+ }
+
+ /* DWB and MMHUBBUB */
+ if (!dcn301_dwbc_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create dwbc!\n");
+ goto create_fail;
+ }
+
+ if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create mcif_wb!\n");
+ goto create_fail;
+ }
+
+ /* AUX and I2C */
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
+ goto create_fail;
+ }
+ pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
+ if (pool->base.hw_i2cs[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create hw i2c!!\n");
+ goto create_fail;
+ }
+ pool->base.sw_i2cs[i] = NULL;
+ }
+
+ /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+ &res_create_funcs : &res_create_maximus_funcs)))
+ goto create_fail;
+
+ /* HW Sequencer and Plane caps */
+ dcn301_hw_sequencer_construct(dc);
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
+ for (i = 0; i < dc->caps.max_planes; ++i)
+ dc->caps.planes[i] = plane_cap;
+
+ dc->cap_funcs = cap_funcs;
+
+ return true;
+
+create_fail:
+
+ dcn301_destruct(pool);
+
+ return false;
+}
+
+struct resource_pool *dcn301_create_resource_pool(
+ const struct dc_init_data *init_data,
+ struct dc *dc)
+{
+ struct dcn301_resource_pool *pool =
+ kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
+
+ if (!pool)
+ return NULL;
+
+ if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+ kfree(pool);
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h
new file mode 100644
index 000000000000..17e4e91ff4b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN301_RESOURCE_H_
+#define _DCN301_RESOURCE_H_
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+struct dcn301_resource_pool {
+ struct resource_pool base;
+};
+struct resource_pool *dcn301_create_resource_pool(
+ const struct dc_init_data *init_data,
+ struct dc *dc);
+
+#endif /* _DCN301_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 3586934df25f..e05273d4739d 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -278,14 +278,38 @@ struct pp_smu_funcs_rn {
enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
struct dpm_clocks *clock_table);
};
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+struct pp_smu_funcs_vgh {
+ struct pp_smu pp_smu;
+ /*
+ * reader and writer WM's are sent together as part of one table
+ *
+ * PPSMC_MSG_SetDriverDramAddrHigh
+ * PPSMC_MSG_SetDriverDramAddrLow
+ * PPSMC_MSG_TransferTableDram2Smu
+ *
+ */
+ // TODO: Check whether this is moved to DAL, and remove as needed
+ enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
+ struct pp_smu_wm_range_sets *ranges);
+
+ // TODO: Check whether this is moved to DAL, and remove as needed
+ enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
+ struct dpm_clocks *clock_table);
+
+ enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);
+};
+#endif
struct pp_smu_funcs {
struct pp_smu ctx;
union {
struct pp_smu_funcs_rv rv_funcs;
struct pp_smu_funcs_nv nv_funcs;
struct pp_smu_funcs_rn rn_funcs;
-
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ struct pp_smu_funcs_vgh vgh_funcs;
+#endif
};
};
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 6fc8a6e9dc15..f9ed80c48980 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -114,6 +114,9 @@ bool dal_hw_factory_init(
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case DCN_VERSION_3_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case DCN_VERSION_3_01:
+#endif
dal_hw_factory_dcn30_init(factory);
return true;
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 3a93c945e57d..8abc4b0a961c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -109,6 +109,9 @@ bool dal_hw_translate_init(
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case DCN_VERSION_3_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case DCN_VERSION_3_01:
+#endif
dal_hw_translate_dcn30_init(translate);
return true;
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 947d6106f341..35d1b85713b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -62,6 +62,25 @@ struct dcn3_clk_internal {
};
#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+struct dcn301_clk_internal {
+ int dummy;
+ uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
+ uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
+ uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
+ uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
+ uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
+ uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
+
+ uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
+ uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
+ uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
+ uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
+};
+
+#endif
+
/* Will these bw structures be ASIC specific? */
#define MAX_NUM_DPM_LVL 8
@@ -262,6 +281,17 @@ struct clk_mgr_funcs {
#endif
};
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+struct dpm_clocks;
+struct wartermarks;
+
+struct smu_watermark_set {
+ struct watermarks *wm_set;
+ union large_integer mc_address;
+};
+
+#endif
+
struct clk_mgr {
struct dc_context *ctx;
struct clk_mgr_funcs *funcs;
@@ -275,6 +305,9 @@ struct clk_mgr {
struct clk_state_registers_and_bypass boot_snapshot;
struct clk_bw_params *bw_params;
struct pp_smu_wm_range_sets ranges;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+ struct smu_watermark_set smu_wm_set;
+#endif
};
/* forward declarations */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 65f182c8bf14..371da657c8a4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -152,6 +152,10 @@ struct hubbub_funcs {
void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+
+ void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
+#endif
};
struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 286cceeb9c24..0dbd5a55de33 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -187,6 +187,11 @@ struct hubp_funcs {
struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ void (*set_unbounded_requesting)(
+ struct hubp *hubp,
+ bool enable);
+#endif
};
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index c6a8d6c54621..47c1da263d9d 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -90,6 +90,9 @@ enum dmub_asic {
DMUB_ASIC_DCN21,
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
DMUB_ASIC_DCN30,
+#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+ DMUB_ASIC_DCN301,
#endif
DMUB_ASIC_MAX,
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index bb584f39cad0..f40d82e19e59 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -22,7 +22,7 @@
DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
ifdef CONFIG_DRM_AMD_DC_DCN3_0
-DMUB += dmub_dcn30.o
+DMUB += dmub_dcn30.o dmub_dcn301.o
endif
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
new file mode 100644
index 000000000000..197398257692
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn301.h"
+
+#include "dcn/dcn_3_0_1_offset.h"
+#include "dcn/dcn_3_0_1_sh_mask.h"
+#include "vangogh_ip_offset.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs
+
+/* Registers. */
+
+const struct dmub_srv_common_regs dmub_srv_dcn301_regs = {
+#define DMUB_SR(reg) REG_OFFSET(reg),
+ { DMUB_COMMON_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+ { DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+ { DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+};
+
+/* Shared functions. */
+
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h
new file mode 100644
index 000000000000..faafaf300583
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN301_H_
+#define _DMUB_DCN301_H_
+
+#include "dmub_dcn20.h"
+
+/* Registers. */
+
+extern const struct dmub_srv_common_regs dmub_srv_dcn301_regs;
+
+/* Hardware functions. */
+
+#endif /* _DMUB_DCN301_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 08da423b24a1..8ba7ecd29665 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -30,6 +30,9 @@
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
#include "dmub_dcn30.h"
#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+#include "dmub_dcn301.h"
+#endif
#include "os_types.h"
/*
* Note: the DMUB service is standalone. No additional headers should be
@@ -138,6 +141,9 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
case DMUB_ASIC_DCN21:
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
case DMUB_ASIC_DCN30:
+#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+ case DMUB_ASIC_DCN301:
#endif
dmub->regs = &dmub_srv_dcn20_regs;
@@ -169,6 +175,14 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->setup_windows = dmub_dcn30_setup_windows;
}
#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN3_01
+ if (asic == DMUB_ASIC_DCN301) {
+ dmub->regs = &dmub_srv_dcn301_regs;
+
+ funcs->backdoor_load = dmub_dcn30_backdoor_load;
+ funcs->setup_windows = dmub_dcn30_setup_windows;
+ }
+#endif
break;
default:
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index b267987aed06..b6b60a9c0509 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -205,6 +205,16 @@ enum {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define FAMILY_VGH 144
+#define DEVICE_ID_VGH_163F 0x163F
+#define VANGOGH_A0 0x01
+#define VANGOGH_UNKNOWN 0xFF
+
+#ifndef ASICREV_IS_VANGOGH
+#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
+#endif
+#endif
/*
* ASIC chip ID
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 8aaa3af69202..9cf6853193f8 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -51,7 +51,12 @@ enum dce_version {
DCN_VERSION_1_01,
DCN_VERSION_2_0,
DCN_VERSION_2_1,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
DCN_VERSION_3_0,
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ DCN_VERSION_3_01,
+#endif
DCN_VERSION_MAX
};
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 7a06e3914c00..04dd546a143c 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -284,6 +284,18 @@ struct ext_hdmi_settings {
struct i2c_reg_info reg_settings_6g[3];
};
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+struct edp_info {
+ uint16_t edp_backlight_pwm_hz;
+ uint16_t edp_ss_percentage;
+ uint16_t edp_ss_rate_10hz;
+ uint8_t edp_pwr_on_off_delay;
+ uint8_t edp_pwr_on_vary_bl_to_blon;
+ uint8_t edp_pwr_down_bloff_to_vary_bloff;
+ uint8_t edp_panel_bpc;
+ uint8_t edp_bootup_bl_level;
+};
+#endif
/* V6 */
struct integrated_info {
@@ -403,6 +415,11 @@ struct integrated_info {
struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
/* V11 */
uint32_t dp_ss_control;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ /* V2.1 */
+ struct edp_info edp1_info;
+ struct edp_info edp2_info;
+#endif
};
/**
--
2.25.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (41 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 43/45] drm/amd/display: Add dcn3.01 support to DC Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 45/45] drm/amdgpu: add van gogh pci id Alex Deucher
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Roman Li
From: Roman Li <Roman.Li@amd.com>
Update dm for vangogh support.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e8177656e083..3cf4e08931bb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,6 +100,10 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
+#endif
#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1135,6 +1139,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
#endif
return 0;
case CHIP_NAVI12:
@@ -1242,6 +1249,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
break;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
+ dmub_asic = DMUB_ASIC_DCN301;
+ fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
+ break;
+#endif
default:
/* ASIC doesn't support DMUB. */
@@ -3362,6 +3375,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
#endif
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -3609,6 +3625,13 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
+ adev->mode_info.num_crtc = 4;
+ adev->mode_info.num_hpd = 4;
+ adev->mode_info.num_dig = 4;
+ break;
+#endif
case CHIP_NAVI14:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
@@ -3928,6 +3951,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER ||
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ adev->asic_type == CHIP_VANGOGH ||
#endif
adev->asic_type == CHIP_RENOIR ||
adev->asic_type == CHIP_RAVEN) {
--
2.25.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 45/45] drm/amdgpu: add van gogh pci id
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
` (42 preceding siblings ...)
2020-09-25 20:10 ` [PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM Alex Deucher
@ 2020-09-25 20:10 ` Alex Deucher
43 siblings, 0 replies; 64+ messages in thread
From: Alex Deucher @ 2020-09-25 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add Van Gogh PCI id support.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 9ad1da52e6da..564336c2ee66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1088,6 +1088,9 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ /* Van Gogh */
+ {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
+
{0, 0, 0}
};
--
2.25.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread