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From: Stylon Wang <stylon.wang@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Stylon Wang <stylon.wang@amd.com>, Aric Cyr <Aric.Cyr@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Wyatt Wood <wyatt.wood@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 02/20] drm/amd/display: Add get_current_time interface to dmub_srv
Date: Fri, 14 May 2021 12:49:45 +0800	[thread overview]
Message-ID: <20210514045003.3069681-3-stylon.wang@amd.com> (raw)
In-Reply-To: <20210514045003.3069681-1-stylon.wang@amd.com>

From: Wyatt Wood <wyatt.wood@amd.com>

[Why]
Need to get current DMUB time.

[How]
Add get_current_time interface to dmub_srv.

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 39 ++++++++++---------
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |  8 ++--
 drivers/gpu/drm/amd/display/dc/dm_services.h  |  1 -
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |  1 +
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  5 +++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  5 ++-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  1 +
 7 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d6f11dbf1bd4..b4aa20250301 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2636,14 +2636,14 @@ static void commit_planes_for_stream(struct dc *dc,
 						top_pipe_to_program->stream_res.tg);
 		}
 
-	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
-		dc->hwss.interdependent_update_lock(dc, context, true);
-	else
-		/* Lock the top pipe while updating plane addrs, since freesync requires
-		 *  plane addr update event triggers to be synchronized.
-		 *  top_pipe_to_program is expected to never be NULL
-		 */
-		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
+		if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
+			dc->hwss.interdependent_update_lock(dc, context, true);
+		else
+			/* Lock the top pipe while updating plane addrs, since freesync requires
+			 *  plane addr update event triggers to be synchronized.
+			 *  top_pipe_to_program is expected to never be NULL
+			 */
+			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 
 	// Stream updates
 	if (stream_update)
@@ -2659,11 +2659,10 @@ static void commit_planes_for_stream(struct dc *dc,
 		if (dc->hwss.program_front_end_for_ctx)
 			dc->hwss.program_front_end_for_ctx(dc, context);
 
-		if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
-			dc->hwss.interdependent_update_lock(dc, context, false);
-		else
-			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
-
+			if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
+				dc->hwss.interdependent_update_lock(dc, context, false);
+			else
+				dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 		dc->hwss.post_unlock_program_front_end(dc, context);
 		return;
 	}
@@ -2764,6 +2763,7 @@ static void commit_planes_for_stream(struct dc *dc,
 							plane_state->flip_immediate);
 				}
 			}
+
 		/* Perform requested Updates */
 		for (i = 0; i < surface_count; i++) {
 			struct dc_plane_state *plane_state = srf_updates[i].surface;
@@ -2786,12 +2786,13 @@ static void commit_planes_for_stream(struct dc *dc,
 					dc->hwss.update_plane_addr(dc, pipe_ctx);
 			}
 		}
+
 	}
 
-	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
-		dc->hwss.interdependent_update_lock(dc, context, false);
-	else
-		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
+		if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
+			dc->hwss.interdependent_update_lock(dc, context, false);
+		else
+			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 
 	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
 		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
@@ -2837,8 +2838,8 @@ static void commit_planes_for_stream(struct dc *dc,
 				pipe_ctx->plane_state->skip_manual_trigger)
 			continue;
 
-		if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
-			pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
+			if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
+				pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index b0c9180b808f..e7c56df8f762 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -795,10 +795,10 @@ bool hubp21_program_surface_flip_and_addr(
 	flip_regs.tmz_surface = address->tmz_surface;
 	flip_regs.immediate = flip_immediate;
 
-	if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-		dmcub_PLAT_54186_wa(hubp, &flip_regs);
-	else
-		program_surface_flip_and_addr(hubp, &flip_regs);
+		if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+			dmcub_PLAT_54186_wa(hubp, &flip_regs);
+		else
+			program_surface_flip_and_addr(hubp, &flip_regs);
 
 	hubp->request_address = *address;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 9a3f2a44f882..7a3beaecd19d 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -264,7 +264,6 @@ static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
 		unsigned long long current_time_stamp,
 		unsigned long long last_time_stamp);
-
 /*
  * performance tracing
  */
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 3ef6b536ccea..deff333e7437 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -323,6 +323,7 @@ struct dmub_srv_hw_funcs {
 
 	uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
 
+	uint32_t (*get_current_time)(struct dmub_srv *dmub);
 };
 
 /**
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index b11f530f682c..8cdc1c75394e 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -399,3 +399,8 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
 	boot_options.bits.skip_phy_init_panel_sequence = skip;
 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 }
+
+uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index 42d610a260ef..f772f8b348ea 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -107,7 +107,8 @@ struct dmub_srv;
 	DMUB_SR(MMHUBBUB_SOFT_RESET) \
 	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
 	DMUB_SR(DCN_VM_FB_OFFSET) \
-	DMUB_SR(DMCUB_INTERRUPT_ACK)
+	DMUB_SR(DMCUB_INTERRUPT_ACK) \
+	DMUB_SR(DMCUB_TIMER_CURRENT)
 
 #define DMUB_COMMON_FIELDS() \
 	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -231,4 +232,6 @@ bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);
 
 bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);
 
+uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);
+
 #endif /* _DMUB_DCN20_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index ed9fa6138aa6..fa89ada1e313 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -159,6 +159,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 		funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
 		funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
 		funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
+		funcs->get_current_time = dmub_dcn20_get_current_time;
 
 		// Out mailbox register access functions for RN and above
 		funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
-- 
2.25.1

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  parent reply	other threads:[~2021-05-14  4:50 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14  4:49 [PATCH 00/20] DC Patches May 17, 2021 Stylon Wang
2021-05-14  4:49 ` [PATCH 01/20] drm/amd/display: treat memory as a single-channel for asymmetric memory V3 Stylon Wang
2021-05-14  4:49 ` Stylon Wang [this message]
2021-05-14  4:49 ` [PATCH 03/20] drm/amd/display: Add documentation for power gate plane Stylon Wang
2021-05-14  4:49 ` [PATCH 04/20] drm/amd/display: Remove legacy comments Stylon Wang
2021-05-14  4:49 ` [PATCH 05/20] drm/amd/display: Add kernel-doc to some hubp functions Stylon Wang
2021-05-14  4:49 ` [PATCH 06/20] drm/amd/display: Document set RECOUT operation Stylon Wang
2021-05-14  4:49 ` [PATCH 07/20] drm/amd/display: Minor refactor of DP PHY test automation Stylon Wang
2021-05-14  4:49 ` [PATCH 08/20] drm/amd/display: Disconnect non-DP with no EDID Stylon Wang
2021-05-14  4:49 ` [PATCH 09/20] drm/amd/display: determine dp link encoding format from link settings Stylon Wang
2021-05-14  4:49 ` [PATCH 10/20] drm/amd/display: decide link training settings based on channel coding Stylon Wang
2021-05-14  4:49 ` [PATCH 11/20] drm/amd/display: rename perform_link_training_int function Stylon Wang
2021-05-14  4:49 ` [PATCH 12/20] drm/amd/display: consider channel coding in configure lttpr mode Stylon Wang
2021-05-14  4:49 ` [PATCH 13/20] drm/amd/display: Refactor suspend/resume of Secure display Stylon Wang
2021-05-14  4:49 ` [PATCH 14/20] drm/amd/display: Add Overflow check to skip MALL Stylon Wang
2021-05-14  4:49 ` [PATCH 15/20] drm/amd/display: Correct DPCD revision for eDP v1.4 Stylon Wang
2021-05-14  4:49 ` [PATCH 16/20] drm/amd/display: Avoid get/put vblank when stream disabled Stylon Wang
2021-05-14  4:50 ` [PATCH 17/20] drm/amd/display: Use the correct max downscaling value for DCN3.x family Stylon Wang
2021-05-14  4:50 ` [PATCH 18/20] drm/amd/display: Refactor and add visual confirm for HW Flip Queue Stylon Wang
2021-05-14  4:50 ` [PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.0.66 Stylon Wang
2021-05-14  4:50 ` [PATCH 20/20] drm/amd/display: 3.2.136 Stylon Wang
2021-05-14 19:32 ` [PATCH 00/20] DC Patches May 17, 2021 Wheeler, Daniel

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