From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <alexander.deucher@amd.com>, <Harry.Wentland@amd.com>,
<nicholas.kazlauskas@amd.com>, <Rodrigo.Siqueira@amd.com>,
<wayne.lin@amd.com>, <stylon.wang@amd.com>, <jude.shih@amd.com>,
<jimmy.kizito@amd.com>, <meenakshikumar.somasundaram@amd.com>,
Jude Shih <shenshih@amd.com>,
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>
Subject: [PATCH v2 17/23] drm/amd/display: Support for SET_CONFIG processing with DMUB
Date: Tue, 5 Oct 2021 15:51:59 +0800 [thread overview]
Message-ID: <20211005075205.3467938-18-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20211005075205.3467938-1-Wayne.Lin@amd.com>
From: Jude Shih <shenshih@amd.com>
[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.
[How]
1) DMUB posts SET_CONFIG reply as an Outbox1 message of type
DMUB_OUT_CMD__SET_CONFIG_REPLY.
2) The dmub async to sync mechanism for AUX is modified to accommodate
SET_CONFIG commands for both command issue and reply code paths.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 73 +++++++++++++++----
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 ++++-
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 +-
.../drm/amd/display/dc/core/dc_link_dpia.c | 6 ++
5 files changed, 94 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3c7a8f869b40..41692ae30822 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11333,29 +11333,74 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
return value;
}
-int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
- struct aux_payload *payload, enum aux_return_code_type *operation_result)
+int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux, struct dc_context *ctx, uint8_t status_type,
+ uint32_t *operation_result)
+{
+ struct amdgpu_device *adev = ctx->driver_context;
+ int return_status = -1;
+ struct dmub_notification *p_notify = adev->dm.dmub_notify;
+
+ if (is_cmd_aux) {
+ if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
+ return_status = p_notify->aux_reply.length;
+ *operation_result = p_notify->result;
+ } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT) {
+ *operation_result = AUX_RET_ERROR_TIMEOUT;
+ } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) {
+ *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
+ } else {
+ *operation_result = AUX_RET_ERROR_UNKNOWN;
+ }
+ } else {
+ if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
+ return_status = 0;
+ *operation_result = p_notify->sc_status;
+ } else {
+ *operation_result = SET_CONFIG_UNKNOWN_ERROR;
+ }
+ }
+
+ return return_status;
+}
+
+int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context *ctx, unsigned int link_index,
+ void *cmd_payload, void *operation_result)
{
struct amdgpu_device *adev = ctx->driver_context;
int ret = 0;
- dc_process_dmub_aux_transfer_async(ctx->dc, linkIndex, payload);
+ if (is_cmd_aux) {
+ dc_process_dmub_aux_transfer_async(ctx->dc,
+ link_index, (struct aux_payload *)cmd_payload);
+ } else if (dc_process_dmub_set_config_async(ctx->dc, link_index,
+ (struct set_config_cmd_payload *)cmd_payload,
+ adev->dm.dmub_notify)) {
+ return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
+ ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
+ (uint32_t *)operation_result);
+ }
+
ret = wait_for_completion_interruptible_timeout(&adev->dm.dmub_aux_transfer_done, 10*HZ);
if (ret == 0) {
- *operation_result = AUX_RET_ERROR_TIMEOUT;
- return -1;
+ return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
+ ctx, DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT,
+ (uint32_t *)operation_result);
}
- *operation_result = (enum aux_return_code_type)adev->dm.dmub_notify->result;
- if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
- (*payload->reply) = adev->dm.dmub_notify->aux_reply.command;
+ if (is_cmd_aux) {
+ if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
+ struct aux_payload *payload = (struct aux_payload *)cmd_payload;
- // For read case, Copy data to payload
- if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
- (*payload->reply == AUX_TRANSACTION_REPLY_AUX_ACK))
- memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
- adev->dm.dmub_notify->aux_reply.length);
+ payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
+ if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
+ payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) {
+ memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
+ adev->dm.dmub_notify->aux_reply.length);
+ }
+ }
}
- return adev->dm.dmub_notify->aux_reply.length;
+ return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
+ ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
+ (uint32_t *)operation_result);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index a85b09986aab..37e61a88d49e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -49,6 +49,13 @@
#define AMDGPU_DM_MAX_NUM_EDP 2
#define AMDGPU_DMUB_NOTIFICATION_MAX 5
+
+/**
+ * DMUB Async to Sync Mechanism Status
+ **/
+#define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
+#define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
+#define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
@@ -721,6 +728,7 @@ void amdgpu_dm_update_connector_after_detect(
extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
-int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
- struct aux_payload *payload, enum aux_return_code_type *operation_result);
+int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux,
+ struct dc_context *ctx, unsigned int link_index,
+ void *payload, void *operation_result);
#endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 1aa69dd8e02f..ff0f91c93ba4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -683,8 +683,21 @@ int dm_helper_dmub_aux_transfer_sync(
struct aux_payload *payload,
enum aux_return_code_type *operation_result)
{
- return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, operation_result);
+ return amdgpu_dm_process_dmub_aux_transfer_sync(true, ctx,
+ link->link_index, (void *)payload,
+ (void *)operation_result);
}
+
+int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
+ const struct dc_link *link,
+ struct set_config_cmd_payload *payload,
+ enum set_config_status *operation_result)
+{
+ return amdgpu_dm_process_dmub_aux_transfer_sync(false, ctx,
+ link->link_index, (void *)payload,
+ (void *)operation_result);
+}
+
void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
{
/* TODO: something */
@@ -799,4 +812,4 @@ void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
{
/* TODO: add peridic detection implementation */
}
-#endif
\ No newline at end of file
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index dd6c473be072..b0f1cd7268c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -659,10 +659,12 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
struct aux_payload *payload,
enum aux_return_code_type *operation_result)
{
- if (dc_enable_dmub_notifications(ddc->ctx->dc))
+ if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
+ !ddc->ddc_pin) {
return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
- else
+ } else {
return dce_aux_transfer_raw(ddc, payload, operation_result);
+ }
}
/* dc_link_aux_transfer_with_retries() - Attempt to submit an
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index fb0d8b8a840a..7407c755a73e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -128,6 +128,12 @@ static enum dc_status core_link_send_set_config(struct dc_link *link,
payload.msg_type = msg_type;
payload.msg_data = msg_data;
+ if (!link->ddc->ddc_pin && !link->aux_access_disabled &&
+ (dm_helpers_dmub_set_config_sync(link->ctx, link,
+ &payload, &set_config_result) == -1)) {
+ return DC_ERROR_UNEXPECTED;
+ }
+
/* set_config should return ACK if successful */
return (set_config_result == SET_CONFIG_ACK_RECEIVED) ? DC_OK : DC_ERROR_UNEXPECTED;
}
--
2.25.1
next prev parent reply other threads:[~2021-10-05 7:59 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-05 7:51 [PATCH v2 00/23] USB4 DP tunneling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 01/23] drm/amd/display: Update link encoder object creation Wayne Lin
2021-10-05 14:15 ` Harry Wentland
2021-10-05 15:13 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 02/23] drm/amd/display: USB4 DPIA enumeration and AUX Tunneling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 03/23] drm/amd/display: Support for DMUB HPD and HPD RX interrupt handling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 04/23] drm/amd/display: Support USB4 dynamic link encoder selection Wayne Lin
2021-10-05 15:46 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 05/23] drm/amd/display: Support USB4 for display endpoint control path Wayne Lin
2021-10-05 15:50 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 06/23] drm/amd/display: Support DP tunneling when DPRX detection Wayne Lin
2021-10-05 15:57 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 07/23] drm/amd/display: Update training parameters for DPIA links Wayne Lin
2021-10-05 15:58 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 08/23] drm/amd/display: Support USB4 when DP link training Wayne Lin
2021-10-05 15:59 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 09/23] drm/amd/display: Implement DPIA training loop Wayne Lin
2021-10-05 7:51 ` [PATCH v2 10/23] drm/amd/display: Implement DPIA link configuration Wayne Lin
2021-10-05 7:51 ` [PATCH v2 11/23] drm/amd/display: Implement DPIA clock recovery phase Wayne Lin
2021-10-07 10:00 ` Mike Lothian
2021-10-08 8:32 ` Lin, Wayne
2021-10-05 7:51 ` [PATCH v2 12/23] drm/amd/display: Implement DPIA equalisation phase Wayne Lin
2021-10-05 7:51 ` [PATCH v2 13/23] drm/amd/display: Implement end of training for hop in DPIA display path Wayne Lin
2021-10-05 7:51 ` [PATCH v2 14/23] drm/amd/display: Support for SET_CONFIG processing with DMUB Wayne Lin
2021-10-05 7:51 ` [PATCH v2 15/23] drm/amd/display: Read USB4 DP tunneling data from DPCD Wayne Lin
2021-10-05 7:51 ` [PATCH v2 16/23] drm/amd/display: Add dpia debug options Wayne Lin
2021-10-05 7:51 ` Wayne Lin [this message]
2021-10-05 7:52 ` [PATCH v2 18/23] drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints Wayne Lin
2021-10-05 7:52 ` [PATCH v2 19/23] drm/amd/display: Add debug flags for USB4 DP link training Wayne Lin
2021-10-05 17:10 ` Harry Wentland
2021-10-06 10:14 ` Lin, Wayne
2021-10-06 14:02 ` Harry Wentland
2021-10-07 9:22 ` Lin, Wayne
2021-10-05 7:52 ` [PATCH v2 20/23] drm/amd/display: Fix for access for ddc pin and aux engine Wayne Lin
2021-10-05 7:52 ` [PATCH v2 21/23] drm/amd/display: Deadlock/HPD Status/Crash Bug Fix Wayne Lin
2021-10-05 7:52 ` [PATCH v2 22/23] drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly Wayne Lin
2021-10-05 7:52 ` [PATCH v2 23/23] drm/amd/display: USB4 bring up set correct address Wayne Lin
2021-10-05 17:13 ` [PATCH v2 00/23] USB4 DP tunneling Harry Wentland
2021-10-06 10:14 ` Lin, Wayne
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