From: Harry Wentland <harry.wentland@amd.com>
To: Wayne Lin <Wayne.Lin@amd.com>, amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com, nicholas.kazlauskas@amd.com,
Rodrigo.Siqueira@amd.com, stylon.wang@amd.com, jude.shih@amd.com,
jimmy.kizito@amd.com, meenakshikumar.somasundaram@amd.com,
Jun Lei <Jun.Lei@amd.com>
Subject: Re: [PATCH v2 19/23] drm/amd/display: Add debug flags for USB4 DP link training
Date: Tue, 5 Oct 2021 13:10:59 -0400 [thread overview]
Message-ID: <33774abc-c31d-e3d6-43ec-b80bc7e946c5@amd.com> (raw)
In-Reply-To: <20211005075205.3467938-20-Wayne.Lin@amd.com>
On 2021-10-05 03:52, Wayne Lin wrote:
> From: Jimmy Kizito <Jimmy.Kizito@amd.com>
>
> [Why & How]
> Additional debug flags that can be useful for testing USB4 DP
> link training.
>
> Add flags:
> - 0x2 : Forces USB4 DP link to non-LTTPR mode
> - 0x4 : Extends status read intervals to about 60s.
>
> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
> Reviewed-by: Jun Lei <Jun.Lei@amd.com>
> Acked-by: Wayne Lin <Wayne.Lin@amd.com>
> Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ++++++
> drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 6 ++++++
> drivers/gpu/drm/amd/display/dc/dc.h | 4 +++-
> drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h | 3 +++
> 4 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index bfba1d2c6a18..423fbd2b9b39 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -4528,6 +4528,12 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> else
> link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
> }
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
Why is this guarded with DC_DCN when all other DPIA code isn't?
It looks like it might be unnecessary.
> + /* Check DP tunnel LTTPR mode debug option. */
> + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
> + link->dc->debug.dpia_debug.bits.force_non_lttpr)
> + link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
> +#endif
>
> if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
> /* By reading LTTPR capability, RX assumes that we will enable
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> index 7407c755a73e..ce15a38c2aea 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> @@ -528,6 +528,12 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
> dp_translate_training_aux_read_interval(
> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
Same here. Please drop this guard if we don't need it.
Harry
> + /* Check debug option for extending aux read interval. */
> + if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
> + wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
> +#endif
> +
> return wait_time_microsec;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index e3f884942e04..86fa94a2ef48 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -499,7 +499,9 @@ union root_clock_optimization_options {
> union dpia_debug_options {
> struct {
> uint32_t disable_dpia:1;
> - uint32_t reserved:31;
> + uint32_t force_non_lttpr:1;
> + uint32_t extend_aux_rd_interval:1;
> + uint32_t reserved:29;
> } bits;
> uint32_t raw;
> };
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
> index 790b904e37e1..e3dfe4c89ce0 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
> @@ -34,6 +34,9 @@ struct dc_link_settings;
> /* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */
> #define DPIA_CLK_SYNC_DELAY 16000
>
> +/* Extend interval between training status checks for manual testing. */
> +#define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000
> +
> /** @note Can remove once DP tunneling registers in upstream include/drm/drm_dp_helper.h */
> /* DPCD DP Tunneling over USB4 */
> #define DP_TUNNELING_CAPABILITIES_SUPPORT 0xe000d
>
next prev parent reply other threads:[~2021-10-05 17:11 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-05 7:51 [PATCH v2 00/23] USB4 DP tunneling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 01/23] drm/amd/display: Update link encoder object creation Wayne Lin
2021-10-05 14:15 ` Harry Wentland
2021-10-05 15:13 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 02/23] drm/amd/display: USB4 DPIA enumeration and AUX Tunneling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 03/23] drm/amd/display: Support for DMUB HPD and HPD RX interrupt handling Wayne Lin
2021-10-05 7:51 ` [PATCH v2 04/23] drm/amd/display: Support USB4 dynamic link encoder selection Wayne Lin
2021-10-05 15:46 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 05/23] drm/amd/display: Support USB4 for display endpoint control path Wayne Lin
2021-10-05 15:50 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 06/23] drm/amd/display: Support DP tunneling when DPRX detection Wayne Lin
2021-10-05 15:57 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 07/23] drm/amd/display: Update training parameters for DPIA links Wayne Lin
2021-10-05 15:58 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 08/23] drm/amd/display: Support USB4 when DP link training Wayne Lin
2021-10-05 15:59 ` Harry Wentland
2021-10-05 7:51 ` [PATCH v2 09/23] drm/amd/display: Implement DPIA training loop Wayne Lin
2021-10-05 7:51 ` [PATCH v2 10/23] drm/amd/display: Implement DPIA link configuration Wayne Lin
2021-10-05 7:51 ` [PATCH v2 11/23] drm/amd/display: Implement DPIA clock recovery phase Wayne Lin
2021-10-07 10:00 ` Mike Lothian
2021-10-08 8:32 ` Lin, Wayne
2021-10-05 7:51 ` [PATCH v2 12/23] drm/amd/display: Implement DPIA equalisation phase Wayne Lin
2021-10-05 7:51 ` [PATCH v2 13/23] drm/amd/display: Implement end of training for hop in DPIA display path Wayne Lin
2021-10-05 7:51 ` [PATCH v2 14/23] drm/amd/display: Support for SET_CONFIG processing with DMUB Wayne Lin
2021-10-05 7:51 ` [PATCH v2 15/23] drm/amd/display: Read USB4 DP tunneling data from DPCD Wayne Lin
2021-10-05 7:51 ` [PATCH v2 16/23] drm/amd/display: Add dpia debug options Wayne Lin
2021-10-05 7:51 ` [PATCH v2 17/23] drm/amd/display: Support for SET_CONFIG processing with DMUB Wayne Lin
2021-10-05 7:52 ` [PATCH v2 18/23] drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints Wayne Lin
2021-10-05 7:52 ` [PATCH v2 19/23] drm/amd/display: Add debug flags for USB4 DP link training Wayne Lin
2021-10-05 17:10 ` Harry Wentland [this message]
2021-10-06 10:14 ` Lin, Wayne
2021-10-06 14:02 ` Harry Wentland
2021-10-07 9:22 ` Lin, Wayne
2021-10-05 7:52 ` [PATCH v2 20/23] drm/amd/display: Fix for access for ddc pin and aux engine Wayne Lin
2021-10-05 7:52 ` [PATCH v2 21/23] drm/amd/display: Deadlock/HPD Status/Crash Bug Fix Wayne Lin
2021-10-05 7:52 ` [PATCH v2 22/23] drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly Wayne Lin
2021-10-05 7:52 ` [PATCH v2 23/23] drm/amd/display: USB4 bring up set correct address Wayne Lin
2021-10-05 17:13 ` [PATCH v2 00/23] USB4 DP tunneling Harry Wentland
2021-10-06 10:14 ` Lin, Wayne
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