From: Fangzhi Zuo <Jerry.Zuo@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
<roman.li@amd.com>, <wayne.lin@amd.com>,
<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
<jerry.zuo@amd.com>, Relja Vojvodic <relja.vojvodic@amd.com>,
Krunoslav Kovac <krunoslav.kovac@amd.com>
Subject: [PATCH 10/50] drm/amd/display: Implement bias and scale pre scl
Date: Wed, 10 Jul 2024 15:36:27 -0400 [thread overview]
Message-ID: <20240710193707.43754-11-Jerry.Zuo@amd.com> (raw)
In-Reply-To: <20240710193707.43754-1-Jerry.Zuo@amd.com>
From: Relja Vojvodic <relja.vojvodic@amd.com>
why:
New scaler needs the input to be full range color space. This will also fix
issues that come up due to not having a predefined limited color space matrix
for certain color spaces
how:
Use bias and scale HW to expand the range of limited color spaces to full
before the scaler
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com>
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 6 ++---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
.../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 27 ++++++++++++++++++-
.../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h | 3 +++
.../amd/display/dc/dpp/dcn401/dcn401_dpp.c | 3 ++-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 +--
.../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 13 ++++-----
7 files changed, 43 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 87e36d51c56d..9e42a0128baa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -901,12 +901,12 @@ void hwss_program_bias_and_scale(union block_sequence_params *params)
struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
- struct dc_bias_and_scale bns_params = {0};
+ struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
//TODO :for CNVC set scale and bias registers if necessary
- build_prescale_params(&bns_params, plane_state);
- if (dpp->funcs->dpp_program_bias_and_scale)
+ if (dpp->funcs->dpp_program_bias_and_scale) {
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+ }
}
void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4c9bb913125d..83fe13f5a367 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1292,7 +1292,7 @@ struct dc_plane_state {
struct dc_gamma gamma_correction;
struct dc_transfer_func in_transfer_func;
- struct dc_bias_and_scale *bias_and_scale;
+ struct dc_bias_and_scale bias_and_scale;
struct dc_csc_transform input_csc_color_matrix;
struct fixed31_32 coeff_reduction_factor;
struct fixed31_32 hdr_mult;
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
index e16274fee31d..8473c694bfdc 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
@@ -59,6 +59,31 @@ void dpp35_dppclk_control(
DISPCLK_R_GATE_DISABLE, 0);
}
+void dpp35_program_bias_and_scale_fcnv(
+ struct dpp *dpp_base,
+ struct dc_bias_and_scale *params)
+{
+ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+
+ if (!params->bias_and_scale_valid) {
+ REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0);
+ REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0);
+ REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0);
+
+ REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000);
+ REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000);
+ REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000);
+ } else {
+ REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params->bias_red);
+ REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params->bias_green);
+ REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params->bias_blue);
+
+ REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params->scale_red);
+ REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, params->scale_green);
+ REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, params->scale_blue);
+ }
+}
+
static struct dpp_funcs dcn35_dpp_funcs = {
.dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
.dpp_read_state = dpp30_read_state,
@@ -81,7 +106,7 @@ static struct dpp_funcs dcn35_dpp_funcs = {
.dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
.dpp_program_3dlut = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
- .dpp_program_bias_and_scale = NULL,
+ .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv,
.dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
.set_cursor_attributes = dpp3_set_cursor_attributes,
.set_cursor_position = dpp1_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
index 135872d88219..3ca339a16e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
@@ -61,4 +61,7 @@ bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,
void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
+void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
+ struct dc_bias_and_scale *bias_and_scale);
+
#endif // __DCN35_DPP_H
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
index 7cae18fd7be9..97bf26fa3573 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
@@ -30,6 +30,7 @@
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"
#include "dcn32/dcn32_dpp.h"
+#include "dcn35/dcn35_dpp.h"
#define REG(reg)\
dpp->tf_regs->reg
@@ -240,7 +241,7 @@ static struct dpp_funcs dcn401_dpp_funcs = {
.dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
.dpp_program_3dlut = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
- .dpp_program_bias_and_scale = NULL,
+ .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv,
.dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
.set_cursor_attributes = dpp401_set_cursor_attributes,
.set_cursor_position = dpp401_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index ea9bedf65d84..9a00479f0417 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1698,7 +1698,7 @@ static void dcn20_update_dchubp_dpp(
plane_state->update_flags.bits.input_csc_change ||
plane_state->update_flags.bits.color_space_change ||
plane_state->update_flags.bits.coeff_reduction_change) {
- struct dc_bias_and_scale bns_params = {0};
+ struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
// program the input csc
dpp->funcs->dpp_setup(dpp,
@@ -1715,7 +1715,6 @@ static void dcn20_update_dchubp_dpp(
}
if (dpp->funcs->dpp_program_bias_and_scale) {
//TODO :for CNVC set scale and bias registers if necessary
- build_prescale_params(&bns_params, plane_state);
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 27bba47186e9..41c76ba9ba56 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -217,12 +217,13 @@ enum optc_dsc_mode {
};
struct dc_bias_and_scale {
- uint16_t scale_red;
- uint16_t bias_red;
- uint16_t scale_green;
- uint16_t bias_green;
- uint16_t scale_blue;
- uint16_t bias_blue;
+ uint32_t scale_red;
+ uint32_t bias_red;
+ uint32_t scale_green;
+ uint32_t bias_green;
+ uint32_t scale_blue;
+ uint32_t bias_blue;
+ bool bias_and_scale_valid;
};
enum test_pattern_dyn_range {
--
2.34.1
next prev parent reply other threads:[~2024-07-10 19:37 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 19:36 [PATCH 00/50] DC Patches July 10th, 2024 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 01/50] drm/amd/display: Disable replay if VRR capability is false Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 02/50] drm/amd/display: Disable HBR audio for DP2 for certain ASICs Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 03/50] drm/amd/display: quality improvements for EASF and ISHARP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 04/50] drm/amd/display: Don't consider cursor for no plane case in DML1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 05/50] drm/amd/display: Added logging for automated DPM testing Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 06/50] drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap() Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 07/50] drm/amd/display: Revert "Check HDCP returned status" Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 08/50] drm/amd/display: fix dscclk programming sequence on DCN401 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 09/50] drm/amd/display: apply vmin optimization even if it doesn't reach vmin level Fangzhi Zuo
2024-07-10 19:36 ` Fangzhi Zuo [this message]
2024-07-10 19:36 ` [PATCH 11/50] drm/amd/display: avoid disable otg when dig was disabled Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 12/50] drm/amd/display: Add option to allow transition when odm is forced Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 13/50] drm/amd/display: When resync fifo ensure to use correct pipe ctx Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 14/50] drm/amd/display: Disable subvp based on HW cursor requirement Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 15/50] drm/amd/display: Fix DP-DVI dongle hotplug Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 16/50] drm/amd/display: Refactoring OPP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 17/50] drm/amd/display: Initialize denominators' default to 1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 18/50] drm/amd/display: Check null-initialized variables Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 19/50] drm/amd/display: Check phantom_stream before it is used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 20/50] drm/amd/display: Pass non-null to dcn20_validate_apply_pipe_split_flags Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 21/50] drm/amd/display: Check null pointers before using them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 22/50] drm/amd/display: Check stream before comparing them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 23/50] drm/amd/display: Deallocate DML memory if allocation fails Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 24/50] drm/amd/display: Refactoring MMHUBBUB Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 25/50] drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 26/50] drm/amd/display: DML2.1 resynchronization Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 27/50] drm/amd/display: Refactoring MPC Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 28/50] drm/amd/display: Fix VRR cannot enable Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 29/50] drm/amd/display: Re-enable panel replay feature Fangzhi Zuo
2024-07-10 19:47 ` Leo Li
2024-07-10 19:36 ` [PATCH 30/50] drm/amd/display: Add blanked streams override to DML2.1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 31/50] drm/amd/display: Calculate ODM width using odm slice rect, not recout Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 32/50] drm/amd/display: Issue with 3 or more mcaches per surface Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 33/50] drm/amd/display: remove dc dependencies from SPL library Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 34/50] drm/amd/display: Add P-State Keepout to dcn401 Global Sync Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 35/50] drm/amd/display: Check link_res->hpo_dp_link_enc before using it Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 36/50] drm/amd/display: Check null pointers before used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 37/50] drm/amd/display: Check null pointers before multiple uses Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 38/50] drm/amd/display: Increase array size of dummy_boolean Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 39/50] drm/amd/display: add dmcub support check Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 40/50] drm/amd/display: Refactoring DWB related files from dcn30 Files Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 41/50] drm/amd/display: Export additional FAMS2 global configuration options from DML Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 42/50] drm/amd/display: Check stream pointer is initialized before accessing Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 43/50] drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 44/50] drm/amd/display: Add visual confirm for Idle State Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 45/50] drm/amd/display: free bo used for dmub bounding box Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 46/50] drm/amd/display: Remove unnecessary DSC power gating for DCN401 Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 47/50] drm/amd/display: Allow display DCC " Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 48/50] drm/amd/display: improve logic for addition of modifers Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 49/50] drm/amd/display: Remove unused dml2_core_ip_params struct Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 50/50] drm/amd/display: 3.2.292 Fangzhi Zuo
2024-07-12 17:56 ` [PATCH 00/50] DC Patches July 10th, 2024 Wheeler, Daniel
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