From: Fangzhi Zuo <Jerry.Zuo@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
<roman.li@amd.com>, <wayne.lin@amd.com>,
<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
<jerry.zuo@amd.com>, Dillon Varone <dillon.varone@amd.com>,
Alvin Lee <alvin.lee2@amd.com>
Subject: [PATCH 34/50] drm/amd/display: Add P-State Keepout to dcn401 Global Sync
Date: Wed, 10 Jul 2024 15:36:51 -0400 [thread overview]
Message-ID: <20240710193707.43754-35-Jerry.Zuo@amd.com> (raw)
In-Reply-To: <20240710193707.43754-1-Jerry.Zuo@amd.com>
From: Dillon Varone <dillon.varone@amd.com>
[WHY&HOW]
OTG has new functionality to allow P-State relative to VStartup. Keepout region
for this should be configured based on DML outputs same as other global sync
params.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
.../dc/dce110/dce110_timing_generator.c | 1 +
.../dc/dce110/dce110_timing_generator.h | 1 +
.../dc/dce110/dce110_timing_generator_v.c | 1 +
.../dc/dce120/dce120_timing_generator.c | 1 +
.../display/dc/dce60/dce60_timing_generator.c | 3 +-
.../display/dc/dce80/dce80_timing_generator.c | 3 +-
.../amd/display/dc/dml/display_mode_structs.h | 1 +
.../dc/dml2/dml21/dml21_translation_helper.c | 1 +
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 +
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 ++-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 7 ++--
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h | 5 ++-
.../amd/display/dc/inc/hw/timing_generator.h | 4 ++-
.../amd/display/dc/optc/dcn10/dcn10_optc.c | 9 +++--
.../amd/display/dc/optc/dcn10/dcn10_optc.h | 7 +++-
.../amd/display/dc/optc/dcn401/dcn401_optc.c | 36 ++++++++++++++++++-
.../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 +++-
.../dc/resource/dce110/dce110_resource.c | 1 +
.../dc/resource/dcn401/dcn401_resource.h | 3 +-
20 files changed, 83 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 49bcfe6ec999..fa422a8cbced 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1955,6 +1955,7 @@ void dce110_tg_program_timing(struct timing_generator *tg,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index 28c58f1dff2d..ee4de740aceb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -261,6 +261,7 @@ void dce110_tg_program_timing(struct timing_generator *tg,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
index bf35dc65ca29..9837dec837ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
@@ -438,6 +438,7 @@ static void dce110_timing_generator_v_program_timing(struct timing_generator *tg
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index eb3557965781..fcf59348eb62 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -697,6 +697,7 @@ static void dce120_tg_program_timing(struct timing_generator *tg,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
index c1a85ee374d9..e5fb0e8333e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
@@ -111,13 +111,14 @@ static void program_timing(struct timing_generator *tg,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
if (!use_vbios)
program_pix_dur(tg, timing->pix_clk_100hz);
- dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
+ dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);
}
static void dce60_timing_generator_enable_advanced_request(
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 2df4654858be..003a9330c286 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -111,13 +111,14 @@ static void program_timing(struct timing_generator *tg,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
if (!use_vbios)
program_pix_dur(tg, timing->pix_clk_100hz);
- dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
+ dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);
}
static void dce80_timing_generator_enable_advanced_request(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 410e4b671228..641a8cd019cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -523,6 +523,7 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned int vupdate_offset;
unsigned int vupdate_width;
unsigned int vready_offset;
+ unsigned int pstate_keepout;
unsigned char interlaced;
double pixel_rate_mhz;
unsigned char synchronized_vblank_all_planes;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index e9647f068ee4..1fce61323201 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -1129,6 +1129,7 @@ void dml21_populate_pipe_ctx_dlg_params(struct dml2_context *dml_ctx, struct dc_
pipe_ctx->pipe_dlg_param.vupdate_offset = global_sync->dcn4.vupdate_offset_pixels;
pipe_ctx->pipe_dlg_param.vupdate_width = global_sync->dcn4.vupdate_vupdate_width_pixels;
pipe_ctx->pipe_dlg_param.vready_offset = global_sync->dcn4.vready_offset_pixels;
+ pipe_ctx->pipe_dlg_param.pstate_keepout = global_sync->dcn4.pstate_keepout_start_lines;
pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 982b2d5bfb5f..849b41f886d3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1549,6 +1549,7 @@ static enum dc_status dce110_enable_stream_timing(
0,
0,
0,
+ 0,
pipe_ctx->stream->signal,
true);
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index e06fc370267b..4846601c612d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1005,6 +1005,7 @@ enum dc_status dcn10_enable_stream_timing(
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout,
pipe_ctx->stream->signal,
true);
@@ -2995,7 +2996,8 @@ void dcn10_program_pipe(
calculate_vready_offset_for_group(pipe_ctx),
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
- pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout);
pipe_ctx->stream_res.tg->funcs->set_vtg_params(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 9a00479f0417..dd652436a539 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -909,6 +909,7 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout,
pipe_ctx->stream->signal,
true);
@@ -1885,7 +1886,8 @@ static void dcn20_program_pipe(
calculate_vready_offset_for_group(pipe_ctx),
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
- pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout);
if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
@@ -2458,7 +2460,8 @@ bool dcn20_update_bandwidth(
calculate_vready_offset_for_group(pipe_ctx),
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
- pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout);
pipe_ctx->stream_res.tg->funcs->set_vtg_params(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 31e0e9210dd7..d0b4308dca96 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -871,6 +871,7 @@ enum dc_status dcn401_enable_stream_timing(
pipe_ctx->pipe_dlg_param.vstartup_start,
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width,
+ pipe_ctx->pipe_dlg_param.pstate_keepout,
pipe_ctx->stream->signal,
true);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
index 287bf8a90ff6..03cbcbb36f1c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
@@ -65,6 +65,7 @@ struct optc {
int vupdate_offset;
int vupdate_width;
int vready_offset;
+ int pstate_keepout;
struct dc_crtc_timing orginal_patched_timing;
enum signal_type signal;
};
@@ -110,6 +111,7 @@ void optc1_program_timing(struct timing_generator *optc,
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios);
@@ -127,7 +129,8 @@ void optc1_program_global_sync(struct timing_generator *optc,
int vready_offset,
int vstartup_start,
int vupdate_offset,
- int vupdate_width);
+ int vupdate_width,
+ int pstate_keepout);
bool optc1_disable_crtc(struct timing_generator *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 0f453452234c..3d4c8bd42b49 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -172,6 +172,7 @@ struct timing_generator_funcs {
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios
);
@@ -256,7 +257,8 @@ struct timing_generator_funcs {
int vready_offset,
int vstartup_start,
int vupdate_offset,
- int vupdate_width);
+ int vupdate_width,
+ int pstate_keepout);
void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
void (*program_stereo)(struct timing_generator *tg,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
index 336488c0574e..4f82146d94b1 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
@@ -65,7 +65,8 @@ void optc1_program_global_sync(
int vready_offset,
int vstartup_start,
int vupdate_offset,
- int vupdate_width)
+ int vupdate_width,
+ int pstate_keepout)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -73,6 +74,7 @@ void optc1_program_global_sync(
optc1->vstartup_start = vstartup_start;
optc1->vupdate_offset = vupdate_offset;
optc1->vupdate_width = vupdate_width;
+ optc1->pstate_keepout = pstate_keepout;
if (optc1->vstartup_start == 0) {
BREAK_TO_DEBUGGER();
@@ -157,6 +159,7 @@ void optc1_program_timing(
int vstartup_start,
int vupdate_offset,
int vupdate_width,
+ int pstate_keepout,
const enum signal_type signal,
bool use_vbios)
{
@@ -177,6 +180,7 @@ void optc1_program_timing(
optc1->vstartup_start = vstartup_start;
optc1->vupdate_offset = vupdate_offset;
optc1->vupdate_width = vupdate_width;
+ optc1->pstate_keepout = pstate_keepout;
patched_crtc_timing = *dc_crtc_timing;
apply_front_porch_workaround(&patched_crtc_timing);
optc1->orginal_patched_timing = patched_crtc_timing;
@@ -282,7 +286,8 @@ void optc1_program_timing(
vready_offset,
vstartup_start,
vupdate_offset,
- vupdate_width);
+ vupdate_width,
+ pstate_keepout);
optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
index 369a13244e5e..b7a57f98553d 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
@@ -201,6 +201,7 @@ struct dcn_optc_registers {
uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
uint32_t OPTC_CLOCK_CONTROL;
uint32_t OPTC_WIDTH_CONTROL2;
+ uint32_t OTG_PSTATE_REGISTER;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -590,7 +591,11 @@ struct dcn_optc_registers {
type OTG_V_COUNT_STOP_TIMER;
#define TG_REG_FIELD_LIST_DCN401(type) \
- type OPTC_SEGMENT_WIDTH_LAST;
+ type OPTC_SEGMENT_WIDTH_LAST;\
+ type OTG_PSTATE_KEEPOUT_START;\
+ type OTG_PSTATE_EXTEND;\
+ type OTG_UNBLANK;\
+ type OTG_PSTATE_ALLOW_WIDTH_MIN;
struct dcn_optc_shift {
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index 9f5c2efa7560..a5d6a7dca554 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -396,13 +396,47 @@ void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, i
}
}
+static void optc401_program_global_sync(
+ struct timing_generator *optc,
+ int vready_offset,
+ int vstartup_start,
+ int vupdate_offset,
+ int vupdate_width,
+ int pstate_keepout)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ optc1->vready_offset = vready_offset;
+ optc1->vstartup_start = vstartup_start;
+ optc1->vupdate_offset = vupdate_offset;
+ optc1->vupdate_width = vupdate_width;
+ optc1->pstate_keepout = pstate_keepout;
+
+ if (optc1->vstartup_start == 0) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ REG_SET(OTG_VSTARTUP_PARAM, 0,
+ VSTARTUP_START, optc1->vstartup_start);
+
+ REG_SET_2(OTG_VUPDATE_PARAM, 0,
+ VUPDATE_OFFSET, optc1->vupdate_offset,
+ VUPDATE_WIDTH, optc1->vupdate_width);
+
+ REG_SET(OTG_VREADY_PARAM, 0,
+ VREADY_OFFSET, optc1->vready_offset);
+
+ REG_UPDATE(OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, pstate_keepout);
+}
+
static struct timing_generator_funcs dcn401_tg_funcs = {
.validate_timing = optc1_validate_timing,
.program_timing = optc1_program_timing,
.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
- .program_global_sync = optc1_program_global_sync,
+ .program_global_sync = optc401_program_global_sync,
.enable_crtc = optc401_enable_crtc,
.disable_crtc = optc401_disable_crtc,
.phantom_crtc_post_enable = optc401_phantom_crtc_post_enable,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
index 3114ecef332a..bb13a645802d 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
@@ -155,7 +155,11 @@
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
- SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+ SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\
+ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\
+ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\
+ SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\
+ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh)
void dcn401_timing_generator_init(struct optc *optc1);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
index fe518fd27b08..91da5cf85b69 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
@@ -1163,6 +1163,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
0,
0,
0,
+ 0,
pipe_ctx->stream->signal,
false);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 26efeada4f41..106008593464 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -534,7 +534,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
- SRI_ARR(OTG_DRR_CONTROL, OTG, inst)
+ SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst)
/* HUBBUB */
#define HUBBUB_REG_LIST_DCN4_01_RI(id) \
--
2.34.1
next prev parent reply other threads:[~2024-07-10 19:39 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 19:36 [PATCH 00/50] DC Patches July 10th, 2024 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 01/50] drm/amd/display: Disable replay if VRR capability is false Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 02/50] drm/amd/display: Disable HBR audio for DP2 for certain ASICs Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 03/50] drm/amd/display: quality improvements for EASF and ISHARP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 04/50] drm/amd/display: Don't consider cursor for no plane case in DML1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 05/50] drm/amd/display: Added logging for automated DPM testing Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 06/50] drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap() Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 07/50] drm/amd/display: Revert "Check HDCP returned status" Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 08/50] drm/amd/display: fix dscclk programming sequence on DCN401 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 09/50] drm/amd/display: apply vmin optimization even if it doesn't reach vmin level Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 10/50] drm/amd/display: Implement bias and scale pre scl Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 11/50] drm/amd/display: avoid disable otg when dig was disabled Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 12/50] drm/amd/display: Add option to allow transition when odm is forced Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 13/50] drm/amd/display: When resync fifo ensure to use correct pipe ctx Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 14/50] drm/amd/display: Disable subvp based on HW cursor requirement Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 15/50] drm/amd/display: Fix DP-DVI dongle hotplug Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 16/50] drm/amd/display: Refactoring OPP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 17/50] drm/amd/display: Initialize denominators' default to 1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 18/50] drm/amd/display: Check null-initialized variables Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 19/50] drm/amd/display: Check phantom_stream before it is used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 20/50] drm/amd/display: Pass non-null to dcn20_validate_apply_pipe_split_flags Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 21/50] drm/amd/display: Check null pointers before using them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 22/50] drm/amd/display: Check stream before comparing them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 23/50] drm/amd/display: Deallocate DML memory if allocation fails Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 24/50] drm/amd/display: Refactoring MMHUBBUB Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 25/50] drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 26/50] drm/amd/display: DML2.1 resynchronization Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 27/50] drm/amd/display: Refactoring MPC Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 28/50] drm/amd/display: Fix VRR cannot enable Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 29/50] drm/amd/display: Re-enable panel replay feature Fangzhi Zuo
2024-07-10 19:47 ` Leo Li
2024-07-10 19:36 ` [PATCH 30/50] drm/amd/display: Add blanked streams override to DML2.1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 31/50] drm/amd/display: Calculate ODM width using odm slice rect, not recout Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 32/50] drm/amd/display: Issue with 3 or more mcaches per surface Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 33/50] drm/amd/display: remove dc dependencies from SPL library Fangzhi Zuo
2024-07-10 19:36 ` Fangzhi Zuo [this message]
2024-07-10 19:36 ` [PATCH 35/50] drm/amd/display: Check link_res->hpo_dp_link_enc before using it Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 36/50] drm/amd/display: Check null pointers before used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 37/50] drm/amd/display: Check null pointers before multiple uses Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 38/50] drm/amd/display: Increase array size of dummy_boolean Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 39/50] drm/amd/display: add dmcub support check Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 40/50] drm/amd/display: Refactoring DWB related files from dcn30 Files Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 41/50] drm/amd/display: Export additional FAMS2 global configuration options from DML Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 42/50] drm/amd/display: Check stream pointer is initialized before accessing Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 43/50] drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 44/50] drm/amd/display: Add visual confirm for Idle State Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 45/50] drm/amd/display: free bo used for dmub bounding box Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 46/50] drm/amd/display: Remove unnecessary DSC power gating for DCN401 Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 47/50] drm/amd/display: Allow display DCC " Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 48/50] drm/amd/display: improve logic for addition of modifers Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 49/50] drm/amd/display: Remove unused dml2_core_ip_params struct Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 50/50] drm/amd/display: 3.2.292 Fangzhi Zuo
2024-07-12 17:56 ` [PATCH 00/50] DC Patches July 10th, 2024 Wheeler, Daniel
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