From: Fangzhi Zuo <Jerry.Zuo@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
<roman.li@amd.com>, <wayne.lin@amd.com>,
<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
<jerry.zuo@amd.com>, Alex Hung <alex.hung@amd.com>,
Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Subject: [PATCH 36/50] drm/amd/display: Check null pointers before used
Date: Wed, 10 Jul 2024 15:36:53 -0400 [thread overview]
Message-ID: <20240710193707.43754-37-Jerry.Zuo@amd.com> (raw)
In-Reply-To: <20240710193707.43754-1-Jerry.Zuo@amd.com>
From: Alex Hung <alex.hung@amd.com>
[WHAT & HOW]
Poniters, such as dc->clk_mgr, are null checked previously in the same
function, so Coverity warns "implies that "dc->clk_mgr" might be null".
As a result, these pointers need to be checked when used again.
This fixes 10 FORWARD_NULL issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 3 ++-
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c | 3 ++-
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 5 +++--
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 ++--
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 4 ++--
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 8 ++++----
.../amd/display/dc/link/protocols/link_dp_capability.c | 2 +-
8 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index 78df96882d6e..f8409453434c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -195,7 +195,7 @@ void dce11_pplib_apply_display_requirements(
* , then change minimum memory clock based on real-time bandwidth
* limitation.
*/
- if ((dc->ctx->asic_id.chip_family == FAMILY_AI) &&
+ if (dc->bw_vbios && (dc->ctx->asic_id.chip_family == FAMILY_AI) &&
ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
(uint32_t) div64_s64(
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index bf399819ca80..22ac2b7e49ae 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -749,7 +749,8 @@ bool hubp1_is_flip_pending(struct hubp *hubp)
if (flip_pending)
return true;
- if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
+ if (hubp &&
+ earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
return true;
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index 6bba020ad6fb..0637e4c552d8 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -927,7 +927,8 @@ bool hubp2_is_flip_pending(struct hubp *hubp)
if (flip_pending)
return true;
- if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
+ if (hubp &&
+ earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
return true;
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 849b41f886d3..4593fb2a0536 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -949,7 +949,7 @@ void dce110_edp_backlight_control(
{
struct dc_context *ctx = link->ctx;
struct bp_transmitter_control cntl = { 0 };
- uint8_t pwrseq_instance;
+ uint8_t pwrseq_instance = 0;
unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
unsigned int post_T7_delay = OLED_POST_T7_DELAY;
@@ -1002,7 +1002,8 @@ void dce110_edp_backlight_control(
*/
/* dc_service_sleep_in_milliseconds(50); */
/*edp 1.2*/
- pwrseq_instance = link->panel_cntl->pwrseq_inst;
+ if (link->panel_cntl)
+ pwrseq_instance = link->panel_cntl->pwrseq_inst;
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
if (!link->dc->config.edp_no_power_sequencing)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 4846601c612d..212576dbc336 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1553,7 +1553,7 @@ void dcn10_init_hw(struct dc *dc)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
/* Align bw context with hw config when system resume. */
- if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
+ if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
}
@@ -1673,7 +1673,7 @@ void dcn10_init_hw(struct dc *dc)
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
- if (dc->clk_mgr->funcs->notify_wm_ranges)
+ if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 746c522adf84..3d4b31bd9946 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -256,10 +256,10 @@ void dcn31_init_hw(struct dc *dc)
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
- if (dc->clk_mgr->funcs->notify_wm_ranges)
+ if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
- if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
+ if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index e4f7078c1026..ddf0807db627 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -235,7 +235,7 @@ void dcn35_init_hw(struct dc *dc)
if (hws->funcs.enable_power_gating_plane)
hws->funcs.enable_power_gating_plane(dc->hwseq, true);
*/
- if (res_pool->hubbub->funcs->dchubbub_init)
+ if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init)
res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);
/* If taking control over from VBIOS, we may want to optimize our first
* mode set, so we need to skip powering down pipes until we know which
@@ -328,10 +328,10 @@ void dcn35_init_hw(struct dc *dc)
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
- if (dc->clk_mgr->funcs->notify_wm_ranges)
+ if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
- if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
+ if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
@@ -1039,7 +1039,7 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
if (pipe_ctx->plane_res.hubp)
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
- if (pipe_ctx->plane_res.dpp)
+ if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index c257e733044a..f3b6d8936f91 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2258,7 +2258,7 @@ bool dp_verify_link_cap_with_retries(
memset(&link->verified_link_cap, 0,
sizeof(struct dc_link_settings));
- if (!link_detect_connection_type(link, &type) || type == dc_connection_none) {
+ if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
link->verified_link_cap = fail_safe_link_settings;
break;
} else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
--
2.34.1
next prev parent reply other threads:[~2024-07-10 19:40 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 19:36 [PATCH 00/50] DC Patches July 10th, 2024 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 01/50] drm/amd/display: Disable replay if VRR capability is false Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 02/50] drm/amd/display: Disable HBR audio for DP2 for certain ASICs Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 03/50] drm/amd/display: quality improvements for EASF and ISHARP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 04/50] drm/amd/display: Don't consider cursor for no plane case in DML1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 05/50] drm/amd/display: Added logging for automated DPM testing Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 06/50] drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap() Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 07/50] drm/amd/display: Revert "Check HDCP returned status" Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 08/50] drm/amd/display: fix dscclk programming sequence on DCN401 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 09/50] drm/amd/display: apply vmin optimization even if it doesn't reach vmin level Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 10/50] drm/amd/display: Implement bias and scale pre scl Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 11/50] drm/amd/display: avoid disable otg when dig was disabled Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 12/50] drm/amd/display: Add option to allow transition when odm is forced Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 13/50] drm/amd/display: When resync fifo ensure to use correct pipe ctx Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 14/50] drm/amd/display: Disable subvp based on HW cursor requirement Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 15/50] drm/amd/display: Fix DP-DVI dongle hotplug Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 16/50] drm/amd/display: Refactoring OPP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 17/50] drm/amd/display: Initialize denominators' default to 1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 18/50] drm/amd/display: Check null-initialized variables Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 19/50] drm/amd/display: Check phantom_stream before it is used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 20/50] drm/amd/display: Pass non-null to dcn20_validate_apply_pipe_split_flags Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 21/50] drm/amd/display: Check null pointers before using them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 22/50] drm/amd/display: Check stream before comparing them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 23/50] drm/amd/display: Deallocate DML memory if allocation fails Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 24/50] drm/amd/display: Refactoring MMHUBBUB Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 25/50] drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 26/50] drm/amd/display: DML2.1 resynchronization Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 27/50] drm/amd/display: Refactoring MPC Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 28/50] drm/amd/display: Fix VRR cannot enable Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 29/50] drm/amd/display: Re-enable panel replay feature Fangzhi Zuo
2024-07-10 19:47 ` Leo Li
2024-07-10 19:36 ` [PATCH 30/50] drm/amd/display: Add blanked streams override to DML2.1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 31/50] drm/amd/display: Calculate ODM width using odm slice rect, not recout Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 32/50] drm/amd/display: Issue with 3 or more mcaches per surface Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 33/50] drm/amd/display: remove dc dependencies from SPL library Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 34/50] drm/amd/display: Add P-State Keepout to dcn401 Global Sync Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 35/50] drm/amd/display: Check link_res->hpo_dp_link_enc before using it Fangzhi Zuo
2024-07-10 19:36 ` Fangzhi Zuo [this message]
2024-07-10 19:36 ` [PATCH 37/50] drm/amd/display: Check null pointers before multiple uses Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 38/50] drm/amd/display: Increase array size of dummy_boolean Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 39/50] drm/amd/display: add dmcub support check Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 40/50] drm/amd/display: Refactoring DWB related files from dcn30 Files Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 41/50] drm/amd/display: Export additional FAMS2 global configuration options from DML Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 42/50] drm/amd/display: Check stream pointer is initialized before accessing Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 43/50] drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 44/50] drm/amd/display: Add visual confirm for Idle State Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 45/50] drm/amd/display: free bo used for dmub bounding box Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 46/50] drm/amd/display: Remove unnecessary DSC power gating for DCN401 Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 47/50] drm/amd/display: Allow display DCC " Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 48/50] drm/amd/display: improve logic for addition of modifers Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 49/50] drm/amd/display: Remove unused dml2_core_ip_params struct Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 50/50] drm/amd/display: 3.2.292 Fangzhi Zuo
2024-07-12 17:56 ` [PATCH 00/50] DC Patches July 10th, 2024 Wheeler, Daniel
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