From: Fangzhi Zuo <Jerry.Zuo@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
<roman.li@amd.com>, <wayne.lin@amd.com>,
<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
<jerry.zuo@amd.com>, Alvin Lee <alvin.lee2@amd.com>,
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: [PATCH 13/50] drm/amd/display: When resync fifo ensure to use correct pipe ctx
Date: Wed, 10 Jul 2024 15:36:30 -0400 [thread overview]
Message-ID: <20240710193707.43754-14-Jerry.Zuo@amd.com> (raw)
In-Reply-To: <20240710193707.43754-1-Jerry.Zuo@amd.com>
From: Alvin Lee <alvin.lee2@amd.com>
We resync the FIFO after each pipe update in apply_ctx_to_hw.
However, this means that some pipes (in hardware) are based on the
new context and some are based on the current_state (since the pipes
are updated on at a time). In this case we must ensure to use the
pipe_ctx that's currently still configured in hardware when turning
off / on OTG's and reconfiguring ODM during the resync.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 13 +++++++++---
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.h | 2 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 20 ++++++++++++++-----
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 +-
.../display/dc/hwss/hw_sequencer_private.h | 3 ++-
6 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 51c5195f8325..982b2d5bfb5f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -2443,7 +2443,7 @@ enum dc_status dce110_apply_ctx_to_hw(
#ifdef CONFIG_DRM_AMD_DC_FP
if (hws->funcs.resync_fifo_dccg_dio)
- hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
+ hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 388404cdeeaa..4e93eeedfc1b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -355,14 +355,18 @@ void dcn314_calculate_pix_rate_divider(
}
}
-void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
+void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
{
unsigned int i;
struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false};
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ if (i <= current_pipe_idx) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+ } else {
+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ }
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
@@ -377,7 +381,10 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc
hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ if (i <= current_pipe_idx)
+ pipe = &context->res_ctx.pipe_ctx[i];
+ else
+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (otg_disabled[i]) {
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
index fb4f90f61b22..2305ad282f21 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
@@ -41,7 +41,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);
-void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
+void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 4534843ba66a..7f41eccefe02 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1201,20 +1201,27 @@ void dcn32_calculate_pix_rate_divider(
}
}
-void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
{
unsigned int i;
struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false};
+ struct dc_state *dc_state = NULL;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ if (i <= current_pipe_idx) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+ dc_state = context;
+ } else {
+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ dc_state = dc->current_state;
+ }
if (!resource_is_pipe_type(pipe, OTG_MASTER))
continue;
if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
- && dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_PHANTOM) {
+ && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
reset_sync_context_for_pipe(dc, context, i);
otg_disabled[i] = true;
@@ -1224,7 +1231,10 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_
hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ if (i <= current_pipe_idx)
+ pipe = &context->res_ctx.pipe_ctx[i];
+ else
+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (otg_disabled[i]) {
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
@@ -1572,7 +1582,7 @@ void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
#ifdef CONFIG_DRM_AMD_DC_FP
if (hws->funcs.resync_fifo_dccg_dio)
- hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
+ hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
#endif
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
index db562e45d6ff..b1563e2c0491 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
@@ -75,7 +75,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
-void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);
void dcn32_subvp_pipe_control_lock(struct dc *dc,
struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
index 7ac3f2a09487..7a75ff320511 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
@@ -170,7 +170,8 @@ struct hwseq_private_funcs {
unsigned int *k1_div,
unsigned int *k2_div);
void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
- struct dc_state *context);
+ struct dc_state *context,
+ unsigned int current_pipe_idx);
enum dc_status (*apply_single_controller_ctx_to_hw)(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
--
2.34.1
next prev parent reply other threads:[~2024-07-10 19:38 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 19:36 [PATCH 00/50] DC Patches July 10th, 2024 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 01/50] drm/amd/display: Disable replay if VRR capability is false Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 02/50] drm/amd/display: Disable HBR audio for DP2 for certain ASICs Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 03/50] drm/amd/display: quality improvements for EASF and ISHARP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 04/50] drm/amd/display: Don't consider cursor for no plane case in DML1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 05/50] drm/amd/display: Added logging for automated DPM testing Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 06/50] drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap() Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 07/50] drm/amd/display: Revert "Check HDCP returned status" Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 08/50] drm/amd/display: fix dscclk programming sequence on DCN401 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 09/50] drm/amd/display: apply vmin optimization even if it doesn't reach vmin level Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 10/50] drm/amd/display: Implement bias and scale pre scl Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 11/50] drm/amd/display: avoid disable otg when dig was disabled Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 12/50] drm/amd/display: Add option to allow transition when odm is forced Fangzhi Zuo
2024-07-10 19:36 ` Fangzhi Zuo [this message]
2024-07-10 19:36 ` [PATCH 14/50] drm/amd/display: Disable subvp based on HW cursor requirement Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 15/50] drm/amd/display: Fix DP-DVI dongle hotplug Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 16/50] drm/amd/display: Refactoring OPP Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 17/50] drm/amd/display: Initialize denominators' default to 1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 18/50] drm/amd/display: Check null-initialized variables Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 19/50] drm/amd/display: Check phantom_stream before it is used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 20/50] drm/amd/display: Pass non-null to dcn20_validate_apply_pipe_split_flags Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 21/50] drm/amd/display: Check null pointers before using them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 22/50] drm/amd/display: Check stream before comparing them Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 23/50] drm/amd/display: Deallocate DML memory if allocation fails Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 24/50] drm/amd/display: Refactoring MMHUBBUB Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 25/50] drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 26/50] drm/amd/display: DML2.1 resynchronization Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 27/50] drm/amd/display: Refactoring MPC Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 28/50] drm/amd/display: Fix VRR cannot enable Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 29/50] drm/amd/display: Re-enable panel replay feature Fangzhi Zuo
2024-07-10 19:47 ` Leo Li
2024-07-10 19:36 ` [PATCH 30/50] drm/amd/display: Add blanked streams override to DML2.1 Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 31/50] drm/amd/display: Calculate ODM width using odm slice rect, not recout Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 32/50] drm/amd/display: Issue with 3 or more mcaches per surface Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 33/50] drm/amd/display: remove dc dependencies from SPL library Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 34/50] drm/amd/display: Add P-State Keepout to dcn401 Global Sync Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 35/50] drm/amd/display: Check link_res->hpo_dp_link_enc before using it Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 36/50] drm/amd/display: Check null pointers before used Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 37/50] drm/amd/display: Check null pointers before multiple uses Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 38/50] drm/amd/display: Increase array size of dummy_boolean Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 39/50] drm/amd/display: add dmcub support check Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 40/50] drm/amd/display: Refactoring DWB related files from dcn30 Files Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 41/50] drm/amd/display: Export additional FAMS2 global configuration options from DML Fangzhi Zuo
2024-07-10 19:36 ` [PATCH 42/50] drm/amd/display: Check stream pointer is initialized before accessing Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 43/50] drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 44/50] drm/amd/display: Add visual confirm for Idle State Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 45/50] drm/amd/display: free bo used for dmub bounding box Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 46/50] drm/amd/display: Remove unnecessary DSC power gating for DCN401 Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 47/50] drm/amd/display: Allow display DCC " Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 48/50] drm/amd/display: improve logic for addition of modifers Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 49/50] drm/amd/display: Remove unused dml2_core_ip_params struct Fangzhi Zuo
2024-07-10 19:37 ` [PATCH 50/50] drm/amd/display: 3.2.292 Fangzhi Zuo
2024-07-12 17:56 ` [PATCH 00/50] DC Patches July 10th, 2024 Wheeler, Daniel
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