[PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Antheas Kapenekakis]

The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
Therefore, kernel support for S0ix was previously absent. Introduce
this support in three patches:

1) Add Van Gogh to AMD PMC driver
2) Enable spurious_8042 quirk, as it is common in those generations
3) Adjust the Van Gogh init logic to avoid powering down the rlc
   and tweak post init

This allows the Xbox Ally to properly enter and exit S0ix suspend.
Perhaps it also allows the Steam Deck to use s2idle without crashing,
note it is not currently possible [1].

Currently, around 1/10 times the SoC misses the PMC hint and does not
enter S0ix, so perhaps 1 or 3 need tweaking further. It wakes up always,
however.

@Alex: I tweaked the text on patch 3 a bit. You can resend it separately
after the issue with 1/10 failures is fixed.

[1]: https://github.com/evlaV/linux-integration/commit/5ab73e9069017aa1b5351f91513ba540ce5905fb

Alex Deucher (1):
  drm/amdgpu: only send the SMU RLC notification on S3

Antheas Kapenekakis (2):
  platform/x86/amd/pmc: Add support for Van Gogh SoC
  platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
 drivers/platform/x86/amd/pmc/pmc-quirks.c        | 8 ++++++++
 drivers/platform/x86/amd/pmc/pmc.c               | 3 +++
 drivers/platform/x86/amd/pmc/pmc.h               | 1 +
 6 files changed, 26 insertions(+), 3 deletions(-)


base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5
-- 
2.51.0

[PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Antheas Kapenekakis]

The ROG Xbox Ally (non-X) SoC features a similar architecture to the
Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
this support was dropped by the Xbox Ally which only S0ix suspend.

Since the handler is missing here, this causes the device to not suspend
and the AMD GPU driver to crash while trying to resume afterwards due to
a power hang.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
---
 drivers/platform/x86/amd/pmc/pmc.c | 3 +++
 drivers/platform/x86/amd/pmc/pmc.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index bd318fd02ccf..cae3fcafd4d7 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
 	switch (dev->cpu_id) {
 	case AMD_CPU_ID_PCO:
 	case AMD_CPU_ID_RN:
+	case AMD_CPU_ID_VG:
 	case AMD_CPU_ID_YC:
 	case AMD_CPU_ID_CB:
 		dev->num_ips = 12;
@@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 	case AMD_CPU_ID_PCO:
 		return MSG_OS_HINT_PCO;
 	case AMD_CPU_ID_RN:
+	case AMD_CPU_ID_VG:
 	case AMD_CPU_ID_YC:
 	case AMD_CPU_ID_CB:
 	case AMD_CPU_ID_PS:
@@ -717,6 +719,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
 	{ }
diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
index 62f3e51020fd..fe3f53eb5955 100644
--- a/drivers/platform/x86/amd/pmc/pmc.h
+++ b/drivers/platform/x86/amd/pmc/pmc.h
@@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
 #define AMD_CPU_ID_RN			0x1630
 #define AMD_CPU_ID_PCO			AMD_CPU_ID_RV
 #define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
+#define AMD_CPU_ID_VG			0x1645
 #define AMD_CPU_ID_YC			0x14B5
 #define AMD_CPU_ID_CB			0x14D8
 #define AMD_CPU_ID_PS			0x14E8
-- 
2.51.0

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Mario Limonciello]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> this support was dropped by the Xbox Ally which only S0ix suspend.
> 
> Since the handler is missing here, this causes the device to not suspend
> and the AMD GPU driver to crash while trying to resume afterwards due to
> a power hang.
> 
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> ---
>   drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>   drivers/platform/x86/amd/pmc/pmc.h | 1 +
>   2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index bd318fd02ccf..cae3fcafd4d7 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>   	switch (dev->cpu_id) {
>   	case AMD_CPU_ID_PCO:
>   	case AMD_CPU_ID_RN:
> +	case AMD_CPU_ID_VG:
>   	case AMD_CPU_ID_YC:
>   	case AMD_CPU_ID_CB:
>   		dev->num_ips = 12;
> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
>   	case AMD_CPU_ID_PCO:
>   		return MSG_OS_HINT_PCO;
>   	case AMD_CPU_ID_RN:
> +	case AMD_CPU_ID_VG:
>   	case AMD_CPU_ID_YC:
>   	case AMD_CPU_ID_CB:
>   	case AMD_CPU_ID_PS:
> @@ -717,6 +719,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> +	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>   	{ }
> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
> index 62f3e51020fd..fe3f53eb5955 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.h
> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>   #define AMD_CPU_ID_RN			0x1630
>   #define AMD_CPU_ID_PCO			AMD_CPU_ID_RV
>   #define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
> +#define AMD_CPU_ID_VG			0x1645

Can you see if 0xF14 gives you a reasonable value for the idle mask if 
you add it to amd_pmc_idlemask_read()?  Make a new define for it though, 
it shouldn't use the same define as 0x1a platforms.

>   #define AMD_CPU_ID_YC			0x14B5
>   #define AMD_CPU_ID_CB			0x14D8
>   #define AMD_CPU_ID_PS			0x14E8

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Antheas Kapenekakis]

On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
<mario.limonciello@amd.com> wrote:
>
>
>
> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> > The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> > Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> > this support was dropped by the Xbox Ally which only S0ix suspend.
> >
> > Since the handler is missing here, this causes the device to not suspend
> > and the AMD GPU driver to crash while trying to resume afterwards due to
> > a power hang.
> >
> > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> > Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> > ---
> >   drivers/platform/x86/amd/pmc/pmc.c | 3 +++
> >   drivers/platform/x86/amd/pmc/pmc.h | 1 +
> >   2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> > index bd318fd02ccf..cae3fcafd4d7 100644
> > --- a/drivers/platform/x86/amd/pmc/pmc.c
> > +++ b/drivers/platform/x86/amd/pmc/pmc.c
> > @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> >       switch (dev->cpu_id) {
> >       case AMD_CPU_ID_PCO:
> >       case AMD_CPU_ID_RN:
> > +     case AMD_CPU_ID_VG:
> >       case AMD_CPU_ID_YC:
> >       case AMD_CPU_ID_CB:
> >               dev->num_ips = 12;
> > @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
> >       case AMD_CPU_ID_PCO:
> >               return MSG_OS_HINT_PCO;
> >       case AMD_CPU_ID_RN:
> > +     case AMD_CPU_ID_VG:
> >       case AMD_CPU_ID_YC:
> >       case AMD_CPU_ID_CB:
> >       case AMD_CPU_ID_PS:
> > @@ -717,6 +719,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
> >       { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> >       { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
> >       { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> > +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
> >       { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
> >       { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
> >       { }
> > diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
> > index 62f3e51020fd..fe3f53eb5955 100644
> > --- a/drivers/platform/x86/amd/pmc/pmc.h
> > +++ b/drivers/platform/x86/amd/pmc/pmc.h
> > @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
> >   #define AMD_CPU_ID_RN                       0x1630
> >   #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
> >   #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
> > +#define AMD_CPU_ID_VG                        0x1645
>
> Can you see if 0xF14 gives you a reasonable value for the idle mask if
> you add it to amd_pmc_idlemask_read()?  Make a new define for it though,
> it shouldn't use the same define as 0x1a platforms.

It does not work. Reports 0. I also tested the other ones, but the
0x1a was the same as you said. All report 0x0.

Any idea why the OS hint only works 90% of the time?

> >   #define AMD_CPU_ID_YC                       0x14B5
> >   #define AMD_CPU_ID_CB                       0x14D8
> >   #define AMD_CPU_ID_PS                       0x14E8
>
>

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Mario Limonciello]

On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
> <mario.limonciello@amd.com> wrote:
>>
>>
>>
>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>
>>> Since the handler is missing here, this causes the device to not suspend
>>> and the AMD GPU driver to crash while trying to resume afterwards due to
>>> a power hang.
>>>
>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>> ---
>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>    2 files changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>>>        switch (dev->cpu_id) {
>>>        case AMD_CPU_ID_PCO:
>>>        case AMD_CPU_ID_RN:
>>> +     case AMD_CPU_ID_VG:
>>>        case AMD_CPU_ID_YC:
>>>        case AMD_CPU_ID_CB:
>>>                dev->num_ips = 12;
>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
>>>        case AMD_CPU_ID_PCO:
>>>                return MSG_OS_HINT_PCO;
>>>        case AMD_CPU_ID_RN:
>>> +     case AMD_CPU_ID_VG:
>>>        case AMD_CPU_ID_YC:
>>>        case AMD_CPU_ID_CB:
>>>        case AMD_CPU_ID_PS:
>>> @@ -717,6 +719,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>        { }
>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
>>> index 62f3e51020fd..fe3f53eb5955 100644
>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>    #define AMD_CPU_ID_RN                       0x1630
>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>> +#define AMD_CPU_ID_VG                        0x1645
>>
>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>> you add it to amd_pmc_idlemask_read()?  Make a new define for it though,
>> it shouldn't use the same define as 0x1a platforms.
> 
> It does not work. Reports 0. I also tested the other ones, but the
> 0x1a was the same as you said. All report 0x0.

It's possible the platform doesn't report an idle mask.

0xF14 is where I would have expected it to report.

Shyam - can you look into this to see if it's in a different place than 
0xF14 for Van Gogh?

> 
> Any idea why the OS hint only works 90% of the time?

If we get the idle mask reporting working we would have a better idea if 
that is what is reported wrong.

If I was to guess though; maybe GFX is still active.

Depending upon what's going wrong smu_fw_info might have some more 
information too.
> 
>>>    #define AMD_CPU_ID_YC                       0x14B5
>>>    #define AMD_CPU_ID_CB                       0x14D8
>>>    #define AMD_CPU_ID_PS                       0x14E8
>>
>>
> 

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Shyam Sundar S K]

On 10/24/2025 22:02, Mario Limonciello wrote:
> 
> 
> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
>> <mario.limonciello@amd.com> wrote:
>>>
>>>
>>>
>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>>
>>>> Since the handler is missing here, this causes the device to not
>>>> suspend
>>>> and the AMD GPU driver to crash while trying to resume afterwards
>>>> due to
>>>> a power hang.
>>>>
>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>> ---
>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>>    2 files changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
>>>> platform/x86/amd/pmc/pmc.c
>>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
>>>> amd_pmc_dev *dev)
>>>>        switch (dev->cpu_id) {
>>>>        case AMD_CPU_ID_PCO:
>>>>        case AMD_CPU_ID_RN:
>>>> +     case AMD_CPU_ID_VG:
>>>>        case AMD_CPU_ID_YC:
>>>>        case AMD_CPU_ID_CB:
>>>>                dev->num_ips = 12;
>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
>>>> amd_pmc_dev *dev)
>>>>        case AMD_CPU_ID_PCO:
>>>>                return MSG_OS_HINT_PCO;
>>>>        case AMD_CPU_ID_RN:
>>>> +     case AMD_CPU_ID_VG:
>>>>        case AMD_CPU_ID_YC:
>>>>        case AMD_CPU_ID_CB:
>>>>        case AMD_CPU_ID_PS:
>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
>>>> pmc_pci_ids[] = {
>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>>        { }
>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
>>>> platform/x86/amd/pmc/pmc.h
>>>> index 62f3e51020fd..fe3f53eb5955 100644
>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>>    #define AMD_CPU_ID_RN                       0x1630
>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>
>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
>>> though,
>>> it shouldn't use the same define as 0x1a platforms.
>>
>> It does not work. Reports 0. I also tested the other ones, but the
>> 0x1a was the same as you said. All report 0x0.
> 
> It's possible the platform doesn't report an idle mask.
> 
> 0xF14 is where I would have expected it to report.
> 
> Shyam - can you look into this to see if it's in a different place
> than 0xF14 for Van Gogh?

Van Gogh is before Cezzane? I am bit surprised that pmc is getting
loaded there.

Antheas - what is the output of

#lspci -s 00:00.0

0xF14 index is meant for 1Ah (i.e. Strix and above)

> 
>>
>> Any idea why the OS hint only works 90% of the time?

What is the output of amd_pmc_dump_registers() when 10% of the time
when the OS_HINT is not working?

What I can surmise is, though pmc driver is sending the hint PMFW is
not taking any action (since the support in FW is missing)

> 
> If we get the idle mask reporting working we would have a better idea
> if that is what is reported wrong.
> 

IIRC, The concept of idlemask came only after cezzane that too after a
certain PMFW version. So I am not sure if idlemask actually exists.


> If I was to guess though; maybe GFX is still active.
> 
> Depending upon what's going wrong smu_fw_info might have some more
> information too.

That's a good point to try it out.

Thanks,
Shyam

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Antheas Kapenekakis]

On Mon, 27 Oct 2025 at 09:22, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>
>
>
> On 10/24/2025 22:02, Mario Limonciello wrote:
> >
> >
> > On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
> >> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
> >> <mario.limonciello@amd.com> wrote:
> >>>
> >>>
> >>>
> >>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> >>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> >>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> >>>> this support was dropped by the Xbox Ally which only S0ix suspend.
> >>>>
> >>>> Since the handler is missing here, this causes the device to not
> >>>> suspend
> >>>> and the AMD GPU driver to crash while trying to resume afterwards
> >>>> due to
> >>>> a power hang.
> >>>>
> >>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> >>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> >>>> ---
> >>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
> >>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
> >>>>    2 files changed, 4 insertions(+)
> >>>>
> >>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
> >>>> platform/x86/amd/pmc/pmc.c
> >>>> index bd318fd02ccf..cae3fcafd4d7 100644
> >>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
> >>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> >>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
> >>>> amd_pmc_dev *dev)
> >>>>        switch (dev->cpu_id) {
> >>>>        case AMD_CPU_ID_PCO:
> >>>>        case AMD_CPU_ID_RN:
> >>>> +     case AMD_CPU_ID_VG:
> >>>>        case AMD_CPU_ID_YC:
> >>>>        case AMD_CPU_ID_CB:
> >>>>                dev->num_ips = 12;
> >>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
> >>>> amd_pmc_dev *dev)
> >>>>        case AMD_CPU_ID_PCO:
> >>>>                return MSG_OS_HINT_PCO;
> >>>>        case AMD_CPU_ID_RN:
> >>>> +     case AMD_CPU_ID_VG:
> >>>>        case AMD_CPU_ID_YC:
> >>>>        case AMD_CPU_ID_CB:
> >>>>        case AMD_CPU_ID_PS:
> >>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
> >>>> pmc_pci_ids[] = {
> >>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> >>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
> >>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> >>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
> >>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
> >>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
> >>>>        { }
> >>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
> >>>> platform/x86/amd/pmc/pmc.h
> >>>> index 62f3e51020fd..fe3f53eb5955 100644
> >>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
> >>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> >>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
> >>>>    #define AMD_CPU_ID_RN                       0x1630
> >>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
> >>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
> >>>> +#define AMD_CPU_ID_VG                        0x1645
> >>>
> >>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
> >>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
> >>> though,
> >>> it shouldn't use the same define as 0x1a platforms.
> >>
> >> It does not work. Reports 0. I also tested the other ones, but the
> >> 0x1a was the same as you said. All report 0x0.
> >
> > It's possible the platform doesn't report an idle mask.
> >
> > 0xF14 is where I would have expected it to report.
> >
> > Shyam - can you look into this to see if it's in a different place
> > than 0xF14 for Van Gogh?
>
> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> loaded there.

The device only came out last week, so I suppose they had to add it

> Antheas - what is the output of
>
> #lspci -s 00:00.0
>
> 0xF14 index is meant for 1Ah (i.e. Strix and above)

lspci -s 00:00.0 -nn
00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] VanGogh
Root Complex [1022:1645]

> >
> >>
> >> Any idea why the OS hint only works 90% of the time?
>
> What is the output of amd_pmc_dump_registers() when 10% of the time
> when the OS_HINT is not working?

First sleep with initial data:
[   63.569557] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.569581] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:73f
[   63.569597] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:9
[   63.583472] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.583497] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:735677a0
[   63.583513] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:5
[   63.607472] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.607496] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[   63.607512] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:4
[   63.607687] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.607702] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[   63.607709] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:7
[   63.608417] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.608436] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[   63.608452] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:6
[   63.608603] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   63.608621] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:1
[   63.608637] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[   64.764466] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   64.764490] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[   64.764506] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[   64.764631] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[   64.764646] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[   64.764660] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:8

Second sleep (successful):
[  235.211752] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  235.211776] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  235.211790] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:7
[  235.211931] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  235.211946] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  235.211960] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:6
[  235.212083] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  235.212096] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:1
[  235.212109] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[  236.520156] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  236.520177] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  236.520192] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[  236.520330] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  236.520346] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  236.520360] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:8

Failed sleep:
[  152.839926] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  152.839951] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  152.839965] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:7
[  152.840115] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  152.840134] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  152.840148] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:6
[  152.840270] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  152.840276] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:1
[  152.840280] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[  158.037073] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  158.037097] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  158.037111] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:3
[  158.037252] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_RESPONSE:1
[  158.037268] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_ARGUMENT:0
[  158.037282] amd_pmc AMDI0005:00: AMD_PMC_REGISTER_MESSAGE:8

So it is the same

> What I can surmise is, though pmc driver is sending the hint PMFW is
> not taking any action (since the support in FW is missing)

The hint is working... 90% of the time. Without the hint in the patch,
sleep never works.

> >
> > If we get the idle mask reporting working we would have a better idea
> > if that is what is reported wrong.
> >
>
> IIRC, The concept of idlemask came only after cezzane that too after a
> certain PMFW version. So I am not sure if idlemask actually exists.
>
>
> > If I was to guess though; maybe GFX is still active.
> >
> > Depending upon what's going wrong smu_fw_info might have some more
> > information too.
>
> That's a good point to try it out.
>
> Thanks,
> Shyam
>
>

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Shyam Sundar S K]

On 10/27/2025 13:52, Shyam Sundar S K wrote:
> 
> 
> On 10/24/2025 22:02, Mario Limonciello wrote:
>>
>>
>> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
>>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
>>> <mario.limonciello@amd.com> wrote:
>>>>
>>>>
>>>>
>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>>>
>>>>> Since the handler is missing here, this causes the device to not
>>>>> suspend
>>>>> and the AMD GPU driver to crash while trying to resume afterwards
>>>>> due to
>>>>> a power hang.
>>>>>
>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>> ---
>>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>>>    2 files changed, 4 insertions(+)
>>>>>
>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
>>>>> platform/x86/amd/pmc/pmc.c
>>>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
>>>>> amd_pmc_dev *dev)
>>>>>        switch (dev->cpu_id) {
>>>>>        case AMD_CPU_ID_PCO:
>>>>>        case AMD_CPU_ID_RN:
>>>>> +     case AMD_CPU_ID_VG:
>>>>>        case AMD_CPU_ID_YC:
>>>>>        case AMD_CPU_ID_CB:
>>>>>                dev->num_ips = 12;
>>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
>>>>> amd_pmc_dev *dev)
>>>>>        case AMD_CPU_ID_PCO:
>>>>>                return MSG_OS_HINT_PCO;
>>>>>        case AMD_CPU_ID_RN:
>>>>> +     case AMD_CPU_ID_VG:
>>>>>        case AMD_CPU_ID_YC:
>>>>>        case AMD_CPU_ID_CB:
>>>>>        case AMD_CPU_ID_PS:
>>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
>>>>> pmc_pci_ids[] = {
>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>>>        { }
>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
>>>>> platform/x86/amd/pmc/pmc.h
>>>>> index 62f3e51020fd..fe3f53eb5955 100644
>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>>>    #define AMD_CPU_ID_RN                       0x1630
>>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>>
>>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
>>>> though,
>>>> it shouldn't use the same define as 0x1a platforms.
>>>
>>> It does not work. Reports 0. I also tested the other ones, but the
>>> 0x1a was the same as you said. All report 0x0.
>>
>> It's possible the platform doesn't report an idle mask.
>>
>> 0xF14 is where I would have expected it to report.
>>
>> Shyam - can you look into this to see if it's in a different place
>> than 0xF14 for Van Gogh?
> 
> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> loaded there.
> 
> Antheas - what is the output of
> 
> #lspci -s 00:00.0

OK. I get it from the diff.

+#define AMD_CPU_ID_VG                        0x1645

S0 its 0x1645 that indicates SoC is 17h family and 90h model.

What is the PMFW version running on your system?
amd_pmc_get_smu_version() tells you that information.

Can you see if you put the scratch information same as Cezzane and if
that works? i.e.

AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)

Thanks,
Shyam


> 
> 0xF14 index is meant for 1Ah (i.e. Strix and above)
> 
>>
>>>
>>> Any idea why the OS hint only works 90% of the time?
> 
> What is the output of amd_pmc_dump_registers() when 10% of the time
> when the OS_HINT is not working?
> 
> What I can surmise is, though pmc driver is sending the hint PMFW is
> not taking any action (since the support in FW is missing)
> 
>>
>> If we get the idle mask reporting working we would have a better idea
>> if that is what is reported wrong.
>>
> 
> IIRC, The concept of idlemask came only after cezzane that too after a
> certain PMFW version. So I am not sure if idlemask actually exists.
> 
> 
>> If I was to guess though; maybe GFX is still active.
>>
>> Depending upon what's going wrong smu_fw_info might have some more
>> information too.
> 
> That's a good point to try it out.
> 
> Thanks,
> Shyam
> 

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Antheas Kapenekakis]

On Mon, 27 Oct 2025 at 09:36, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>
>
>
> On 10/27/2025 13:52, Shyam Sundar S K wrote:
> >
> >
> > On 10/24/2025 22:02, Mario Limonciello wrote:
> >>
> >>
> >> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
> >>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
> >>> <mario.limonciello@amd.com> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> >>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> >>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> >>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
> >>>>>
> >>>>> Since the handler is missing here, this causes the device to not
> >>>>> suspend
> >>>>> and the AMD GPU driver to crash while trying to resume afterwards
> >>>>> due to
> >>>>> a power hang.
> >>>>>
> >>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> >>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> >>>>> ---
> >>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
> >>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
> >>>>>    2 files changed, 4 insertions(+)
> >>>>>
> >>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
> >>>>> platform/x86/amd/pmc/pmc.c
> >>>>> index bd318fd02ccf..cae3fcafd4d7 100644
> >>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
> >>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> >>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
> >>>>> amd_pmc_dev *dev)
> >>>>>        switch (dev->cpu_id) {
> >>>>>        case AMD_CPU_ID_PCO:
> >>>>>        case AMD_CPU_ID_RN:
> >>>>> +     case AMD_CPU_ID_VG:
> >>>>>        case AMD_CPU_ID_YC:
> >>>>>        case AMD_CPU_ID_CB:
> >>>>>                dev->num_ips = 12;
> >>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
> >>>>> amd_pmc_dev *dev)
> >>>>>        case AMD_CPU_ID_PCO:
> >>>>>                return MSG_OS_HINT_PCO;
> >>>>>        case AMD_CPU_ID_RN:
> >>>>> +     case AMD_CPU_ID_VG:
> >>>>>        case AMD_CPU_ID_YC:
> >>>>>        case AMD_CPU_ID_CB:
> >>>>>        case AMD_CPU_ID_PS:
> >>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
> >>>>> pmc_pci_ids[] = {
> >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
> >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> >>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
> >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
> >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
> >>>>>        { }
> >>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
> >>>>> platform/x86/amd/pmc/pmc.h
> >>>>> index 62f3e51020fd..fe3f53eb5955 100644
> >>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
> >>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> >>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
> >>>>>    #define AMD_CPU_ID_RN                       0x1630
> >>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
> >>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
> >>>>> +#define AMD_CPU_ID_VG                        0x1645
> >>>>
> >>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
> >>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
> >>>> though,
> >>>> it shouldn't use the same define as 0x1a platforms.
> >>>
> >>> It does not work. Reports 0. I also tested the other ones, but the
> >>> 0x1a was the same as you said. All report 0x0.
> >>
> >> It's possible the platform doesn't report an idle mask.
> >>
> >> 0xF14 is where I would have expected it to report.
> >>
> >> Shyam - can you look into this to see if it's in a different place
> >> than 0xF14 for Van Gogh?
> >
> > Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> > loaded there.
> >
> > Antheas - what is the output of
> >
> > #lspci -s 00:00.0
>
> OK. I get it from the diff.
>
> +#define AMD_CPU_ID_VG                        0x1645
>
> S0 its 0x1645 that indicates SoC is 17h family and 90h model.
>
> What is the PMFW version running on your system?
> amd_pmc_get_smu_version() tells you that information.

cat /sys/devices/platform/AMDI0005:00/smu_fw_version
63.18.0
cat /sys/devices/platform/AMDI0005:00/smu_program
7

> Can you see if you put the scratch information same as Cezzane and if
> that works? i.e.
>
> AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)

I tried all idle masks and they return 0

Antheas

> Thanks,
> Shyam
>
>
> >
> > 0xF14 index is meant for 1Ah (i.e. Strix and above)
> >
> >>
> >>>
> >>> Any idea why the OS hint only works 90% of the time?
> >
> > What is the output of amd_pmc_dump_registers() when 10% of the time
> > when the OS_HINT is not working?
> >
> > What I can surmise is, though pmc driver is sending the hint PMFW is
> > not taking any action (since the support in FW is missing)
> >
> >>
> >> If we get the idle mask reporting working we would have a better idea
> >> if that is what is reported wrong.
> >>
> >
> > IIRC, The concept of idlemask came only after cezzane that too after a
> > certain PMFW version. So I am not sure if idlemask actually exists.
> >
> >
> >> If I was to guess though; maybe GFX is still active.
> >>
> >> Depending upon what's going wrong smu_fw_info might have some more
> >> information too.
> >
> > That's a good point to try it out.
> >
> > Thanks,
> > Shyam
> >
>
>

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Ilpo Järvinen]

On Mon, 27 Oct 2025, Antheas Kapenekakis wrote:

> On Mon, 27 Oct 2025 at 09:36, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
> >
> >
> >
> > On 10/27/2025 13:52, Shyam Sundar S K wrote:
> > >
> > >
> > > On 10/24/2025 22:02, Mario Limonciello wrote:
> > >>
> > >>
> > >> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
> > >>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
> > >>> <mario.limonciello@amd.com> wrote:
> > >>>>
> > >>>>
> > >>>>
> > >>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> > >>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> > >>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> > >>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
> > >>>>>
> > >>>>> Since the handler is missing here, this causes the device to not
> > >>>>> suspend
> > >>>>> and the AMD GPU driver to crash while trying to resume afterwards
> > >>>>> due to
> > >>>>> a power hang.
> > >>>>>
> > >>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> > >>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> > >>>>> ---
> > >>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
> > >>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
> > >>>>>    2 files changed, 4 insertions(+)
> > >>>>>
> > >>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
> > >>>>> platform/x86/amd/pmc/pmc.c
> > >>>>> index bd318fd02ccf..cae3fcafd4d7 100644
> > >>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
> > >>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> > >>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
> > >>>>> amd_pmc_dev *dev)
> > >>>>>        switch (dev->cpu_id) {
> > >>>>>        case AMD_CPU_ID_PCO:
> > >>>>>        case AMD_CPU_ID_RN:
> > >>>>> +     case AMD_CPU_ID_VG:
> > >>>>>        case AMD_CPU_ID_YC:
> > >>>>>        case AMD_CPU_ID_CB:
> > >>>>>                dev->num_ips = 12;
> > >>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
> > >>>>> amd_pmc_dev *dev)
> > >>>>>        case AMD_CPU_ID_PCO:
> > >>>>>                return MSG_OS_HINT_PCO;
> > >>>>>        case AMD_CPU_ID_RN:
> > >>>>> +     case AMD_CPU_ID_VG:
> > >>>>>        case AMD_CPU_ID_YC:
> > >>>>>        case AMD_CPU_ID_CB:
> > >>>>>        case AMD_CPU_ID_PS:
> > >>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
> > >>>>> pmc_pci_ids[] = {
> > >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> > >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
> > >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> > >>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
> > >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> > >>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
> > >>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> > >>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
> > >>>>>        { }
> > >>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
> > >>>>> platform/x86/amd/pmc/pmc.h
> > >>>>> index 62f3e51020fd..fe3f53eb5955 100644
> > >>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
> > >>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> > >>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
> > >>>>>    #define AMD_CPU_ID_RN                       0x1630
> > >>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
> > >>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
> > >>>>> +#define AMD_CPU_ID_VG                        0x1645
> > >>>>
> > >>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
> > >>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
> > >>>> though,
> > >>>> it shouldn't use the same define as 0x1a platforms.
> > >>>
> > >>> It does not work. Reports 0. I also tested the other ones, but the
> > >>> 0x1a was the same as you said. All report 0x0.
> > >>
> > >> It's possible the platform doesn't report an idle mask.
> > >>
> > >> 0xF14 is where I would have expected it to report.
> > >>
> > >> Shyam - can you look into this to see if it's in a different place
> > >> than 0xF14 for Van Gogh?
> > >
> > > Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> > > loaded there.
> > >
> > > Antheas - what is the output of
> > >
> > > #lspci -s 00:00.0
> >
> > OK. I get it from the diff.
> >
> > +#define AMD_CPU_ID_VG                        0x1645
> >
> > S0 its 0x1645 that indicates SoC is 17h family and 90h model.
> >
> > What is the PMFW version running on your system?
> > amd_pmc_get_smu_version() tells you that information.
> 
> cat /sys/devices/platform/AMDI0005:00/smu_fw_version
> 63.18.0
> cat /sys/devices/platform/AMDI0005:00/smu_program
> 7
> 
> > Can you see if you put the scratch information same as Cezzane and if
> > that works? i.e.
> >
> > AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)
> 
> I tried all idle masks and they return 0

Hi Shyam & Antheas,

This discussion seems to have died down without clear indication what's 
the best course of action here. Should I still wait?

There's no particular hurry from my side but it seems Mario gave his 
Reviewed-by already and there hasn't been any follow-ups between you two, 
I'm left a bit unsure how to interpret that.


In addition, is the patch 3/3 entire independent from these two PMC ones?
(If yes, I don't know why they were submitted as a series as that just 
manages to add a little bit of uncertainty when combined into a series.)

Thanks in advance,

--
 i.

> Antheas
> 
> > Thanks,
> > Shyam
> >
> >
> > >
> > > 0xF14 index is meant for 1Ah (i.e. Strix and above)
> > >
> > >>
> > >>>
> > >>> Any idea why the OS hint only works 90% of the time?
> > >
> > > What is the output of amd_pmc_dump_registers() when 10% of the time
> > > when the OS_HINT is not working?
> > >
> > > What I can surmise is, though pmc driver is sending the hint PMFW is
> > > not taking any action (since the support in FW is missing)
> > >
> > >>
> > >> If we get the idle mask reporting working we would have a better idea
> > >> if that is what is reported wrong.
> > >>
> > >
> > > IIRC, The concept of idlemask came only after cezzane that too after a
> > > certain PMFW version. So I am not sure if idlemask actually exists.
> > >
> > >
> > >> If I was to guess though; maybe GFX is still active.
> > >>
> > >> Depending upon what's going wrong smu_fw_info might have some more
> > >> information too.
> > >
> > > That's a good point to try it out.
> > >
> > > Thanks,
> > > Shyam
> > >
> >
> >
> 
> 

-- 
 i.

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Shyam Sundar S K]

Hi Ilpo,

On 11/5/2025 16:43, Ilpo Järvinen wrote:
> On Mon, 27 Oct 2025, Antheas Kapenekakis wrote:
> 
>> On Mon, 27 Oct 2025 at 09:36, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>>>
>>>
>>>
>>> On 10/27/2025 13:52, Shyam Sundar S K wrote:
>>>>
>>>>
>>>> On 10/24/2025 22:02, Mario Limonciello wrote:
>>>>>
>>>>>
>>>>> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
>>>>>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
>>>>>> <mario.limonciello@amd.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>>>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>>>>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>>>>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>>>>>>
>>>>>>>> Since the handler is missing here, this causes the device to not
>>>>>>>> suspend
>>>>>>>> and the AMD GPU driver to crash while trying to resume afterwards
>>>>>>>> due to
>>>>>>>> a power hang.
>>>>>>>>
>>>>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>>>>> ---
>>>>>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>>>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>>>>>>    2 files changed, 4 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
>>>>>>>> platform/x86/amd/pmc/pmc.c
>>>>>>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>>>>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
>>>>>>>> amd_pmc_dev *dev)
>>>>>>>>        switch (dev->cpu_id) {
>>>>>>>>        case AMD_CPU_ID_PCO:
>>>>>>>>        case AMD_CPU_ID_RN:
>>>>>>>> +     case AMD_CPU_ID_VG:
>>>>>>>>        case AMD_CPU_ID_YC:
>>>>>>>>        case AMD_CPU_ID_CB:
>>>>>>>>                dev->num_ips = 12;
>>>>>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
>>>>>>>> amd_pmc_dev *dev)
>>>>>>>>        case AMD_CPU_ID_PCO:
>>>>>>>>                return MSG_OS_HINT_PCO;
>>>>>>>>        case AMD_CPU_ID_RN:
>>>>>>>> +     case AMD_CPU_ID_VG:
>>>>>>>>        case AMD_CPU_ID_YC:
>>>>>>>>        case AMD_CPU_ID_CB:
>>>>>>>>        case AMD_CPU_ID_PS:
>>>>>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
>>>>>>>> pmc_pci_ids[] = {
>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>>>>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>>>>>>        { }
>>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
>>>>>>>> platform/x86/amd/pmc/pmc.h
>>>>>>>> index 62f3e51020fd..fe3f53eb5955 100644
>>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>>>>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>>>>>>    #define AMD_CPU_ID_RN                       0x1630
>>>>>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>>>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>>>>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>>>>>
>>>>>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>>>>>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
>>>>>>> though,
>>>>>>> it shouldn't use the same define as 0x1a platforms.
>>>>>>
>>>>>> It does not work. Reports 0. I also tested the other ones, but the
>>>>>> 0x1a was the same as you said. All report 0x0.
>>>>>
>>>>> It's possible the platform doesn't report an idle mask.
>>>>>
>>>>> 0xF14 is where I would have expected it to report.
>>>>>
>>>>> Shyam - can you look into this to see if it's in a different place
>>>>> than 0xF14 for Van Gogh?
>>>>
>>>> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
>>>> loaded there.
>>>>
>>>> Antheas - what is the output of
>>>>
>>>> #lspci -s 00:00.0
>>>
>>> OK. I get it from the diff.
>>>
>>> +#define AMD_CPU_ID_VG                        0x1645
>>>
>>> S0 its 0x1645 that indicates SoC is 17h family and 90h model.
>>>
>>> What is the PMFW version running on your system?
>>> amd_pmc_get_smu_version() tells you that information.
>>
>> cat /sys/devices/platform/AMDI0005:00/smu_fw_version
>> 63.18.0
>> cat /sys/devices/platform/AMDI0005:00/smu_program
>> 7
>>
>>> Can you see if you put the scratch information same as Cezzane and if
>>> that works? i.e.
>>>
>>> AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)
>>
>> I tried all idle masks and they return 0
> 
> Hi Shyam & Antheas,
> 
> This discussion seems to have died down without clear indication what's 
> the best course of action here. Should I still wait?
> 
> There's no particular hurry from my side but it seems Mario gave his 
> Reviewed-by already and there hasn't been any follow-ups between you two, 
> I'm left a bit unsure how to interpret that.
> 

The thought process to was understand how do we debug the rest 5%
failures when we do no not have idlemask concept, which got introduced
after sometime. But both the patches should work independently, so I
am ok with both patch 1/3 and 2/3.

Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>


> 
> In addition, is the patch 3/3 entire independent from these two PMC ones?
> (If yes, I don't know why they were submitted as a series as that just 
> manages to add a little bit of uncertainty when combined into a series.)

I see a note from Mario on the cover letter that the patch 3/3 can be
dropped from this series and a newer approach is being planned.

So, 1/3 and 2/3 of this series can be taken.

Thanks,
Shyam
> 
> Thanks in advance,
> 
> --
>  i.
> 
>> Antheas
>>
>>> Thanks,
>>> Shyam
>>>
>>>
>>>>
>>>> 0xF14 index is meant for 1Ah (i.e. Strix and above)
>>>>
>>>>>
>>>>>>
>>>>>> Any idea why the OS hint only works 90% of the time?
>>>>
>>>> What is the output of amd_pmc_dump_registers() when 10% of the time
>>>> when the OS_HINT is not working?
>>>>
>>>> What I can surmise is, though pmc driver is sending the hint PMFW is
>>>> not taking any action (since the support in FW is missing)
>>>>
>>>>>
>>>>> If we get the idle mask reporting working we would have a better idea
>>>>> if that is what is reported wrong.
>>>>>
>>>>
>>>> IIRC, The concept of idlemask came only after cezzane that too after a
>>>> certain PMFW version. So I am not sure if idlemask actually exists.
>>>>
>>>>
>>>>> If I was to guess though; maybe GFX is still active.
>>>>>
>>>>> Depending upon what's going wrong smu_fw_info might have some more
>>>>> information too.
>>>>
>>>> That's a good point to try it out.
>>>>
>>>> Thanks,
>>>> Shyam
>>>>
>>>
>>>
>>
>>
> 

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Antheas Kapenekakis]

On Wed, 5 Nov 2025 at 12:28, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>
> Hi Ilpo,
>
> On 11/5/2025 16:43, Ilpo Järvinen wrote:
> > On Mon, 27 Oct 2025, Antheas Kapenekakis wrote:
> >
> >> On Mon, 27 Oct 2025 at 09:36, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
> >>>
> >>>
> >>>
> >>> On 10/27/2025 13:52, Shyam Sundar S K wrote:
> >>>>
> >>>>
> >>>> On 10/24/2025 22:02, Mario Limonciello wrote:
> >>>>>
> >>>>>
> >>>>> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
> >>>>>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
> >>>>>> <mario.limonciello@amd.com> wrote:
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> >>>>>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> >>>>>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> >>>>>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
> >>>>>>>>
> >>>>>>>> Since the handler is missing here, this causes the device to not
> >>>>>>>> suspend
> >>>>>>>> and the AMD GPU driver to crash while trying to resume afterwards
> >>>>>>>> due to
> >>>>>>>> a power hang.
> >>>>>>>>
> >>>>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> >>>>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> >>>>>>>> ---
> >>>>>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
> >>>>>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
> >>>>>>>>    2 files changed, 4 insertions(+)
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
> >>>>>>>> platform/x86/amd/pmc/pmc.c
> >>>>>>>> index bd318fd02ccf..cae3fcafd4d7 100644
> >>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
> >>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> >>>>>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
> >>>>>>>> amd_pmc_dev *dev)
> >>>>>>>>        switch (dev->cpu_id) {
> >>>>>>>>        case AMD_CPU_ID_PCO:
> >>>>>>>>        case AMD_CPU_ID_RN:
> >>>>>>>> +     case AMD_CPU_ID_VG:
> >>>>>>>>        case AMD_CPU_ID_YC:
> >>>>>>>>        case AMD_CPU_ID_CB:
> >>>>>>>>                dev->num_ips = 12;
> >>>>>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
> >>>>>>>> amd_pmc_dev *dev)
> >>>>>>>>        case AMD_CPU_ID_PCO:
> >>>>>>>>                return MSG_OS_HINT_PCO;
> >>>>>>>>        case AMD_CPU_ID_RN:
> >>>>>>>> +     case AMD_CPU_ID_VG:
> >>>>>>>>        case AMD_CPU_ID_YC:
> >>>>>>>>        case AMD_CPU_ID_CB:
> >>>>>>>>        case AMD_CPU_ID_PS:
> >>>>>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
> >>>>>>>> pmc_pci_ids[] = {
> >>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> >>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
> >>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> >>>>>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
> >>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>>>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
> >>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
> >>>>>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
> >>>>>>>>        { }
> >>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
> >>>>>>>> platform/x86/amd/pmc/pmc.h
> >>>>>>>> index 62f3e51020fd..fe3f53eb5955 100644
> >>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
> >>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> >>>>>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
> >>>>>>>>    #define AMD_CPU_ID_RN                       0x1630
> >>>>>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
> >>>>>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
> >>>>>>>> +#define AMD_CPU_ID_VG                        0x1645
> >>>>>>>
> >>>>>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
> >>>>>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
> >>>>>>> though,
> >>>>>>> it shouldn't use the same define as 0x1a platforms.
> >>>>>>
> >>>>>> It does not work. Reports 0. I also tested the other ones, but the
> >>>>>> 0x1a was the same as you said. All report 0x0.
> >>>>>
> >>>>> It's possible the platform doesn't report an idle mask.
> >>>>>
> >>>>> 0xF14 is where I would have expected it to report.
> >>>>>
> >>>>> Shyam - can you look into this to see if it's in a different place
> >>>>> than 0xF14 for Van Gogh?
> >>>>
> >>>> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> >>>> loaded there.
> >>>>
> >>>> Antheas - what is the output of
> >>>>
> >>>> #lspci -s 00:00.0
> >>>
> >>> OK. I get it from the diff.
> >>>
> >>> +#define AMD_CPU_ID_VG                        0x1645
> >>>
> >>> S0 its 0x1645 that indicates SoC is 17h family and 90h model.
> >>>
> >>> What is the PMFW version running on your system?
> >>> amd_pmc_get_smu_version() tells you that information.
> >>
> >> cat /sys/devices/platform/AMDI0005:00/smu_fw_version
> >> 63.18.0
> >> cat /sys/devices/platform/AMDI0005:00/smu_program
> >> 7
> >>
> >>> Can you see if you put the scratch information same as Cezzane and if
> >>> that works? i.e.
> >>>
> >>> AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)
> >>
> >> I tried all idle masks and they return 0
> >
> > Hi Shyam & Antheas,
> >
> > This discussion seems to have died down without clear indication what's
> > the best course of action here. Should I still wait?
> >
> > There's no particular hurry from my side but it seems Mario gave his
> > Reviewed-by already and there hasn't been any follow-ups between you two,
> > I'm left a bit unsure how to interpret that.
> >
>
> The thought process to was understand how do we debug the rest 5%
> failures when we do no not have idlemask concept, which got introduced
> after sometime. But both the patches should work independently, so I
> am ok with both patch 1/3 and 2/3.
>
> Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
>
>
> >
> > In addition, is the patch 3/3 entire independent from these two PMC ones?
> > (If yes, I don't know why they were submitted as a series as that just
> > manages to add a little bit of uncertainty when combined into a series.)
>
> I see a note from Mario on the cover letter that the patch 3/3 can be
> dropped from this series and a newer approach is being planned.

To be more specific, patch 3 became two separate patches that went through drm.

For the rare failure, it would be an additional patch (if appropriate)
that does not affect 1 and 2.

Do you have any idea of where the failure for the other 5% of cases
comes from? I noticed that after I hibernated my device and it booted
up, it would never go into LPS0, the OS hint stopped working, would
that be a hint?

Antheas

> So, 1/3 and 2/3 of this series can be taken.
>
> Thanks,
> Shyam
> >
> > Thanks in advance,
> >
> > --
> >  i.
> >
> >> Antheas
> >>
> >>> Thanks,
> >>> Shyam
> >>>
> >>>
> >>>>
> >>>> 0xF14 index is meant for 1Ah (i.e. Strix and above)
> >>>>
> >>>>>
> >>>>>>
> >>>>>> Any idea why the OS hint only works 90% of the time?
> >>>>
> >>>> What is the output of amd_pmc_dump_registers() when 10% of the time
> >>>> when the OS_HINT is not working?
> >>>>
> >>>> What I can surmise is, though pmc driver is sending the hint PMFW is
> >>>> not taking any action (since the support in FW is missing)
> >>>>
> >>>>>
> >>>>> If we get the idle mask reporting working we would have a better idea
> >>>>> if that is what is reported wrong.
> >>>>>
> >>>>
> >>>> IIRC, The concept of idlemask came only after cezzane that too after a
> >>>> certain PMFW version. So I am not sure if idlemask actually exists.
> >>>>
> >>>>
> >>>>> If I was to guess though; maybe GFX is still active.
> >>>>>
> >>>>> Depending upon what's going wrong smu_fw_info might have some more
> >>>>> information too.
> >>>>
> >>>> That's a good point to try it out.
> >>>>
> >>>> Thanks,
> >>>> Shyam
> >>>>
> >>>
> >>>
> >>
> >>
> >
>
>

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Shyam Sundar S K]

On 11/5/2025 17:04, Antheas Kapenekakis wrote:
> On Wed, 5 Nov 2025 at 12:28, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>>
>> Hi Ilpo,
>>
>> On 11/5/2025 16:43, Ilpo Järvinen wrote:
>>> On Mon, 27 Oct 2025, Antheas Kapenekakis wrote:
>>>
>>>> On Mon, 27 Oct 2025 at 09:36, Shyam Sundar S K <Shyam-sundar.S-k@amd.com> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 10/27/2025 13:52, Shyam Sundar S K wrote:
>>>>>>
>>>>>>
>>>>>> On 10/24/2025 22:02, Mario Limonciello wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
>>>>>>>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
>>>>>>>> <mario.limonciello@amd.com> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>>>>>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>>>>>>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>>>>>>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>>>>>>>>
>>>>>>>>>> Since the handler is missing here, this causes the device to not
>>>>>>>>>> suspend
>>>>>>>>>> and the AMD GPU driver to crash while trying to resume afterwards
>>>>>>>>>> due to
>>>>>>>>>> a power hang.
>>>>>>>>>>
>>>>>>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>>>>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>>>>>>> ---
>>>>>>>>>>    drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>>>>>>>>    drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>>>>>>>>    2 files changed, 4 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
>>>>>>>>>> platform/x86/amd/pmc/pmc.c
>>>>>>>>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>>>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>>>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>>>>>>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
>>>>>>>>>> amd_pmc_dev *dev)
>>>>>>>>>>        switch (dev->cpu_id) {
>>>>>>>>>>        case AMD_CPU_ID_PCO:
>>>>>>>>>>        case AMD_CPU_ID_RN:
>>>>>>>>>> +     case AMD_CPU_ID_VG:
>>>>>>>>>>        case AMD_CPU_ID_YC:
>>>>>>>>>>        case AMD_CPU_ID_CB:
>>>>>>>>>>                dev->num_ips = 12;
>>>>>>>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
>>>>>>>>>> amd_pmc_dev *dev)
>>>>>>>>>>        case AMD_CPU_ID_PCO:
>>>>>>>>>>                return MSG_OS_HINT_PCO;
>>>>>>>>>>        case AMD_CPU_ID_RN:
>>>>>>>>>> +     case AMD_CPU_ID_VG:
>>>>>>>>>>        case AMD_CPU_ID_YC:
>>>>>>>>>>        case AMD_CPU_ID_CB:
>>>>>>>>>>        case AMD_CPU_ID_PS:
>>>>>>>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
>>>>>>>>>> pmc_pci_ids[] = {
>>>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>>>>>>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>>>>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>>>>>>>>        { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>>>>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>>>>>>>>        { }
>>>>>>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
>>>>>>>>>> platform/x86/amd/pmc/pmc.h
>>>>>>>>>> index 62f3e51020fd..fe3f53eb5955 100644
>>>>>>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>>>>>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>>>>>>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>>>>>>>>    #define AMD_CPU_ID_RN                       0x1630
>>>>>>>>>>    #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>>>>>>>>    #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>>>>>>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>>>>>>>
>>>>>>>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>>>>>>>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
>>>>>>>>> though,
>>>>>>>>> it shouldn't use the same define as 0x1a platforms.
>>>>>>>>
>>>>>>>> It does not work. Reports 0. I also tested the other ones, but the
>>>>>>>> 0x1a was the same as you said. All report 0x0.
>>>>>>>
>>>>>>> It's possible the platform doesn't report an idle mask.
>>>>>>>
>>>>>>> 0xF14 is where I would have expected it to report.
>>>>>>>
>>>>>>> Shyam - can you look into this to see if it's in a different place
>>>>>>> than 0xF14 for Van Gogh?
>>>>>>
>>>>>> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
>>>>>> loaded there.
>>>>>>
>>>>>> Antheas - what is the output of
>>>>>>
>>>>>> #lspci -s 00:00.0
>>>>>
>>>>> OK. I get it from the diff.
>>>>>
>>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>>>
>>>>> S0 its 0x1645 that indicates SoC is 17h family and 90h model.
>>>>>
>>>>> What is the PMFW version running on your system?
>>>>> amd_pmc_get_smu_version() tells you that information.
>>>>
>>>> cat /sys/devices/platform/AMDI0005:00/smu_fw_version
>>>> 63.18.0
>>>> cat /sys/devices/platform/AMDI0005:00/smu_program
>>>> 7
>>>>
>>>>> Can you see if you put the scratch information same as Cezzane and if
>>>>> that works? i.e.
>>>>>
>>>>> AMD_PMC_SCRATCH_REG_CZN(0x94) instead of AMD_PMC_SCRATCH_REG_1AH(0xF14)
>>>>
>>>> I tried all idle masks and they return 0
>>>
>>> Hi Shyam & Antheas,
>>>
>>> This discussion seems to have died down without clear indication what's
>>> the best course of action here. Should I still wait?
>>>
>>> There's no particular hurry from my side but it seems Mario gave his
>>> Reviewed-by already and there hasn't been any follow-ups between you two,
>>> I'm left a bit unsure how to interpret that.
>>>
>>
>> The thought process to was understand how do we debug the rest 5%
>> failures when we do no not have idlemask concept, which got introduced
>> after sometime. But both the patches should work independently, so I
>> am ok with both patch 1/3 and 2/3.
>>
>> Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
>>
>>
>>>
>>> In addition, is the patch 3/3 entire independent from these two PMC ones?
>>> (If yes, I don't know why they were submitted as a series as that just
>>> manages to add a little bit of uncertainty when combined into a series.)
>>
>> I see a note from Mario on the cover letter that the patch 3/3 can be
>> dropped from this series and a newer approach is being planned.
> 
> To be more specific, patch 3 became two separate patches that went through drm.
> 
> For the rare failure, it would be an additional patch (if appropriate)
> that does not affect 1 and 2.
> 
> Do you have any idea of where the failure for the other 5% of cases
> comes from? I noticed that after I hibernated my device and it booted
> up, it would never go into LPS0, the OS hint stopped working, would
> that be a hint?

Possibly. If the PMC driver did send the hint but the PMFW didn’t act
on it, that could explain it. However, your earlier logs don’t
indicate that, and the PMFW response register shows success, so I am
unsure about it.

Thanks,
Shyam

> 
> Antheas
> 
>> So, 1/3 and 2/3 of this series can be taken.
>>
>> Thanks,
>> Shyam
>>>
>>> Thanks in advance,
>>>
>>> --
>>>  i.
>>>
>>>> Antheas
>>>>
>>>>> Thanks,
>>>>> Shyam
>>>>>
>>>>>
>>>>>>
>>>>>> 0xF14 index is meant for 1Ah (i.e. Strix and above)
>>>>>>
>>>>>>>
>>>>>>>>
>>>>>>>> Any idea why the OS hint only works 90% of the time?
>>>>>>
>>>>>> What is the output of amd_pmc_dump_registers() when 10% of the time
>>>>>> when the OS_HINT is not working?
>>>>>>
>>>>>> What I can surmise is, though pmc driver is sending the hint PMFW is
>>>>>> not taking any action (since the support in FW is missing)
>>>>>>
>>>>>>>
>>>>>>> If we get the idle mask reporting working we would have a better idea
>>>>>>> if that is what is reported wrong.
>>>>>>>
>>>>>>
>>>>>> IIRC, The concept of idlemask came only after cezzane that too after a
>>>>>> certain PMFW version. So I am not sure if idlemask actually exists.
>>>>>>
>>>>>>
>>>>>>> If I was to guess though; maybe GFX is still active.
>>>>>>>
>>>>>>> Depending upon what's going wrong smu_fw_info might have some more
>>>>>>> information too.
>>>>>>
>>>>>> That's a good point to try it out.
>>>>>>
>>>>>> Thanks,
>>>>>> Shyam
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>
>>
> 

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Mario Limonciello]

On 10/27/25 3:22 AM, Shyam Sundar S K wrote:
> 
> 
> On 10/24/2025 22:02, Mario Limonciello wrote:
>>
>>
>> On 10/24/2025 11:08 AM, Antheas Kapenekakis wrote:
>>> On Fri, 24 Oct 2025 at 17:43, Mario Limonciello
>>> <mario.limonciello@amd.com> wrote:
>>>>
>>>>
>>>>
>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>>> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
>>>>> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
>>>>> this support was dropped by the Xbox Ally which only S0ix suspend.
>>>>>
>>>>> Since the handler is missing here, this causes the device to not
>>>>> suspend
>>>>> and the AMD GPU driver to crash while trying to resume afterwards
>>>>> due to
>>>>> a power hang.
>>>>>
>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>> ---
>>>>>     drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>>>>>     drivers/platform/x86/amd/pmc/pmc.h | 1 +
>>>>>     2 files changed, 4 insertions(+)
>>>>>
>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/
>>>>> platform/x86/amd/pmc/pmc.c
>>>>> index bd318fd02ccf..cae3fcafd4d7 100644
>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>>>>> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct
>>>>> amd_pmc_dev *dev)
>>>>>         switch (dev->cpu_id) {
>>>>>         case AMD_CPU_ID_PCO:
>>>>>         case AMD_CPU_ID_RN:
>>>>> +     case AMD_CPU_ID_VG:
>>>>>         case AMD_CPU_ID_YC:
>>>>>         case AMD_CPU_ID_CB:
>>>>>                 dev->num_ips = 12;
>>>>> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct
>>>>> amd_pmc_dev *dev)
>>>>>         case AMD_CPU_ID_PCO:
>>>>>                 return MSG_OS_HINT_PCO;
>>>>>         case AMD_CPU_ID_RN:
>>>>> +     case AMD_CPU_ID_VG:
>>>>>         case AMD_CPU_ID_YC:
>>>>>         case AMD_CPU_ID_CB:
>>>>>         case AMD_CPU_ID_PS:
>>>>> @@ -717,6 +719,7 @@ static const struct pci_device_id
>>>>> pmc_pci_ids[] = {
>>>>>         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>>>>>         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>>>>>         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
>>>>> +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>>>>>         { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>> PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>>>>>         { PCI_DEVICE(PCI_VENDOR_ID_AMD,
>>>>> PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>>>>>         { }
>>>>> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/
>>>>> platform/x86/amd/pmc/pmc.h
>>>>> index 62f3e51020fd..fe3f53eb5955 100644
>>>>> --- a/drivers/platform/x86/amd/pmc/pmc.h
>>>>> +++ b/drivers/platform/x86/amd/pmc/pmc.h
>>>>> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>>>>>     #define AMD_CPU_ID_RN                       0x1630
>>>>>     #define AMD_CPU_ID_PCO                      AMD_CPU_ID_RV
>>>>>     #define AMD_CPU_ID_CZN                      AMD_CPU_ID_RN
>>>>> +#define AMD_CPU_ID_VG                        0x1645
>>>>
>>>> Can you see if 0xF14 gives you a reasonable value for the idle mask if
>>>> you add it to amd_pmc_idlemask_read()?  Make a new define for it
>>>> though,
>>>> it shouldn't use the same define as 0x1a platforms.
>>>
>>> It does not work. Reports 0. I also tested the other ones, but the
>>> 0x1a was the same as you said. All report 0x0.
>>
>> It's possible the platform doesn't report an idle mask.
>>
>> 0xF14 is where I would have expected it to report.
>>
>> Shyam - can you look into this to see if it's in a different place
>> than 0xF14 for Van Gogh?
> 
> Van Gogh is before Cezzane? I am bit surprised that pmc is getting
> loaded there.

IIRC the first Van Gogh parts actually came after Cezanne.  Around 
Rembrandt timeframe.  But nothing used s2idle at that time.  So I wasn't 
sure whether idle mask support was present.

I think that the Xbox Ally X is the first Van Gogh based part that has 
s2idle support.  My wonder was if idle mask reading made it into the 
updated PMFW on the Xbox Ally X but the offset was wrong.
> 
> Antheas - what is the output of
> 
> #lspci -s 00:00.0
> 
> 0xF14 index is meant for 1Ah (i.e. Strix and above)
> 
>>
>>>
>>> Any idea why the OS hint only works 90% of the time?
> 
> What is the output of amd_pmc_dump_registers() when 10% of the time
> when the OS_HINT is not working?
> 
> What I can surmise is, though pmc driver is sending the hint PMFW is
> not taking any action (since the support in FW is missing)
> 
>>
>> If we get the idle mask reporting working we would have a better idea
>> if that is what is reported wrong.
>>
> 
> IIRC, The concept of idlemask came only after cezzane that too after a
> certain PMFW version. So I am not sure if idlemask actually exists.
> 
> 
>> If I was to guess though; maybe GFX is still active.
>>
>> Depending upon what's going wrong smu_fw_info might have some more
>> information too.
> 
> That's a good point to try it out.
> 
> Thanks,
> Shyam
> 

Re: [PATCH v1 1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC

[Mario Limonciello (AMD) (kernel.org)]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> The ROG Xbox Ally (non-X) SoC features a similar architecture to the
> Steam Deck. While the Steam Deck supports S3 (s2idle causes a crash),
> this support was dropped by the Xbox Ally which only S0ix suspend.
> 
> Since the handler is missing here, this causes the device to not suspend
> and the AMD GPU driver to crash while trying to resume afterwards due to
> a power hang.
> 
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>

Having seen that a few things were tried for the idle mask which don't 
work I think this patch makes sense as is.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>

> ---
>   drivers/platform/x86/amd/pmc/pmc.c | 3 +++
>   drivers/platform/x86/amd/pmc/pmc.h | 1 +
>   2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index bd318fd02ccf..cae3fcafd4d7 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -106,6 +106,7 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>   	switch (dev->cpu_id) {
>   	case AMD_CPU_ID_PCO:
>   	case AMD_CPU_ID_RN:
> +	case AMD_CPU_ID_VG:
>   	case AMD_CPU_ID_YC:
>   	case AMD_CPU_ID_CB:
>   		dev->num_ips = 12;
> @@ -517,6 +518,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
>   	case AMD_CPU_ID_PCO:
>   		return MSG_OS_HINT_PCO;
>   	case AMD_CPU_ID_RN:
> +	case AMD_CPU_ID_VG:
>   	case AMD_CPU_ID_YC:
>   	case AMD_CPU_ID_CB:
>   	case AMD_CPU_ID_PS:
> @@ -717,6 +719,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
> +	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
>   	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
>   	{ }
> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
> index 62f3e51020fd..fe3f53eb5955 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.h
> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> @@ -156,6 +156,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>   #define AMD_CPU_ID_RN			0x1630
>   #define AMD_CPU_ID_PCO			AMD_CPU_ID_RV
>   #define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
> +#define AMD_CPU_ID_VG			0x1645
>   #define AMD_CPU_ID_YC			0x14B5
>   #define AMD_CPU_ID_CB			0x14D8
>   #define AMD_CPU_ID_PS			0x14E8

[PATCH v1 2/3] platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally

[Antheas Kapenekakis]

The Xbox Ally features a Van Gogh SoC that has spurious interrupts
during resume. We get the following logs:

atkbd_receive_byte: 20 callbacks suppressed
atkbd serio0: Spurious ACK on isa0060/serio0. Some program might be trying to access hardware directly.

So, add the spurious_8042 quirk for it. It does not have a keyboard, so
this does not result in any functional loss.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
---
 drivers/platform/x86/amd/pmc/pmc-quirks.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/platform/x86/amd/pmc/pmc-quirks.c b/drivers/platform/x86/amd/pmc/pmc-quirks.c
index d63aaad7ef59..eb641ce0e982 100644
--- a/drivers/platform/x86/amd/pmc/pmc-quirks.c
+++ b/drivers/platform/x86/amd/pmc/pmc-quirks.c
@@ -122,6 +122,14 @@ static const struct dmi_system_id fwbug_list[] = {
 			DMI_MATCH(DMI_PRODUCT_NAME, "21A1"),
 		}
 	},
+	{
+		.ident = "ROG Xbox Ally RC73YA",
+		.driver_data = &quirk_spurious_8042,
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "RC73YA"),
+		}
+	},
 	/* https://bugzilla.kernel.org/show_bug.cgi?id=218024 */
 	{
 		.ident = "V14 G4 AMN",
-- 
2.51.0

Re: [PATCH v1 2/3] platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally

[Mario Limonciello (AMD) (kernel.org)]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> The Xbox Ally features a Van Gogh SoC that has spurious interrupts
> during resume. We get the following logs:
> 
> atkbd_receive_byte: 20 callbacks suppressed
> atkbd serio0: Spurious ACK on isa0060/serio0. Some program might be trying to access hardware directly.
> 
> So, add the spurious_8042 quirk for it. It does not have a keyboard, so
> this does not result in any functional loss.
> 
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>> ---
>   drivers/platform/x86/amd/pmc/pmc-quirks.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/platform/x86/amd/pmc/pmc-quirks.c b/drivers/platform/x86/amd/pmc/pmc-quirks.c
> index d63aaad7ef59..eb641ce0e982 100644
> --- a/drivers/platform/x86/amd/pmc/pmc-quirks.c
> +++ b/drivers/platform/x86/amd/pmc/pmc-quirks.c
> @@ -122,6 +122,14 @@ static const struct dmi_system_id fwbug_list[] = {
>   			DMI_MATCH(DMI_PRODUCT_NAME, "21A1"),
>   		}
>   	},
> +	{
> +		.ident = "ROG Xbox Ally RC73YA",
> +		.driver_data = &quirk_spurious_8042,
> +		.matches = {
> +			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
> +			DMI_MATCH(DMI_BOARD_NAME, "RC73YA"),
> +		}
> +	},
>   	/* https://bugzilla.kernel.org/show_bug.cgi?id=218024 */
>   	{
>   		.ident = "V14 G4 AMN",

[PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Antheas Kapenekakis]

From: Alex Deucher <alexander.deucher@amd.com>

For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
skip powering it down and skip part of post-init.

Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification on Vangogh")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3d032c4e2dce..220b12d59795 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
 	if (amdgpu_sriov_vf(adev))
 		amdgpu_virt_release_full_gpu(adev, false);
 
-	r = amdgpu_dpm_notify_rlc_state(adev, false);
-	if (r)
-		return r;
+	if (!adev->in_s0ix) {
+		r = amdgpu_dpm_notify_rlc_state(adev, false);
+		if (r)
+			return r;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fb8086859857..244b8c364d45 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context *smu)
 	    smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
 		return 0;
 
+	/* vangogh s0ix */
+	if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
+	     amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) &&
+	    adev->in_s0ix)
+		return 0;
+
 	/*
 	 * For gpu reset, runpm and hibernation through BACO,
 	 * BACO feature has to be kept enabled.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 2c9869feba61..0708d0f0938b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct smu_context *smu)
 	uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
 		adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
 
+	if (adev->in_s0ix)
+		return 0;
+
 	/* allow message will be sent after enable message on Vangogh*/
 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 			(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
-- 
2.51.0

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Mario Limonciello]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> From: Alex Deucher <alexander.deucher@amd.com>
> 
> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
> skip powering it down and skip part of post-init.
> 
> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification on Vangogh")
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>   3 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3d032c4e2dce..220b12d59795 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
>   	if (amdgpu_sriov_vf(adev))
>   		amdgpu_virt_release_full_gpu(adev, false);
>   
> -	r = amdgpu_dpm_notify_rlc_state(adev, false);
> -	if (r)
> -		return r;
> +	if (!adev->in_s0ix) {
> +		r = amdgpu_dpm_notify_rlc_state(adev, false);
> +		if (r)
> +			return r;
> +	}

Just FYI this is going to clash with my unwind failed suspend series [1].

This is fine, just whichever "lands" first the other will need to rework 
a little bit and I wanted to mention it.

Link: 
https://lore.kernel.org/amd-gfx/20251023165243.317153-2-mario.limonciello@amd.com/ 
[1]

This does have me wondering though why amdgpu_dpm_notify_rlc_state() is 
even in amdgpu_device_suspend()?  This is only used on Van Gogh.
Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?

Or should we maybe overhaul this to move the RLC notification into a 
.set_mp1_state callback instead so it's more similar to all the other ASICs?

>   
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index fb8086859857..244b8c364d45 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context *smu)
>   	    smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
>   		return 0;
>   
> +	/* vangogh s0ix */
> +	if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
> +	     amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) &&
> +	    adev->in_s0ix)
> +		return 0;
> +

How about for GPU reset, does PMFW handle this too?

>   	/*
>   	 * For gpu reset, runpm and hibernation through BACO,
>   	 * BACO feature has to be kept enabled.
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 2c9869feba61..0708d0f0938b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct smu_context *smu)
>   	uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
>   		adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
>   
> +	if (adev->in_s0ix)
> +		return 0;
> +
>   	/* allow message will be sent after enable message on Vangogh*/
>   	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
>   			(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Alex Deucher]

On Fri, Oct 24, 2025 at 11:54 AM Mario Limonciello
<mario.limonciello@amd.com> wrote:
>
>
>
> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> > From: Alex Deucher <alexander.deucher@amd.com>
> >
> > For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
> > skip powering it down and skip part of post-init.
> >
> > Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification on Vangogh")
> > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
> > Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
> >   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> >   3 files changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 3d032c4e2dce..220b12d59795 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
> >       if (amdgpu_sriov_vf(adev))
> >               amdgpu_virt_release_full_gpu(adev, false);
> >
> > -     r = amdgpu_dpm_notify_rlc_state(adev, false);
> > -     if (r)
> > -             return r;
> > +     if (!adev->in_s0ix) {
> > +             r = amdgpu_dpm_notify_rlc_state(adev, false);
> > +             if (r)
> > +                     return r;
> > +     }
>
> Just FYI this is going to clash with my unwind failed suspend series [1].
>
> This is fine, just whichever "lands" first the other will need to rework
> a little bit and I wanted to mention it.
>
> Link:
> https://lore.kernel.org/amd-gfx/20251023165243.317153-2-mario.limonciello@amd.com/
> [1]
>
> This does have me wondering though why amdgpu_dpm_notify_rlc_state() is
> even in amdgpu_device_suspend()?  This is only used on Van Gogh.
> Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
>
> Or should we maybe overhaul this to move the RLC notification into a
> .set_mp1_state callback instead so it's more similar to all the other ASICs?
>

TBH, I don't think this is even required at all here.  The rlc is
stopped in smu_disable_dpms() and we already notify the SMU at that
point.  Notifying it again here seems superfluous.  Would need to test
that removing this one doesn't cause an issue with S3.

> >
> >       return 0;
> >   }
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index fb8086859857..244b8c364d45 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context *smu)
> >           smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
> >               return 0;
> >
> > +     /* vangogh s0ix */
> > +     if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
> > +          amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) &&
> > +         adev->in_s0ix)
> > +             return 0;
> > +
>
> How about for GPU reset, does PMFW handle this too?

I'm not 100% sure.  We need to check with the PMFW team.  I think
vangogh works the same as gfx11 and newer APUs since the s0i3
implementation was more aligned with those chips than RMB.  These
special code paths were added specifically for S3 enablement since the
behavior is different relative to S0ix.

Alex

>
> >       /*
> >        * For gpu reset, runpm and hibernation through BACO,
> >        * BACO feature has to be kept enabled.
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > index 2c9869feba61..0708d0f0938b 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct smu_context *smu)
> >       uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
> >               adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
> >
> > +     if (adev->in_s0ix)
> > +             return 0;
> > +
> >       /* allow message will be sent after enable message on Vangogh*/
> >       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
> >                       (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
>

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Mario Limonciello]

On 10/24/2025 10:54 AM, Mario Limonciello wrote:
> 
> 
> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>> From: Alex Deucher <alexander.deucher@amd.com>
>>
>> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
>> skip powering it down and skip part of post-init.
>>
>> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification 
>> on Vangogh")
>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>>   3 files changed, 14 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/ 
>> drm/amd/amdgpu/amdgpu_device.c
>> index 3d032c4e2dce..220b12d59795 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device 
>> *dev, bool notify_clients)
>>       if (amdgpu_sriov_vf(adev))
>>           amdgpu_virt_release_full_gpu(adev, false);
>> -    r = amdgpu_dpm_notify_rlc_state(adev, false);
>> -    if (r)
>> -        return r;
>> +    if (!adev->in_s0ix) {
>> +        r = amdgpu_dpm_notify_rlc_state(adev, false);
>> +        if (r)
>> +            return r;
>> +    }
> 
> Just FYI this is going to clash with my unwind failed suspend series [1].
> 
> This is fine, just whichever "lands" first the other will need to rework 
> a little bit and I wanted to mention it.
> 
> Link: https://lore.kernel.org/amd-gfx/20251023165243.317153-2- 
> mario.limonciello@amd.com/ [1]
> 
> This does have me wondering though why amdgpu_dpm_notify_rlc_state() is 
> even in amdgpu_device_suspend()?  This is only used on Van Gogh.
> Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
> 
> Or should we maybe overhaul this to move the RLC notification into 
> a .set_mp1_state callback instead so it's more similar to all the other 
> ASICs?
> 

My proposal as such is here:

https://lore.kernel.org/amd-gfx/20251024161216.345691-1-mario.limonciello@amd.com/

It would need some testing though to make sure it didn't break Steam 
Deck or Steam Deck OLED.

>>       return 0;
>>   }
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/ 
>> drm/amd/pm/swsmu/amdgpu_smu.c
>> index fb8086859857..244b8c364d45 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context 
>> *smu)
>>           smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
>>           return 0;
>> +    /* vangogh s0ix */
>> +    if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
>> +         amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 
>> 2)) &&
>> +        adev->in_s0ix)
>> +        return 0;
>> +
> 
> How about for GPU reset, does PMFW handle this too?
> 
>>       /*
>>        * For gpu reset, runpm and hibernation through BACO,
>>        * BACO feature has to be kept enabled.
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/ 
>> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>> index 2c9869feba61..0708d0f0938b 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct 
>> smu_context *smu)
>>       uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
>>           adev->gfx.config.max_sh_per_se * adev- 
>> >gfx.config.max_shader_engines;
>> +    if (adev->in_s0ix)
>> +        return 0;
>> +
>>       /* allow message will be sent after enable message on Vangogh*/
>>       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
>>               (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> 

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Antheas Kapenekakis]

On Fri, 24 Oct 2025 at 18:20, Mario Limonciello
<mario.limonciello@amd.com> wrote:
>
>
>
> On 10/24/2025 10:54 AM, Mario Limonciello wrote:
> >
> >
> > On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> >> From: Alex Deucher <alexander.deucher@amd.com>
> >>
> >> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
> >> skip powering it down and skip part of post-init.
> >>
> >> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification
> >> on Vangogh")
> >> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
> >> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
> >>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
> >>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> >>   3 files changed, 14 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/
> >> drm/amd/amdgpu/amdgpu_device.c
> >> index 3d032c4e2dce..220b12d59795 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device
> >> *dev, bool notify_clients)
> >>       if (amdgpu_sriov_vf(adev))
> >>           amdgpu_virt_release_full_gpu(adev, false);
> >> -    r = amdgpu_dpm_notify_rlc_state(adev, false);
> >> -    if (r)
> >> -        return r;
> >> +    if (!adev->in_s0ix) {
> >> +        r = amdgpu_dpm_notify_rlc_state(adev, false);
> >> +        if (r)
> >> +            return r;
> >> +    }
> >
> > Just FYI this is going to clash with my unwind failed suspend series [1].
> >
> > This is fine, just whichever "lands" first the other will need to rework
> > a little bit and I wanted to mention it.
> >
> > Link: https://lore.kernel.org/amd-gfx/20251023165243.317153-2-
> > mario.limonciello@amd.com/ [1]
> >
> > This does have me wondering though why amdgpu_dpm_notify_rlc_state() is
> > even in amdgpu_device_suspend()?  This is only used on Van Gogh.
> > Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
> >
> > Or should we maybe overhaul this to move the RLC notification into
> > a .set_mp1_state callback instead so it's more similar to all the other
> > ASICs?
> >
>
> My proposal as such is here:
>
> https://lore.kernel.org/amd-gfx/20251024161216.345691-1-mario.limonciello@amd.com/
>
> It would need some testing though to make sure it didn't break Steam
> Deck or Steam Deck OLED.

I will give it a quick go on my OLED.


> >>       return 0;
> >>   }
> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/
> >> drm/amd/pm/swsmu/amdgpu_smu.c
> >> index fb8086859857..244b8c364d45 100644
> >> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context
> >> *smu)
> >>           smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
> >>           return 0;
> >> +    /* vangogh s0ix */
> >> +    if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
> >> +         amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5,
> >> 2)) &&
> >> +        adev->in_s0ix)
> >> +        return 0;
> >> +
> >
> > How about for GPU reset, does PMFW handle this too?
> >
> >>       /*
> >>        * For gpu reset, runpm and hibernation through BACO,
> >>        * BACO feature has to be kept enabled.
> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/
> >> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >> index 2c9869feba61..0708d0f0938b 100644
> >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct
> >> smu_context *smu)
> >>       uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
> >>           adev->gfx.config.max_sh_per_se * adev-
> >> >gfx.config.max_shader_engines;
> >> +    if (adev->in_s0ix)
> >> +        return 0;
> >> +
> >>       /* allow message will be sent after enable message on Vangogh*/
> >>       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
> >>               (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> >
>
>

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Antheas Kapenekakis]

On Fri, 24 Oct 2025 at 18:24, Antheas Kapenekakis <lkml@antheas.dev> wrote:
>
> On Fri, 24 Oct 2025 at 18:20, Mario Limonciello
> <mario.limonciello@amd.com> wrote:
> >
> >
> >
> > On 10/24/2025 10:54 AM, Mario Limonciello wrote:
> > >
> > >
> > > On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> > >> From: Alex Deucher <alexander.deucher@amd.com>
> > >>
> > >> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
> > >> skip powering it down and skip part of post-init.
> > >>
> > >> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification
> > >> on Vangogh")
> > >> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> > >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > >> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
> > >> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> > >> ---
> > >>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
> > >>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
> > >>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> > >>   3 files changed, 14 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/
> > >> drm/amd/amdgpu/amdgpu_device.c
> > >> index 3d032c4e2dce..220b12d59795 100644
> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > >> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device
> > >> *dev, bool notify_clients)
> > >>       if (amdgpu_sriov_vf(adev))
> > >>           amdgpu_virt_release_full_gpu(adev, false);
> > >> -    r = amdgpu_dpm_notify_rlc_state(adev, false);
> > >> -    if (r)
> > >> -        return r;
> > >> +    if (!adev->in_s0ix) {
> > >> +        r = amdgpu_dpm_notify_rlc_state(adev, false);
> > >> +        if (r)
> > >> +            return r;
> > >> +    }
> > >
> > > Just FYI this is going to clash with my unwind failed suspend series [1].
> > >
> > > This is fine, just whichever "lands" first the other will need to rework
> > > a little bit and I wanted to mention it.
> > >
> > > Link: https://lore.kernel.org/amd-gfx/20251023165243.317153-2-
> > > mario.limonciello@amd.com/ [1]
> > >
> > > This does have me wondering though why amdgpu_dpm_notify_rlc_state() is
> > > even in amdgpu_device_suspend()?  This is only used on Van Gogh.
> > > Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
> > >
> > > Or should we maybe overhaul this to move the RLC notification into
> > > a .set_mp1_state callback instead so it's more similar to all the other
> > > ASICs?
> > >
> >
> > My proposal as such is here:
> >
> > https://lore.kernel.org/amd-gfx/20251024161216.345691-1-mario.limonciello@amd.com/
> >
> > It would need some testing though to make sure it didn't break Steam
> > Deck or Steam Deck OLED.
>
> I will give it a quick go on my OLED.

Horribly broken. Did not enter S3 and when waking up fan maxed out and
it bootlooped. Journalctl stops on suspend entry. It works on the Xbox
ally though

My series works on both


>
> > >>       return 0;
> > >>   }
> > >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/
> > >> drm/amd/pm/swsmu/amdgpu_smu.c
> > >> index fb8086859857..244b8c364d45 100644
> > >> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > >> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > >> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context
> > >> *smu)
> > >>           smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
> > >>           return 0;
> > >> +    /* vangogh s0ix */
> > >> +    if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
> > >> +         amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5,
> > >> 2)) &&
> > >> +        adev->in_s0ix)
> > >> +        return 0;
> > >> +
> > >
> > > How about for GPU reset, does PMFW handle this too?
> > >
> > >>       /*
> > >>        * For gpu reset, runpm and hibernation through BACO,
> > >>        * BACO feature has to be kept enabled.
> > >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/
> > >> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > >> index 2c9869feba61..0708d0f0938b 100644
> > >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > >> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct
> > >> smu_context *smu)
> > >>       uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
> > >>           adev->gfx.config.max_sh_per_se * adev-
> > >> >gfx.config.max_shader_engines;
> > >> +    if (adev->in_s0ix)
> > >> +        return 0;
> > >> +
> > >>       /* allow message will be sent after enable message on Vangogh*/
> > >>       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
> > >>               (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> > >
> >
> >

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Mario Limonciello]

On 10/24/2025 11:45 AM, Antheas Kapenekakis wrote:
> On Fri, 24 Oct 2025 at 18:24, Antheas Kapenekakis <lkml@antheas.dev> wrote:
>>
>> On Fri, 24 Oct 2025 at 18:20, Mario Limonciello
>> <mario.limonciello@amd.com> wrote:
>>>
>>>
>>>
>>> On 10/24/2025 10:54 AM, Mario Limonciello wrote:
>>>>
>>>>
>>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>>>> From: Alex Deucher <alexander.deucher@amd.com>
>>>>>
>>>>> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
>>>>> skip powering it down and skip part of post-init.
>>>>>
>>>>> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification
>>>>> on Vangogh")
>>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
>>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>>>> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
>>>>> ---
>>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>>>>>    drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>>>>>    drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>>>>>    3 files changed, 14 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/
>>>>> drm/amd/amdgpu/amdgpu_device.c
>>>>> index 3d032c4e2dce..220b12d59795 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>>> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device
>>>>> *dev, bool notify_clients)
>>>>>        if (amdgpu_sriov_vf(adev))
>>>>>            amdgpu_virt_release_full_gpu(adev, false);
>>>>> -    r = amdgpu_dpm_notify_rlc_state(adev, false);
>>>>> -    if (r)
>>>>> -        return r;
>>>>> +    if (!adev->in_s0ix) {
>>>>> +        r = amdgpu_dpm_notify_rlc_state(adev, false);
>>>>> +        if (r)
>>>>> +            return r;
>>>>> +    }
>>>>
>>>> Just FYI this is going to clash with my unwind failed suspend series [1].
>>>>
>>>> This is fine, just whichever "lands" first the other will need to rework
>>>> a little bit and I wanted to mention it.
>>>>
>>>> Link: https://lore.kernel.org/amd-gfx/20251023165243.317153-2-
>>>> mario.limonciello@amd.com/ [1]
>>>>
>>>> This does have me wondering though why amdgpu_dpm_notify_rlc_state() is
>>>> even in amdgpu_device_suspend()?  This is only used on Van Gogh.
>>>> Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
>>>>
>>>> Or should we maybe overhaul this to move the RLC notification into
>>>> a .set_mp1_state callback instead so it's more similar to all the other
>>>> ASICs?
>>>>
>>>
>>> My proposal as such is here:
>>>
>>> https://lore.kernel.org/amd-gfx/20251024161216.345691-1-mario.limonciello@amd.com/
>>>
>>> It would need some testing though to make sure it didn't break Steam
>>> Deck or Steam Deck OLED.
>>
>> I will give it a quick go on my OLED.
> 
> Horribly broken. Did not enter S3 and when waking up fan maxed out and
> it bootlooped. Journalctl stops on suspend entry. It works on the Xbox
> ally though
> 
> My series works on both

OK.

Can you try Alex's idea instead?  Just comment out the RLC notification 
code in amdgpu_device_suspend().

It's supposed to already be called in smu_disable_dpms() anyway.

> 
> 
>>
>>>>>        return 0;
>>>>>    }
>>>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/
>>>>> drm/amd/pm/swsmu/amdgpu_smu.c
>>>>> index fb8086859857..244b8c364d45 100644
>>>>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>>>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>>>>> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context
>>>>> *smu)
>>>>>            smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
>>>>>            return 0;
>>>>> +    /* vangogh s0ix */
>>>>> +    if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
>>>>> +         amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5,
>>>>> 2)) &&
>>>>> +        adev->in_s0ix)
>>>>> +        return 0;
>>>>> +
>>>>
>>>> How about for GPU reset, does PMFW handle this too?
>>>>
>>>>>        /*
>>>>>         * For gpu reset, runpm and hibernation through BACO,
>>>>>         * BACO feature has to be kept enabled.
>>>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/
>>>>> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>>>> index 2c9869feba61..0708d0f0938b 100644
>>>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>>>> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct
>>>>> smu_context *smu)
>>>>>        uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
>>>>>            adev->gfx.config.max_sh_per_se * adev-
>>>>>> gfx.config.max_shader_engines;
>>>>> +    if (adev->in_s0ix)
>>>>> +        return 0;
>>>>> +
>>>>>        /* allow message will be sent after enable message on Vangogh*/
>>>>>        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
>>>>>                (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
>>>>
>>>
>>>
> 

Re: [PATCH v1 3/3] drm/amdgpu: only send the SMU RLC notification on S3

[Antheas Kapenekakis]

On Fri, 24 Oct 2025 at 18:52, Mario Limonciello
<mario.limonciello@amd.com> wrote:
>
>
>
> On 10/24/2025 11:45 AM, Antheas Kapenekakis wrote:
> > On Fri, 24 Oct 2025 at 18:24, Antheas Kapenekakis <lkml@antheas.dev> wrote:
> >>
> >> On Fri, 24 Oct 2025 at 18:20, Mario Limonciello
> >> <mario.limonciello@amd.com> wrote:
> >>>
> >>>
> >>>
> >>> On 10/24/2025 10:54 AM, Mario Limonciello wrote:
> >>>>
> >>>>
> >>>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> >>>>> From: Alex Deucher <alexander.deucher@amd.com>
> >>>>>
> >>>>> For S0ix, the RLC is not powered down. Rework the Van Gogh logic to
> >>>>> skip powering it down and skip part of post-init.
> >>>>>
> >>>>> Fixes: 8c4e9105b2a8 ("drm/amdgpu: optimize RLC powerdown notification
> >>>>> on Vangogh")
> >>>>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
> >>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >>>>> Tested-by: Antheas Kapenekakis <lkml@antheas.dev>
> >>>>> Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev>
> >>>>> ---
> >>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
> >>>>>    drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
> >>>>>    drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> >>>>>    3 files changed, 14 insertions(+), 3 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/
> >>>>> drm/amd/amdgpu/amdgpu_device.c
> >>>>> index 3d032c4e2dce..220b12d59795 100644
> >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>>>> @@ -5243,9 +5243,11 @@ int amdgpu_device_suspend(struct drm_device
> >>>>> *dev, bool notify_clients)
> >>>>>        if (amdgpu_sriov_vf(adev))
> >>>>>            amdgpu_virt_release_full_gpu(adev, false);
> >>>>> -    r = amdgpu_dpm_notify_rlc_state(adev, false);
> >>>>> -    if (r)
> >>>>> -        return r;
> >>>>> +    if (!adev->in_s0ix) {
> >>>>> +        r = amdgpu_dpm_notify_rlc_state(adev, false);
> >>>>> +        if (r)
> >>>>> +            return r;
> >>>>> +    }
> >>>>
> >>>> Just FYI this is going to clash with my unwind failed suspend series [1].
> >>>>
> >>>> This is fine, just whichever "lands" first the other will need to rework
> >>>> a little bit and I wanted to mention it.
> >>>>
> >>>> Link: https://lore.kernel.org/amd-gfx/20251023165243.317153-2-
> >>>> mario.limonciello@amd.com/ [1]
> >>>>
> >>>> This does have me wondering though why amdgpu_dpm_notify_rlc_state() is
> >>>> even in amdgpu_device_suspend()?  This is only used on Van Gogh.
> >>>> Should we be pushing this deeper into amdgpu_device_ip_suspend_phase2()?
> >>>>
> >>>> Or should we maybe overhaul this to move the RLC notification into
> >>>> a .set_mp1_state callback instead so it's more similar to all the other
> >>>> ASICs?
> >>>>
> >>>
> >>> My proposal as such is here:
> >>>
> >>> https://lore.kernel.org/amd-gfx/20251024161216.345691-1-mario.limonciello@amd.com/
> >>>
> >>> It would need some testing though to make sure it didn't break Steam
> >>> Deck or Steam Deck OLED.
> >>
> >> I will give it a quick go on my OLED.
> >
> > Horribly broken. Did not enter S3 and when waking up fan maxed out and
> > it bootlooped. Journalctl stops on suspend entry. It works on the Xbox
> > ally though
> >
> > My series works on both
>
> OK.
>
> Can you try Alex's idea instead?  Just comment out the RLC notification
> code in amdgpu_device_suspend().
>
> It's supposed to already be called in smu_disable_dpms() anyway.

Yes, removing those lines works.

> >
> >
> >>
> >>>>>        return 0;
> >>>>>    }
> >>>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/
> >>>>> drm/amd/pm/swsmu/amdgpu_smu.c
> >>>>> index fb8086859857..244b8c364d45 100644
> >>>>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>>>> @@ -2040,6 +2040,12 @@ static int smu_disable_dpms(struct smu_context
> >>>>> *smu)
> >>>>>            smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
> >>>>>            return 0;
> >>>>> +    /* vangogh s0ix */
> >>>>> +    if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
> >>>>> +         amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5,
> >>>>> 2)) &&
> >>>>> +        adev->in_s0ix)
> >>>>> +        return 0;
> >>>>> +
> >>>>
> >>>> How about for GPU reset, does PMFW handle this too?
> >>>>
> >>>>>        /*
> >>>>>         * For gpu reset, runpm and hibernation through BACO,
> >>>>>         * BACO feature has to be kept enabled.
> >>>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/
> >>>>> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >>>>> index 2c9869feba61..0708d0f0938b 100644
> >>>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >>>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> >>>>> @@ -2217,6 +2217,9 @@ static int vangogh_post_smu_init(struct
> >>>>> smu_context *smu)
> >>>>>        uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
> >>>>>            adev->gfx.config.max_sh_per_se * adev-
> >>>>>> gfx.config.max_shader_engines;
> >>>>> +    if (adev->in_s0ix)
> >>>>> +        return 0;
> >>>>> +
> >>>>>        /* allow message will be sent after enable message on Vangogh*/
> >>>>>        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
> >>>>>                (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> >>>>
> >>>
> >>>
> >
>
>

Re: [PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Mario Limonciello]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
> Therefore, kernel support for S0ix was previously absent. Introduce
> this support in three patches:
> 
> 1) Add Van Gogh to AMD PMC driver
> 2) Enable spurious_8042 quirk, as it is common in those generations
> 3) Adjust the Van Gogh init logic to avoid powering down the rlc
>     and tweak post init
> 

Just to be clear - there is no need for all 3 patches to go to one tree 
or another.  The PMC patches should go platform-x86 and the DRM patch 
should go through drm.

> This allows the Xbox Ally to properly enter and exit S0ix suspend.
> Perhaps it also allows the Steam Deck to use s2idle without crashing,
> note it is not currently possible [1].

FWIW I don't anticipate this series actually gets Steam deck into a 
hardware sleep state because you need firmware support as well.
But the drm patch will probably will help the hang that was observed 
which lead to the patch you've linked below.

> 
> Currently, around 1/10 times the SoC misses the PMC hint and does not
> enter S0ix, so perhaps 1 or 3 need tweaking further. It wakes up always,
> however.
> 
> @Alex: I tweaked the text on patch 3 a bit. You can resend it separately
> after the issue with 1/10 failures is fixed.
> 
> [1]: https://github.com/evlaV/linux-integration/commit/5ab73e9069017aa1b5351f91513ba540ce5905fb
> 
> Alex Deucher (1):
>    drm/amdgpu: only send the SMU RLC notification on S3
> 
> Antheas Kapenekakis (2):
>    platform/x86/amd/pmc: Add support for Van Gogh SoC
>    platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally
> 
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>   drivers/platform/x86/amd/pmc/pmc-quirks.c        | 8 ++++++++
>   drivers/platform/x86/amd/pmc/pmc.c               | 3 +++
>   drivers/platform/x86/amd/pmc/pmc.h               | 1 +
>   6 files changed, 26 insertions(+), 3 deletions(-)
> 
> 
> base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5

Re: [PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Antheas Kapenekakis]

On Fri, 24 Oct 2025 at 17:32, Mario Limonciello
<mario.limonciello@amd.com> wrote:
>
>
>
> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> > The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
> > Therefore, kernel support for S0ix was previously absent. Introduce
> > this support in three patches:
> >
> > 1) Add Van Gogh to AMD PMC driver
> > 2) Enable spurious_8042 quirk, as it is common in those generations
> > 3) Adjust the Van Gogh init logic to avoid powering down the rlc
> >     and tweak post init
> >
>
> Just to be clear - there is no need for all 3 patches to go to one tree
> or another.  The PMC patches should go platform-x86 and the DRM patch
> should go through drm.

Perhaps someone wants to test out all three. I will resend only the
first two next time.

> > This allows the Xbox Ally to properly enter and exit S0ix suspend.
> > Perhaps it also allows the Steam Deck to use s2idle without crashing,
> > note it is not currently possible [1].
>
> FWIW I don't anticipate this series actually gets Steam deck into a
> hardware sleep state because you need firmware support as well.
> But the drm patch will probably will help the hang that was observed
> which lead to the patch you've linked below.

That's what I think too

Antheas

> >
> > Currently, around 1/10 times the SoC misses the PMC hint and does not
> > enter S0ix, so perhaps 1 or 3 need tweaking further. It wakes up always,
> > however.
> >
> > @Alex: I tweaked the text on patch 3 a bit. You can resend it separately
> > after the issue with 1/10 failures is fixed.
> >
> > [1]: https://github.com/evlaV/linux-integration/commit/5ab73e9069017aa1b5351f91513ba540ce5905fb
> >
> > Alex Deucher (1):
> >    drm/amdgpu: only send the SMU RLC notification on S3
> >
> > Antheas Kapenekakis (2):
> >    platform/x86/amd/pmc: Add support for Van Gogh SoC
> >    platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally
> >
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
> >   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> >   drivers/platform/x86/amd/pmc/pmc-quirks.c        | 8 ++++++++
> >   drivers/platform/x86/amd/pmc/pmc.c               | 3 +++
> >   drivers/platform/x86/amd/pmc/pmc.h               | 1 +
> >   6 files changed, 26 insertions(+), 3 deletions(-)
> >
> >
> > base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5
>
>

Re: [PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Mario Limonciello]

On 10/24/2025 10:38 AM, Antheas Kapenekakis wrote:
> On Fri, 24 Oct 2025 at 17:32, Mario Limonciello
> <mario.limonciello@amd.com> wrote:
>>
>>
>>
>> On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
>>> The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
>>> Therefore, kernel support for S0ix was previously absent. Introduce
>>> this support in three patches:
>>>
>>> 1) Add Van Gogh to AMD PMC driver
>>> 2) Enable spurious_8042 quirk, as it is common in those generations
>>> 3) Adjust the Van Gogh init logic to avoid powering down the rlc
>>>      and tweak post init
>>>
>>
>> Just to be clear - there is no need for all 3 patches to go to one tree
>> or another.  The PMC patches should go platform-x86 and the DRM patch
>> should go through drm.
> 
> Perhaps someone wants to test out all three. I will resend only the
> first two next time.

It's fine to send them all together.  To your point it does make it a 
easier to `b4 shazam` the whole series and test it.

If the series needs to spin again and you want to keep them together 
just mention it in the cover letter that they don't need to be merged 
through the same tree.

> 
>>> This allows the Xbox Ally to properly enter and exit S0ix suspend.
>>> Perhaps it also allows the Steam Deck to use s2idle without crashing,
>>> note it is not currently possible [1].
>>
>> FWIW I don't anticipate this series actually gets Steam deck into a
>> hardware sleep state because you need firmware support as well.
>> But the drm patch will probably will help the hang that was observed
>> which lead to the patch you've linked below.
> 
> That's what I think too
> 
> Antheas
> 
>>>
>>> Currently, around 1/10 times the SoC misses the PMC hint and does not
>>> enter S0ix, so perhaps 1 or 3 need tweaking further. It wakes up always,
>>> however.
>>>
>>> @Alex: I tweaked the text on patch 3 a bit. You can resend it separately
>>> after the issue with 1/10 failures is fixed.
>>>
>>> [1]: https://github.com/evlaV/linux-integration/commit/5ab73e9069017aa1b5351f91513ba540ce5905fb
>>>
>>> Alex Deucher (1):
>>>     drm/amdgpu: only send the SMU RLC notification on S3
>>>
>>> Antheas Kapenekakis (2):
>>>     platform/x86/amd/pmc: Add support for Van Gogh SoC
>>>     platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally
>>>
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>>>    drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>>>    drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>>>    drivers/platform/x86/amd/pmc/pmc-quirks.c        | 8 ++++++++
>>>    drivers/platform/x86/amd/pmc/pmc.c               | 3 +++
>>>    drivers/platform/x86/amd/pmc/pmc.h               | 1 +
>>>    6 files changed, 26 insertions(+), 3 deletions(-)
>>>
>>>
>>> base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5
>>
>>
> 

Re: [PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Mario Limonciello (AMD) (kernel.org)]

On 10/24/2025 10:21 AM, Antheas Kapenekakis wrote:
> The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
> Therefore, kernel support for S0ix was previously absent. Introduce
> this support in three patches:
> 
> 1) Add Van Gogh to AMD PMC driver
> 2) Enable spurious_8042 quirk, as it is common in those generations
> 3) Adjust the Van Gogh init logic to avoid powering down the rlc
>     and tweak post init
> 
> This allows the Xbox Ally to properly enter and exit S0ix suspend.
> Perhaps it also allows the Steam Deck to use s2idle without crashing,
> note it is not currently possible [1].
> 
> Currently, around 1/10 times the SoC misses the PMC hint and does not
> enter S0ix, so perhaps 1 or 3 need tweaking further. It wakes up always,
> however.
> 
> @Alex: I tweaked the text on patch 3 a bit. You can resend it separately
> after the issue with 1/10 failures is fixed.
> 
> [1]: https://github.com/evlaV/linux-integration/commit/5ab73e9069017aa1b5351f91513ba540ce5905fb
> 
> Alex Deucher (1):
>    drm/amdgpu: only send the SMU RLC notification on S3
> 
> Antheas Kapenekakis (2):
>    platform/x86/amd/pmc: Add support for Van Gogh SoC
>    platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally
> 
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c       | 8 +++++---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c        | 6 ++++++
>   drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
>   drivers/platform/x86/amd/pmc/pmc-quirks.c        | 8 ++++++++
>   drivers/platform/x86/amd/pmc/pmc.c               | 3 +++
>   drivers/platform/x86/amd/pmc/pmc.h               | 1 +
>   6 files changed, 26 insertions(+), 3 deletions(-)
> 
> 
> base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5

Ilpo,

Patches 1 and 2 are good for platform-x86.  Since this fixes the 
platform-x86 side of a hang at suspend I think these should go 6.18-rc 
if you're open to it.

We're doing something different with the other patches in 
amd-staging-drm-next.  You can ignore the ones in this series.

Re: [PATCH v1 0/3] platform/x86/amd: Add S0ix support to the Xbox Ally

[Ilpo Järvinen]

On Fri, 24 Oct 2025 17:21:49 +0200, Antheas Kapenekakis wrote:

> The Xbox Ally features a Van Gogh SoC that on the Steam Deck uses S3.
> Therefore, kernel support for S0ix was previously absent. Introduce
> this support in three patches:
> 
> 1) Add Van Gogh to AMD PMC driver
> 2) Enable spurious_8042 quirk, as it is common in those generations
> 3) Adjust the Van Gogh init logic to avoid powering down the rlc
>    and tweak post init
> 
> [...]


Thank you for your contribution, it has been applied to my local
review-ilpo-fixes branch. Note it will show up in the public
platform-drivers-x86/review-ilpo-fixes branch only once I've pushed my
local branch there, which might take a while.

The list of commits applied:
[1/3] platform/x86/amd/pmc: Add support for Van Gogh SoC
      commit: a400f448c1ad5e22e7ec1700e911f8f9c6a85475
[2/3] platform/x86/amd/pmc: Add spurious_8042 to Xbox Ally
      commit: 50cb52ee1dd60247746a984392632ec4237df127
[3/3] drm/amdgpu: only send the SMU RLC notification on S3
      (no commit info)

--
 i.