[PATCH 00/14] drm/amd: Delete defunct DAL power level code

[PATCH 00/14] drm/amd: Delete defunct DAL power level code

[Timur Kristóf]

Delete unused code related to DAL power levels.
It seems that the DAL power level concept has been
never fully implemented and was thus non-functional
in amdgpu.

DCE 11.0 and 11.2 never actually relied on the
power level because they calculate all necessary
power requirements in dce_calcs and communicate
that using dm_pp_apply_display_requirements() to
the power management code.

DCE 6, 8 and 10 also didn't rely on power levels
because they always just set the maximum possible
display clock and the power management code
already takes that into account when setting the
power state. This was somewhat improved recently
by also using dm_pp_apply_display_requirements()
on these DCE versions.

The code base for newer GPUs doesn't use the
concept of power levels anymore either, so
this change reduces the maintenance burden
of the old DCE code.

On the DC side:

dm_pp_apply_power_level_change_request() was never
implemented in amdgpu_dm, and DC has been working
fine for years without it. Let's delete the dummy
function and the code that calls it.

With that, we can also delete the power levels
and the static arrays containing hardcoded power
level values. These were never used for anything,
only for finding the maximum supported display clock.

On the AMDGPU PM side:

The get_dal_power_level() implementations were
dummy on SMU10, Vega10, Vega12 and Vega20 meaning
that they didn't return an actual DAL power level,
and were non-functional on SMU8 which always
returned the highest possible power level.
Nothing actually relied on the power level
returned by these functions. Let's delete them.

What's next:

After this code cleanup lands, I have plans to
further improve display power management on old DCE.

Timur Kristóf (14):
  drm/amd/display: Delete unimplemented
    dm_pp_apply_power_level_change_request()
  drm/amd/display: Delete dce_get_required_clocks_state()
  drm/amd/display: Remove min/max clock levels from clk_mgr
  drm/amd/display: Delete max_clocks_state from dm_pp_static_clock_info
  drm/amd/display: Set max supported display clock without
    max_clks_by_state
  drm/amd/display: Delete max_clks_by_state from DCE clock manager
  drm/amd/display: Delete disp_clk_voltage from integrated info
  drm/amd/display: Delete dm_pp_clocks_state
  drm/amd/pm: Delete unused get_display_power_level() function
  drm/amd/pm: Delete dummy get_dal_power_level implementations
  drm/amd/pm: Delete non-functional SMU8 get_dal_power_level
    implementation
  drm/amd/pm: Delete vddc_dep_on_dal_pwrl
  drm/amd/pm: Delete get_dal_power_level
  drm/amd/pm: Delete PP_DAL_POWERLEVEL

 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  39 -----
 .../gpu/drm/amd/display/dc/bios/bios_parser.c |  36 -----
 .../drm/amd/display/dc/bios/bios_parser2.c    |   9 --
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 144 ++----------------
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.h   |   3 -
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c        |  25 ---
 .../dc/clk_mgr/dce112/dce112_clk_mgr.c        |  41 -----
 .../dc/clk_mgr/dce120/dce120_clk_mgr.c        |  16 --
 drivers/gpu/drm/amd/display/dc/dm_services.h  |   4 -
 .../drm/amd/display/dc/dm_services_types.h    |  30 ----
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |   4 -
 .../display/include/grph_object_ctrl_defs.h   |   9 --
 drivers/gpu/drm/amd/include/dm_pp_interface.h |  19 ---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 -
 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |  22 ---
 .../amd/pm/powerplay/hwmgr/hardwaremanager.c  |  10 --
 .../amd/pm/powerplay/hwmgr/processpptables.c  |   1 -
 .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  |  48 ------
 .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   |  64 --------
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c |  18 ---
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c |  16 --
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c |  17 ---
 .../amd/pm/powerplay/inc/hardwaremanager.h    |   3 -
 drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h  |   4 -
 24 files changed, 11 insertions(+), 573 deletions(-)

-- 
2.53.0

[PATCH 00/14] drm/amd: Delete defunct DAL power level code

[Timur Kristóf]

Delete unused code related to DAL power levels.
It seems that the DAL power level concept has been
never fully implemented and was thus non-functional
in amdgpu.

DCE 11.0 and 11.2 never actually relied on the
power level because they calculate all necessary
power requirements in dce_calcs and communicate
that using dm_pp_apply_display_requirements() to
the power management code.

DCE 6, 8 and 10 also didn't rely on power levels
because they always just set the maximum possible
display clock and the power management code
already takes that into account when setting the
power state. This was somewhat improved recently
by also using dm_pp_apply_display_requirements()
on these DCE versions.

The code base for newer GPUs doesn't use the
concept of power levels anymore either, so
this change reduces the maintenance burden
of the old DCE code.

On the DC side:

dm_pp_apply_power_level_change_request() was never
implemented in amdgpu_dm, and DC has been working
fine for years without it. Let's delete the dummy
function and the code that calls it.

With that, we can also delete the power levels
and the static arrays containing hardcoded power
level values. These were never used for anything,
only for finding the maximum supported display clock.

On the AMDGPU PM side:

The get_dal_power_level() implementations were
dummy on SMU10, Vega10, Vega12 and Vega20 meaning
that they didn't return an actual DAL power level,
and were non-functional on SMU8 which always
returned the highest possible power level.
Nothing actually relied on the power level
returned by these functions. Let's delete them.

What's next:

After this code cleanup lands, I have plans to
further improve display power management on old DCE.

Changes in v2:

Applied review suggestions.

Timur Kristóf (14):
  drm/amd/display: Delete unimplemented
    dm_pp_apply_power_level_change_request() (v2)
  drm/amd/display: Delete dce_get_required_clocks_state()
  drm/amd/display: Remove min/max clock levels from clk_mgr (v2)
  drm/amd/display: Delete max_clocks_state
  drm/amd/display: Set max supported display clock without
    max_clks_by_state (v2)
  drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2)
  drm/amd/display: Delete disp_clk_voltage from integrated info (v2)
  drm/amd/display: Delete dm_pp_clocks_state
  drm/amd/pm: Delete unused get_display_power_level() function
  drm/amd/pm: Delete dummy get_dal_power_level implementations
  drm/amd/pm: Delete non-functional SMU8 get_dal_power_level
    implementation
  drm/amd/pm: Delete vddc_dep_on_dal_pwrl
  drm/amd/pm: Delete get_dal_power_level
  drm/amd/pm: Delete PP_DAL_POWERLEVEL

 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  55 -------
 .../gpu/drm/amd/display/dc/bios/bios_parser.c |  36 -----
 .../drm/amd/display/dc/bios/bios_parser2.c    |  18 ---
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 144 ++----------------
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.h   |   3 -
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c        |  25 ---
 .../dc/clk_mgr/dce112/dce112_clk_mgr.c        |  41 -----
 .../dc/clk_mgr/dce120/dce120_clk_mgr.c        |  16 --
 drivers/gpu/drm/amd/display/dc/dm_services.h  |   8 -
 .../drm/amd/display/dc/dm_services_types.h    |  30 ----
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 --
 .../display/include/grph_object_ctrl_defs.h   |   9 --
 drivers/gpu/drm/amd/include/dm_pp_interface.h |  19 ---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 -
 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |  22 ---
 .../amd/pm/powerplay/hwmgr/hardwaremanager.c  |  10 --
 .../amd/pm/powerplay/hwmgr/processpptables.c  |   1 -
 .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  |  48 ------
 .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   |  64 --------
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c |  18 ---
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c |  16 --
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c |  17 ---
 .../amd/pm/powerplay/inc/hardwaremanager.h    |   3 -
 drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h  |   4 -
 24 files changed, 11 insertions(+), 608 deletions(-)

-- 
2.54.0

[PATCH 01/14] drm/amd/display: Delete unimplemented dm_pp_apply_power_level_change_request() (v2)

[Timur Kristóf]

dm_pp_apply_power_level_change_request() was called from old
DCE clock manager implementations on DCE6, 8, 10, 11.2
but has not been implemented ever since the beginning of DC.

Affected GPUs have been working fine without that implementation
for many years. Let's delete it now.

v2:
- Delete dm_pp_apply_power_level_change_request too

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 8 --------
 .../gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 9 ---------
 .../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c   | 9 ---------
 .../drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c   | 9 ---------
 drivers/gpu/drm/amd/display/dc/dm_services.h             | 4 ----
 drivers/gpu/drm/amd/display/dc/dm_services_types.h       | 4 ----
 6 files changed, 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 11b2ea6edf95..17f42201ab86 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -417,14 +417,6 @@ bool dm_pp_notify_wm_clock_changes(
 	return false;
 }
 
-bool dm_pp_apply_power_level_change_request(
-	const struct dc_context *ctx,
-	struct dm_pp_power_level_change_request *level_change_req)
-{
-	/* TODO: to be implemented */
-	return false;
-}
-
 bool dm_pp_apply_clock_for_voltage_request(
 	const struct dc_context *ctx,
 	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 808e24f0e88f..4ccc6c742d00 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -431,19 +431,10 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
 			bool safe_to_lower)
 {
 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	struct dm_pp_power_level_change_request level_change_req;
 	const int max_disp_clk =
 		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
 	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
 
-	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-	/* get max clock state from PPLIB */
-	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-	}
-
 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
 		patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index b35a44976477..d3cd542063db 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -257,21 +257,12 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,
 			bool safe_to_lower)
 {
 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	struct dm_pp_power_level_change_request level_change_req;
 	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
 
 	/*TODO: W/A for dal3 linux, investigate why this works */
 	if (!clk_mgr_dce->dfs_bypass_active)
 		patched_disp_clk = patched_disp_clk * 115 / 100;
 
-	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-	/* get max clock state from PPLIB */
-	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-	}
-
 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
 		context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 1f36ad8a7de4..48393c69735b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -193,21 +193,12 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
 			bool safe_to_lower)
 {
 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	struct dm_pp_power_level_change_request level_change_req;
 	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
 
 	/*TODO: W/A for dal3 linux, investigate why this works */
 	if (!clk_mgr_dce->dfs_bypass_active)
 		patched_disp_clk = patched_disp_clk * 115 / 100;
 
-	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-	/* get max clock state from PPLIB */
-	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-	}
-
 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
 		patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index fbbf9c757b3c..1395d36bfabe 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -224,10 +224,6 @@ bool dm_pp_apply_display_requirements(
 	const struct dc_context *ctx,
 	const struct dm_pp_display_configuration *pp_display_cfg);
 
-bool dm_pp_apply_power_level_change_request(
-	const struct dc_context *ctx,
-	struct dm_pp_power_level_change_request *level_change_req);
-
 bool dm_pp_apply_clock_for_voltage_request(
 	const struct dc_context *ctx,
 	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 3b093b8699ab..cae3ed6056d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -246,10 +246,6 @@ enum dm_acpi_display_type {
 	AcpiDisplayType_DFP6 = 12
 };
 
-struct dm_pp_power_level_change_request {
-	enum dm_pp_clocks_state power_level;
-};
-
 struct dm_pp_clock_for_voltage_req {
 	enum dm_pp_clock_type clk_type;
 	uint32_t clocks_in_khz;
-- 
2.54.0

[PATCH 02/14] drm/amd/display: Delete dce_get_required_clocks_state()

[Timur Kristóf]

It is not called from anywhere anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 34 -------------------
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.h   |  3 --
 2 files changed, 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 4ccc6c742d00..e8daee975b79 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -220,40 +220,6 @@ uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
 	return max_pix_clk;
 }
 
-enum dm_pp_clocks_state dce_get_required_clocks_state(
-	struct clk_mgr *clk_mgr_base,
-	struct dc_state *context)
-{
-	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	int i;
-	enum dm_pp_clocks_state low_req_clk;
-	int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
-
-	/* Iterate from highest supported to lowest valid state, and update
-	 * lowest RequiredState with the lowest state that satisfies
-	 * all required clocks
-	 */
-	for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
-		if (context->bw_ctx.bw.dce.dispclk_khz >
-				clk_mgr_dce->max_clks_by_state[i].display_clk_khz
-			|| max_pix_clk >
-				clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
-			break;
-
-	low_req_clk = i + 1;
-	if (low_req_clk > clk_mgr_dce->max_clks_state) {
-		/* set max clock state for high phyclock, invalid on exceeding display clock */
-		if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
-				< context->bw_ctx.bw.dce.dispclk_khz)
-			low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
-		else
-			low_req_clk = clk_mgr_dce->max_clks_state;
-	}
-
-	return low_req_clk;
-}
-
-
 /* TODO: remove use the two broken down functions */
 int dce_set_clock(
 	struct clk_mgr *clk_mgr_base,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
index 9ea1b0a9923d..e1c6a92d7957 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
@@ -32,9 +32,6 @@
 /* functions shared by other dce clk mgrs */
 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);
 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
-enum dm_pp_clocks_state dce_get_required_clocks_state(
-	struct clk_mgr *clk_mgr_base,
-	struct dc_state *context);
 
 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);
 
-- 
2.54.0

[PATCH 03/14] drm/amd/display: Remove min/max clock levels from clk_mgr (v2)

[Timur Kristóf]

These fields are not used by anything anymore.

v2:
- Delete dm_pp_get_static_clocks()
- Delete pp_to_dc_powerlevel_state()

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 44 -------------------
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 ------
 .../dc/clk_mgr/dce112/dce112_clk_mgr.c        | 15 -------
 drivers/gpu/drm/amd/display/dc/dm_services.h  |  4 --
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  2 -
 5 files changed, 79 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 17f42201ab86..a3ee580d8dd1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -183,33 +183,6 @@ static enum amd_pp_clock_type dc_to_pp_clock_type(
 	return amd_pp_clk_type;
 }
 
-static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
-			enum PP_DAL_POWERLEVEL max_clocks_state)
-{
-	switch (max_clocks_state) {
-	case PP_DAL_POWERLEVEL_0:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
-	case PP_DAL_POWERLEVEL_1:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
-	case PP_DAL_POWERLEVEL_2:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
-	case PP_DAL_POWERLEVEL_3:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
-	case PP_DAL_POWERLEVEL_4:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
-	case PP_DAL_POWERLEVEL_5:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
-	case PP_DAL_POWERLEVEL_6:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
-	case PP_DAL_POWERLEVEL_7:
-		return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
-	default:
-		DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
-				max_clocks_state);
-		return DM_PP_CLOCKS_STATE_INVALID;
-	}
-}
-
 static void pp_to_dc_clock_levels(
 		const struct amd_pp_clocks *pp_clks,
 		struct dm_pp_clock_levels *dc_clks,
@@ -438,23 +411,6 @@ bool dm_pp_apply_clock_for_voltage_request(
 	return true;
 }
 
-bool dm_pp_get_static_clocks(
-	const struct dc_context *ctx,
-	struct dm_pp_static_clock_info *static_clk_info)
-{
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct amd_pp_clock_info pp_clk_info = {0};
-
-	if (amdgpu_dpm_get_current_clocks(adev, &pp_clk_info))
-		return false;
-
-	static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
-	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
-	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
-
-	return true;
-}
-
 static void pp_rv_set_wm_ranges(struct pp_smu *pp,
 		struct pp_smu_wm_range_sets *ranges)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index e8daee975b79..b7b72af9570a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -257,11 +257,6 @@ int dce_set_clock(
 		actual_clock = pxl_clk_params.dfs_bypass_display_clock;
 	}
 
-	/* from power down, we need mark the clock state as ClocksStateNominal
-	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-	if (requested_clk_khz == 0)
-		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
 	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 		dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
 
@@ -425,7 +420,6 @@ void dce_clk_mgr_construct(
 		struct clk_mgr_internal *clk_mgr)
 {
 	struct clk_mgr *base = &clk_mgr->base;
-	struct dm_pp_static_clock_info static_clk_info = {0};
 
 	if (ctx->dce_version <= DCE_VERSION_6_4)
 		memcpy(clk_mgr->max_clks_by_state,
@@ -451,14 +445,6 @@ void dce_clk_mgr_construct(
 	clk_mgr->dprefclk_ss_divider = 1000;
 	clk_mgr->ss_on_dprefclk = false;
 
-	if (ctx->dce_version >= DCE_VERSION_8_0) {
-		if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-			clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
-		else
-			clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-	}
-
 	base->clks.max_supported_dispclk_khz =
 		clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 48393c69735b..0f3f8df4df96 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -89,13 +89,6 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
 	actual_clock = dce_clk_params.target_clock_frequency;
 
-	/*
-	 * from power down, we need mark the clock state as ClocksStateNominal
-	 * from HWReset, so when resume we will call pplib voltage regulator.
-	 */
-	if (requested_clk_khz == 0)
-		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
 	/*Program DP ref Clock*/
 	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
 	dce_clk_params.target_clock_frequency = 0;
@@ -143,14 +136,6 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
 	actual_clock = dce_clk_params.target_clock_frequency;
 
-	/*
-	 * from power down, we need mark the clock state as ClocksStateNominal
-	 * from HWReset, so when resume we will call pplib voltage regulator.
-	 */
-	if (requested_clk_khz == 0)
-		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
-
 	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 		if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
 			dmcu->funcs->set_psr_wait_loop(dmcu,
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 1395d36bfabe..8b062b011fc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -228,10 +228,6 @@ bool dm_pp_apply_clock_for_voltage_request(
 	const struct dc_context *ctx,
 	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
 
-bool dm_pp_get_static_clocks(
-	const struct dc_context *ctx,
-	struct dm_pp_static_clock_info *static_clk_info);
-
 /****** end of PP interfaces ******/
 
 struct persistent_data_flag {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index c69ccfcebeb5..e01bf6bd7f3f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -477,8 +477,6 @@ struct clk_mgr_internal {
 	 */
 	int dprefclk_ss_divider;
 
-	enum dm_pp_clocks_state max_clks_state;
-	enum dm_pp_clocks_state cur_min_clks_state;
 	bool periodic_retraining_disabled;
 
 	unsigned int cur_phyclk_req_table[MAX_LINKS];
-- 
2.54.0

[PATCH 04/14] drm/amd/display: Delete max_clocks_state

[Timur Kristóf]

It's not used by anything anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index cae3ed6056d6..f114ab819afd 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -254,9 +254,6 @@ struct dm_pp_clock_for_voltage_req {
 struct dm_pp_static_clock_info {
 	uint32_t max_sclk_khz;
 	uint32_t max_mclk_khz;
-
-	/* max possible display block clocks state */
-	enum dm_pp_clocks_state max_clocks_state;
 };
 
 struct dtn_min_clk_info {
-- 
2.54.0

[PATCH 05/14] drm/amd/display: Set max supported display clock without max_clks_by_state (v2)

[Timur Kristóf]

The max_clks_by_state was based on hardcoded values, which are
not really used anywhere, only to know the maximum clock.
Just hardcode the same maximum clock for each DCE version.

v2:
- Use previous max display clock for DCE 11.2

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index b7b72af9570a..978bbc307991 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -391,9 +391,7 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
 			bool safe_to_lower)
 {
-	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	const int max_disp_clk =
-		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+	const int max_disp_clk = clk_mgr_base->clks.max_supported_dispclk_khz;
 	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
 
 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
@@ -445,8 +443,16 @@ void dce_clk_mgr_construct(
 	clk_mgr->dprefclk_ss_divider = 1000;
 	clk_mgr->ss_on_dprefclk = false;
 
-	base->clks.max_supported_dispclk_khz =
-		clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+	if (ctx->dce_version >= DCE_VERSION_12_0)
+		base->clks.max_supported_dispclk_khz = 1133000;
+	else if (ctx->dce_version >= DCE_VERSION_11_2)
+		base->clks.max_supported_dispclk_khz = 1132000;
+	else if (ctx->dce_version >= DCE_VERSION_11_0)
+		base->clks.max_supported_dispclk_khz = 643000;
+	else if (ctx->dce_version >= DCE_VERSION_8_0)
+		base->clks.max_supported_dispclk_khz = 625000;
+	else
+		base->clks.max_supported_dispclk_khz = 600000;
 
 	dce_clock_read_integrated_info(clk_mgr);
 	dce_clock_read_ss_info(clk_mgr);
-- 
2.54.0

[PATCH 06/14] drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2)

[Timur Kristóf]

It was not used by anything anymore.

Note that the parts of DC that need this information actually
already query it from the pplib and don't use the hardcoded
information from max_clks_by_state.

v2:
- Also delete state_dependent_clocks

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 71 -------------------
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 16 -----
 .../dc/clk_mgr/dce112/dce112_clk_mgr.c        | 17 -----
 .../dc/clk_mgr/dce120/dce120_clk_mgr.c        | 16 -----
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  8 ---
 5 files changed, 128 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 978bbc307991..d891b3bfe2a1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -62,32 +62,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
 		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
-
 unsigned int dentist_get_divider_from_did(unsigned int did)
 {
 	if (did < DENTIST_BASE_DID_1)
@@ -268,7 +242,6 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
 {
 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
-	int i;
 
 	if (bp->integrated_info)
 		clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
@@ -278,40 +251,6 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
 			clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
 	}
 
-	/*update the maximum display clock for each power state*/
-	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-
-		switch (i) {
-		case 0:
-			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
-			break;
-
-		case 1:
-			clk_state = DM_PP_CLOCKS_STATE_LOW;
-			break;
-
-		case 2:
-			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
-			break;
-
-		case 3:
-			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
-			break;
-
-		default:
-			clk_state = DM_PP_CLOCKS_STATE_INVALID;
-			break;
-		}
-
-		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
-		 * check for > 100MHz*/
-		if (bp->integrated_info)
-			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
-				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
-					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
-	}
-
 	if (!debug->disable_dfs_bypass && bp->integrated_info)
 		if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
 			clk_mgr_dce->dfs_bypass_enabled = true;
@@ -419,16 +358,6 @@ void dce_clk_mgr_construct(
 {
 	struct clk_mgr *base = &clk_mgr->base;
 
-	if (ctx->dce_version <= DCE_VERSION_6_4)
-		memcpy(clk_mgr->max_clks_by_state,
-			dce60_max_clks_by_state,
-			sizeof(dce60_max_clks_by_state));
-	else
-		memcpy(clk_mgr->max_clks_by_state,
-			dce80_max_clks_by_state,
-			sizeof(dce80_max_clks_by_state));
-
-
 	base->ctx = ctx;
 	base->funcs = &dce_funcs;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index d3cd542063db..d52789ba2613 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -51,18 +51,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
 		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
-
 static uint32_t determine_sclk_from_bounding_box(
 		const struct dc *dc,
 		uint32_t required_sclk)
@@ -281,10 +269,6 @@ void dce110_clk_mgr_construct(
 {
 	dce_clk_mgr_construct(ctx, clk_mgr);
 
-	memcpy(clk_mgr->max_clks_by_state,
-		dce110_max_clks_by_state,
-		sizeof(dce110_max_clks_by_state));
-
 	clk_mgr->regs = &disp_clk_regs;
 	clk_mgr->clk_mgr_shift = &disp_clk_shift;
 	clk_mgr->clk_mgr_mask = &disp_clk_mask;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 0f3f8df4df96..08ed6f88025f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -53,19 +53,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
 		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
-
-
 //TODO: remove use the two broken down functions
 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
 {
@@ -202,10 +189,6 @@ void dce112_clk_mgr_construct(
 {
 	dce_clk_mgr_construct(ctx, clk_mgr);
 
-	memcpy(clk_mgr->max_clks_by_state,
-		dce112_max_clks_by_state,
-		sizeof(dce112_max_clks_by_state));
-
 	clk_mgr->regs = &disp_clk_regs;
 	clk_mgr->clk_mgr_shift = &disp_clk_shift;
 	clk_mgr->clk_mgr_mask = &disp_clk_mask;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
index c9ba7b3fd2c3..f8ef3a4710fc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
@@ -32,18 +32,6 @@
 #include "dce100/dce_clk_mgr.h"
 #include "dce120/dce120_hwseq.h"
 
-static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-
 /**
  * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
  * @clk_mgr_dce: clock manager internal structure
@@ -129,10 +117,6 @@ void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *c
 {
 	dce_clk_mgr_construct(ctx, clk_mgr);
 
-	memcpy(clk_mgr->max_clks_by_state,
-		dce120_max_clks_by_state,
-		sizeof(dce120_max_clks_by_state));
-
 	clk_mgr->base.dprefclk_khz = 600000;
 	clk_mgr->base.funcs = &dce120_funcs;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index e01bf6bd7f3f..450bce3d8e02 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -405,12 +405,6 @@ enum clock_type {
 	clock_type_dtbclk,
 };
 
-
-struct state_dependent_clocks {
-	int display_clk_khz;
-	int pixel_clk_khz;
-};
-
 struct clk_mgr_internal {
 	struct clk_mgr base;
 	int smu_ver;
@@ -429,8 +423,6 @@ struct clk_mgr_internal {
 	const struct clk_mgr_shift *clk_mgr_shift;
 	const struct clk_mgr_mask *clk_mgr_mask;
 
-	struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
-
 	/*TODO: figure out which of the below fields should be here vs in asic specific portion */
 	/* Cache the status of DFS-bypass feature*/
 	bool dfs_bypass_enabled;
-- 
2.54.0

[PATCH 07/14] drm/amd/display: Delete disp_clk_voltage from integrated info (v2)

[Timur Kristóf]

Only DCE 11.0 relies on this information and even that
didn't use this field, because it queries the information
from the pplib. It also filled the field incorrectly on
that version.

On newer GPUs, the VIOS integrated info no longer contains
display clock voltage dependencies, so we don't need it.

v2:
- Also delete some code wrapped in #if 0

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../gpu/drm/amd/display/dc/bios/bios_parser.c | 36 -------------------
 .../drm/amd/display/dc/bios/bios_parser2.c    | 18 ----------
 .../display/include/grph_object_ctrl_defs.h   |  9 -----
 3 files changed, 63 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 05f299ec5463..2c7cca697f5f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -2419,15 +2419,6 @@ static enum bp_result get_integrated_info_v8(
 	info->dentist_vco_freq = le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
 	info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
 
-	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		/* Convert [10KHz] into [KHz] */
-		info->disp_clk_voltage[i].max_supported_clk =
-			le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
-				    ulMaximumSupportedCLK) * 10;
-		info->disp_clk_voltage[i].voltage_index =
-			le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
-	}
-
 	info->boot_up_req_display_vector =
 		le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
 	info->gpu_cap_info =
@@ -2570,14 +2561,6 @@ static enum bp_result get_integrated_info_v9(
 	info->dentist_vco_freq = le32_to_cpu(info_v9->ulDentistVCOFreq) * 10;
 	info->boot_up_uma_clock = le32_to_cpu(info_v9->ulBootUpUMAClock) * 10;
 
-	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		/* Convert [10KHz] into [KHz] */
-		info->disp_clk_voltage[i].max_supported_clk =
-			le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
-		info->disp_clk_voltage[i].voltage_index =
-			le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
-	}
-
 	info->boot_up_req_display_vector =
 		le32_to_cpu(info_v9->ulBootUpReqDisplayVector);
 	info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo);
@@ -2719,25 +2702,6 @@ static enum bp_result construct_integrated_info(
 		}
 	}
 
-	/* Sort voltage table from low to high*/
-	if (result == BP_RESULT_OK) {
-		int32_t i;
-		int32_t j;
-
-		for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-			for (j = i; j > 0; --j) {
-				if (
-						info->disp_clk_voltage[j].max_supported_clk <
-						info->disp_clk_voltage[j-1].max_supported_clk) {
-					/* swap j and j - 1*/
-					swap(info->disp_clk_voltage[j - 1],
-					     info->disp_clk_voltage[j]);
-				}
-			}
-		}
-
-	}
-
 	return result;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 39668db6d472..d19ae67ebfac 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -2671,15 +2671,6 @@ static enum bp_result get_integrated_info_v11(
 	info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
 	info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
 
-	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		/* Convert [10KHz] into [KHz] */
-		info->disp_clk_voltage[i].max_supported_clk =
-		le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
-			ulMaximumSupportedCLK) * 10;
-		info->disp_clk_voltage[i].voltage_index =
-		le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
-	}
-
 	info->boot_up_req_display_vector =
 			le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
 	info->boot_up_nb_voltage =
@@ -3032,7 +3023,6 @@ static enum bp_result construct_integrated_info(
 	struct atom_data_revision revision;
 
 	int32_t i;
-	int32_t j;
 
 	if (!info)
 		return result;
@@ -3134,14 +3124,6 @@ static enum bp_result construct_integrated_info(
 			DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
 		}
 	}
-	/* Sort voltage table from low to high*/
-	for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		for (j = i; j > 0; --j) {
-			if (info->disp_clk_voltage[j].max_supported_clk <
-			    info->disp_clk_voltage[j-1].max_supported_clk)
-				swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
-		}
-	}
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index a0f03fb67605..3e4e8d55dd0f 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -273,7 +273,6 @@ struct transmitter_configuration {
 #define NUMBER_OF_UCHAR_FOR_GUID 16
 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
 #define NUMBER_OF_CSR_M3_ARB 10
-#define NUMBER_OF_DISP_CLK_VOLTAGE 4
 #define NUMBER_OF_AVAILABLE_SCLK 5
 
 struct i2c_reg_info {
@@ -302,14 +301,6 @@ struct edp_info {
 
 /* V6 */
 struct integrated_info {
-	struct clock_voltage_caps {
-		/* The Voltage Index indicated by FUSE, same voltage index
-		shared with SCLK DPM fuse table */
-		uint32_t voltage_index;
-		/* Maximum clock supported with specified voltage index */
-		uint32_t max_supported_clk; /* in KHz */
-	} disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
-
 	struct display_connection_info {
 		struct external_display_path {
 			/* A bit vector to show what devices are supported */
-- 
2.54.0

[PATCH 08/14] drm/amd/display: Delete dm_pp_clocks_state

[Timur Kristóf]

It isn't used by anything anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../drm/amd/display/dc/dm_services_types.h    | 23 -------------------
 1 file changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index f114ab819afd..b3505d93503f 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -36,30 +36,7 @@ struct dm_pp_clock_range {
 	int max_khz;
 };
 
-enum dm_pp_clocks_state {
-	DM_PP_CLOCKS_STATE_INVALID,
-	DM_PP_CLOCKS_STATE_ULTRA_LOW,
-	DM_PP_CLOCKS_STATE_LOW,
-	DM_PP_CLOCKS_STATE_NOMINAL,
-	DM_PP_CLOCKS_STATE_PERFORMANCE,
-
-	/* Starting from DCE11, Max 8 levels of DPM state supported. */
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
-	/* to be backward compatible */
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
-	DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
-
-	DM_PP_CLOCKS_MAX_STATES
-};
-
 struct dm_pp_gpu_clock_range {
-	enum dm_pp_clocks_state clock_state;
 	struct dm_pp_clock_range sclk;
 	struct dm_pp_clock_range mclk;
 	struct dm_pp_clock_range eclk;
-- 
2.54.0

[PATCH 09/14] drm/amd/pm: Delete unused get_display_power_level() function

[Timur Kristóf]

Was not called from anywhere.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h   |  2 --
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 12 ------------
 2 files changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 1bbf531de5ed..ac05a12e71bd 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -476,8 +476,6 @@ struct amd_pm_funcs {
 	u32 (*get_mclk)(void *handle, bool low);
 	int (*display_configuration_change)(void *handle,
 		const struct amd_pp_display_configuration *input);
-	int (*get_display_power_level)(void *handle,
-		struct amd_pp_simple_clock_info *output);
 	int (*get_current_clocks)(void *handle,
 		struct amd_pp_clock_info *clocks);
 	int (*get_clock_by_type)(void *handle,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 0bbb89788335..4c2c40e8123b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1020,17 +1020,6 @@ static int pp_display_configuration_change(void *handle,
 	return 0;
 }
 
-static int pp_get_display_power_level(void *handle,
-		struct amd_pp_simple_clock_info *output)
-{
-	struct pp_hwmgr *hwmgr = handle;
-
-	if (!hwmgr || !hwmgr->pm_en || !output)
-		return -EINVAL;
-
-	return phm_get_dal_power_level(hwmgr, output);
-}
-
 static int pp_get_current_clocks(void *handle,
 		struct amd_pp_clock_info *clocks)
 {
@@ -1588,7 +1577,6 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
 	.get_sclk = pp_dpm_get_sclk,
 	.get_mclk = pp_dpm_get_mclk,
 	.display_configuration_change = pp_display_configuration_change,
-	.get_display_power_level = pp_get_display_power_level,
 	.get_current_clocks = pp_get_current_clocks,
 	.get_clock_by_type = pp_get_clock_by_type,
 	.get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
-- 
2.54.0

[PATCH 10/14] drm/amd/pm: Delete dummy get_dal_power_level implementations

[Timur Kristóf]

These implementations did not actually return
the DAL power level, so they were effectively
a no-op.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c    |  7 -------
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c   | 15 ---------------
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c   | 16 ----------------
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c   | 17 -----------------
 4 files changed, 55 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 8de8d66df95f..5be6f82ecc6f 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -963,12 +963,6 @@ static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time
 	return 0;
 }
 
-static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-	return -EINVAL;
-}
-
 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask)
 {
@@ -1664,7 +1658,6 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
 	.store_cc6_data = smu10_store_cc6_data,
 	.force_clock_level = smu10_force_clock_level,
 	.emit_clock_levels = smu10_emit_clock_levels,
-	.get_dal_power_level = smu10_get_dal_power_level,
 	.get_performance_level = smu10_get_performance_level,
 	.get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
 	.get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 1b8a57d98759..12f47ec87997 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -4387,20 +4387,6 @@ static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
 		return AMD_FAN_CTRL_AUTO;
 }
 
-static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-	struct phm_ppt_v2_information *table_info =
-			(struct phm_ppt_v2_information *)hwmgr->pptable;
-	struct phm_clock_and_voltage_limits *max_limits =
-			&table_info->max_clock_voltage_on_ac;
-
-	info->engine_max_clock = max_limits->sclk;
-	info->memory_max_clock = max_limits->mclk;
-
-	return 0;
-}
-
 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
 		struct pp_clock_levels_with_latency *clocks)
 {
@@ -5645,7 +5631,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
 	.set_fan_control_mode = vega10_set_fan_control_mode,
 	.get_fan_control_mode = vega10_get_fan_control_mode,
 	.read_sensor = vega10_read_sensor,
-	.get_dal_power_level = vega10_get_dal_power_level,
 	.get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
 	.get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
 	.set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index 5a987a535e73..6f2bb8fe0317 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -1822,21 +1822,6 @@ static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
 		return AMD_FAN_CTRL_AUTO;
 }
 
-static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-#if 0
-	struct phm_ppt_v2_information *table_info =
-			(struct phm_ppt_v2_information *)hwmgr->pptable;
-	struct phm_clock_and_voltage_limits *max_limits =
-			&table_info->max_clock_voltage_on_ac;
-
-	info->engine_max_clock = max_limits->sclk;
-	info->memory_max_clock = max_limits->mclk;
-#endif
-	return 0;
-}
-
 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
 		uint32_t *clock,
 		PPCLK_e clock_select,
@@ -2963,7 +2948,6 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
 	.set_fan_control_mode = vega12_set_fan_control_mode,
 	.get_fan_control_mode = vega12_get_fan_control_mode,
 	.read_sensor = vega12_read_sensor,
-	.get_dal_power_level = vega12_get_dal_power_level,
 	.get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
 	.get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
 	.set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 5193b7d0e11b..2a06d3e0253f 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -2796,22 +2796,6 @@ static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 	}
 }
 
-static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-#if 0
-	struct phm_ppt_v2_information *table_info =
-			(struct phm_ppt_v2_information *)hwmgr->pptable;
-	struct phm_clock_and_voltage_limits *max_limits =
-			&table_info->max_clock_voltage_on_ac;
-
-	info->engine_max_clock = max_limits->sclk;
-	info->memory_max_clock = max_limits->mclk;
-#endif
-	return 0;
-}
-
-
 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
 		struct pp_clock_levels_with_latency *clocks)
 {
@@ -4446,7 +4430,6 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
 	/* export to DAL */
 	.get_sclk = vega20_dpm_get_sclk,
 	.get_mclk = vega20_dpm_get_mclk,
-	.get_dal_power_level = vega20_get_dal_power_level,
 	.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
 	.get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
 	.set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
-- 
2.54.0

[PATCH 11/14] drm/amd/pm: Delete non-functional SMU8 get_dal_power_level implementation

[Timur Kristóf]

This function was effectively a no-op because it always
returned the maximum possible power level, because the
maximum voltage is in millivolts while the dependency
table didn't contain actual voltages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   | 22 -------------------
 1 file changed, 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 736e5a8af477..8a37c745cb11 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -1522,27 +1522,6 @@ static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 	return 0;
 }
 
-static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-	uint32_t i;
-	const struct phm_clock_voltage_dependency_table *table =
-			hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
-	const struct phm_clock_and_voltage_limits *limits =
-			&hwmgr->dyn_state.max_clock_voltage_on_ac;
-
-	info->engine_max_clock = limits->sclk;
-	info->memory_max_clock = limits->mclk;
-
-	for (i = table->count - 1; i > 0; i--) {
-		if (limits->vddc >= table->entries[i].v) {
-			info->level = table->entries[i].clk;
-			return 0;
-		}
-	}
-	return -EINVAL;
-}
-
 static int smu8_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask)
 {
@@ -2063,7 +2042,6 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
 	.store_cc6_data = smu8_store_cc6_data,
 	.force_clock_level = smu8_force_clock_level,
 	.emit_clock_levels = smu8_emit_clock_levels,
-	.get_dal_power_level = smu8_get_dal_power_level,
 	.get_performance_level = smu8_get_performance_level,
 	.get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks,
 	.get_clock_by_type = smu8_get_clock_by_type,
-- 
2.54.0

[PATCH 12/14] drm/amd/pm: Delete vddc_dep_on_dal_pwrl

[Timur Kristóf]

It was not used by anything anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../amd/pm/powerplay/hwmgr/processpptables.c  |  1 -
 .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  | 41 ------------------
 .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   | 42 -------------------
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c |  3 --
 drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h  |  2 -
 5 files changed, 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
index f06b29e33ba4..00e8f1be87e7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
@@ -1324,7 +1324,6 @@ static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
 	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
 	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
-	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
 	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
 	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 5be6f82ecc6f..f5c1f483dec8 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -127,42 +127,6 @@ static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int smu10_init_dynamic_state_adjustment_rule_settings(
-							struct pp_hwmgr *hwmgr)
-{
-	int count = 8;
-	struct phm_clock_voltage_dependency_table *table_clk_vlt;
-
-	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count),
-				GFP_KERNEL);
-
-	if (NULL == table_clk_vlt) {
-		pr_err("Can not allocate memory!\n");
-		return -ENOMEM;
-	}
-
-	table_clk_vlt->count = count;
-	table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-	table_clk_vlt->entries[0].v = 0;
-	table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
-	table_clk_vlt->entries[1].v = 1;
-	table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
-	table_clk_vlt->entries[2].v = 2;
-	table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
-	table_clk_vlt->entries[3].v = 3;
-	table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
-	table_clk_vlt->entries[4].v = 4;
-	table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
-	table_clk_vlt->entries[5].v = 5;
-	table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
-	table_clk_vlt->entries[6].v = 6;
-	table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
-	table_clk_vlt->entries[7].v = 7;
-	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-
-	return 0;
-}
-
 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 {
 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
@@ -176,8 +140,6 @@ static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 	smu10_construct_max_power_limits_table (hwmgr,
 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
 
-	smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
-
 	return 0;
 }
 
@@ -612,9 +574,6 @@ static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 	kfree(pinfo->vdd_dep_on_phyclk);
 	pinfo->vdd_dep_on_phyclk = NULL;
 
-	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
 	kfree(hwmgr->backend);
 	hwmgr->backend = NULL;
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 8a37c745cb11..63a1e3748e5c 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -270,42 +270,6 @@ static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int smu8_init_dynamic_state_adjustment_rule_settings(
-			struct pp_hwmgr *hwmgr,
-			ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
-{
-	struct phm_clock_voltage_dependency_table *table_clk_vlt;
-
-	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 8),
-				GFP_KERNEL);
-
-	if (NULL == table_clk_vlt) {
-		pr_err("Can not allocate memory!\n");
-		return -ENOMEM;
-	}
-
-	table_clk_vlt->count = 8;
-	table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-	table_clk_vlt->entries[0].v = 0;
-	table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
-	table_clk_vlt->entries[1].v = 1;
-	table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
-	table_clk_vlt->entries[2].v = 2;
-	table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
-	table_clk_vlt->entries[3].v = 3;
-	table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
-	table_clk_vlt->entries[4].v = 4;
-	table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
-	table_clk_vlt->entries[5].v = 5;
-	table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
-	table_clk_vlt->entries[6].v = 6;
-	table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
-	table_clk_vlt->entries[7].v = 7;
-	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-
-	return 0;
-}
-
 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
 {
 	struct smu8_hwmgr *data = hwmgr->backend;
@@ -404,9 +368,6 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
 	smu8_construct_max_power_limits_table (hwmgr,
 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
 
-	smu8_init_dynamic_state_adjustment_rule_settings(hwmgr,
-				    &info->sDISPCLK_Voltage[0]);
-
 	return result;
 }
 
@@ -1150,9 +1111,6 @@ static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
 	if (hwmgr != NULL) {
-		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
 		kfree(hwmgr->backend);
 		hwmgr->backend = NULL;
 	}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 12f47ec87997..8b8c4e899878 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -814,9 +814,6 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 
 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
-	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
 	kfree(hwmgr->backend);
 	hwmgr->backend = NULL;
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
index 3ae45eac0c5c..1ee7e3044272 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
@@ -540,7 +540,6 @@ struct phm_ppt_v1_information {
 	struct phm_clock_array *valid_dcefclk_values;
 	struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 	struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
-	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 	struct phm_ppm_table *ppm_parameter_table;
 	struct phm_cac_tdp_table *cac_dtp_table;
 	struct phm_tdp_table *tdp_table;
@@ -632,7 +631,6 @@ struct phm_dynamic_state_info {
 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_display_clock;
-	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 	struct phm_clock_array                    *valid_sclk_values;
 	struct phm_clock_array                    *valid_mclk_values;
 	struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
-- 
2.54.0

[PATCH 13/14] drm/amd/pm: Delete get_dal_power_level

[Timur Kristóf]

Not needed anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   |  3 ---
 drivers/gpu/drm/amd/include/dm_pp_interface.h          |  1 -
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c       | 10 ----------
 .../gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c   | 10 ----------
 drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h |  3 ---
 drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h           |  2 --
 6 files changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index a3ee580d8dd1..2cdb8fea504a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -288,7 +288,6 @@ bool dm_pp_get_clock_levels_by_type(
 		DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
 		validation_clks.engine_max_clock = 72000;
 		validation_clks.memory_max_clock = 80000;
-		validation_clks.level = 0;
 	}
 
 	DRM_INFO("DM_PPLIB: Validation clocks:\n");
@@ -296,8 +295,6 @@ bool dm_pp_get_clock_levels_by_type(
 			validation_clks.engine_max_clock);
 	DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
 			validation_clks.memory_max_clock);
-	DRM_INFO("DM_PPLIB:    level           : %d\n",
-			validation_clks.level);
 
 	/* Translate 10 kHz to kHz. */
 	validation_clks.engine_max_clock *= 10;
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 349544504c93..10747a1ceda9 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -113,7 +113,6 @@ struct amd_pp_display_configuration {
 struct amd_pp_simple_clock_info {
 	uint32_t	engine_max_clock;
 	uint32_t	memory_max_clock;
-	uint32_t	level;
 };
 
 enum PP_DAL_POWERLEVEL {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 4c2c40e8123b..a53577a83f1b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1023,7 +1023,6 @@ static int pp_display_configuration_change(void *handle,
 static int pp_get_current_clocks(void *handle,
 		struct amd_pp_clock_info *clocks)
 {
-	struct amd_pp_simple_clock_info simple_clocks = { 0 };
 	struct pp_clock_info hw_clocks;
 	struct pp_hwmgr *hwmgr = handle;
 	int ret = 0;
@@ -1031,8 +1030,6 @@ static int pp_get_current_clocks(void *handle,
 	if (!hwmgr || !hwmgr->pm_en)
 		return -EINVAL;
 
-	phm_get_dal_power_level(hwmgr, &simple_clocks);
-
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_PowerContainment))
 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
@@ -1057,11 +1054,6 @@ static int pp_get_current_clocks(void *handle,
 	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 
-	if (simple_clocks.level == 0)
-		clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
-	else
-		clocks->max_clocks_state = simple_clocks.level;
-
 	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
 		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 		clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
@@ -1138,8 +1130,6 @@ static int pp_get_display_mode_validation_clocks(void *handle,
 	if (!hwmgr || !hwmgr->pm_en || !clocks)
 		return -EINVAL;
 
-	clocks->level = PP_DAL_POWERLEVEL_7;
-
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
 		ret = phm_get_max_high_clocks(hwmgr, clocks);
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
index a59677cf8dfc..72c2d3b69a03 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
@@ -328,16 +328,6 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info)
-{
-	PHM_FUNC_CHECK(hwmgr);
-
-	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
-		return -EINVAL;
-	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
-}
-
 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
index 915f1b8e4dba..36dcad065fae 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
@@ -426,9 +426,6 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 		const struct amd_pp_display_configuration *display_config);
 
-extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-		struct amd_pp_simple_clock_info *info);
-
 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
 
 extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
index 1ee7e3044272..fc1ffe1b2c97 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
@@ -292,8 +292,6 @@ struct pp_hwmgr_func {
 	int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 				bool cc6_disable, bool pstate_disable,
 				bool pstate_switch_disable);
-	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
-			struct amd_pp_simple_clock_info *info);
 	int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 			PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 	int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
-- 
2.54.0

[PATCH 14/14] drm/amd/pm: Delete PP_DAL_POWERLEVEL

[Timur Kristóf]

Not used and not needed anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/include/dm_pp_interface.h | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 10747a1ceda9..e3d40fb37103 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -115,23 +115,6 @@ struct amd_pp_simple_clock_info {
 	uint32_t	memory_max_clock;
 };
 
-enum PP_DAL_POWERLEVEL {
-	PP_DAL_POWERLEVEL_INVALID = 0,
-	PP_DAL_POWERLEVEL_ULTRALOW,
-	PP_DAL_POWERLEVEL_LOW,
-	PP_DAL_POWERLEVEL_NOMINAL,
-	PP_DAL_POWERLEVEL_PERFORMANCE,
-
-	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-};
-
 struct amd_pp_clock_info {
 	uint32_t min_engine_clock;
 	uint32_t max_engine_clock;
@@ -141,7 +124,6 @@ struct amd_pp_clock_info {
 	uint32_t max_bus_bandwidth;
 	uint32_t max_engine_clock_in_sr;
 	uint32_t min_engine_clock_in_sr;
-	enum PP_DAL_POWERLEVEL max_clocks_state;
 };
 
 enum amd_pp_clock_type {
-- 
2.54.0

Re: [PATCH 00/14] drm/amd: Delete defunct DAL power level code

[Christian König]

On 5/19/26 12:21, Timur Kristóf wrote:
> Delete unused code related to DAL power levels.
> It seems that the DAL power level concept has been
> never fully implemented and was thus non-functional
> in amdgpu.
> 
> DCE 11.0 and 11.2 never actually relied on the
> power level because they calculate all necessary
> power requirements in dce_calcs and communicate
> that using dm_pp_apply_display_requirements() to
> the power management code.
> 
> DCE 6, 8 and 10 also didn't rely on power levels
> because they always just set the maximum possible
> display clock and the power management code
> already takes that into account when setting the
> power state. This was somewhat improved recently
> by also using dm_pp_apply_display_requirements()
> on these DCE versions.
> 
> The code base for newer GPUs doesn't use the
> concept of power levels anymore either, so
> this change reduces the maintenance burden
> of the old DCE code.
> 
> On the DC side:
> 
> dm_pp_apply_power_level_change_request() was never
> implemented in amdgpu_dm, and DC has been working
> fine for years without it. Let's delete the dummy
> function and the code that calls it.
> 
> With that, we can also delete the power levels
> and the static arrays containing hardcoded power
> level values. These were never used for anything,
> only for finding the maximum supported display clock.
> 
> On the AMDGPU PM side:
> 
> The get_dal_power_level() implementations were
> dummy on SMU10, Vega10, Vega12 and Vega20 meaning
> that they didn't return an actual DAL power level,
> and were non-functional on SMU8 which always
> returned the highest possible power level.
> Nothing actually relied on the power level
> returned by these functions. Let's delete them.
> 
> What's next:
> 
> After this code cleanup lands, I have plans to
> further improve display power management on old DCE.
> 
> Changes in v2:
> 
> Applied review suggestions.

Acked-by: Christian König <christian.koenig@amd.com> to the full series.

Thanks a lot for taking care of that.

Regards,
Christian.

> 
> Timur Kristóf (14):
>   drm/amd/display: Delete unimplemented
>     dm_pp_apply_power_level_change_request() (v2)
>   drm/amd/display: Delete dce_get_required_clocks_state()
>   drm/amd/display: Remove min/max clock levels from clk_mgr (v2)
>   drm/amd/display: Delete max_clocks_state
>   drm/amd/display: Set max supported display clock without
>     max_clks_by_state (v2)
>   drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2)
>   drm/amd/display: Delete disp_clk_voltage from integrated info (v2)
>   drm/amd/display: Delete dm_pp_clocks_state
>   drm/amd/pm: Delete unused get_display_power_level() function
>   drm/amd/pm: Delete dummy get_dal_power_level implementations
>   drm/amd/pm: Delete non-functional SMU8 get_dal_power_level
>     implementation
>   drm/amd/pm: Delete vddc_dep_on_dal_pwrl
>   drm/amd/pm: Delete get_dal_power_level
>   drm/amd/pm: Delete PP_DAL_POWERLEVEL
> 
>  .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  55 -------
>  .../gpu/drm/amd/display/dc/bios/bios_parser.c |  36 -----
>  .../drm/amd/display/dc/bios/bios_parser2.c    |  18 ---
>  .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 144 ++----------------
>  .../display/dc/clk_mgr/dce100/dce_clk_mgr.h   |   3 -
>  .../dc/clk_mgr/dce110/dce110_clk_mgr.c        |  25 ---
>  .../dc/clk_mgr/dce112/dce112_clk_mgr.c        |  41 -----
>  .../dc/clk_mgr/dce120/dce120_clk_mgr.c        |  16 --
>  drivers/gpu/drm/amd/display/dc/dm_services.h  |   8 -
>  .../drm/amd/display/dc/dm_services_types.h    |  30 ----
>  .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 --
>  .../display/include/grph_object_ctrl_defs.h   |   9 --
>  drivers/gpu/drm/amd/include/dm_pp_interface.h |  19 ---
>  .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 -
>  .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |  22 ---
>  .../amd/pm/powerplay/hwmgr/hardwaremanager.c  |  10 --
>  .../amd/pm/powerplay/hwmgr/processpptables.c  |   1 -
>  .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  |  48 ------
>  .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   |  64 --------
>  .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c |  18 ---
>  .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c |  16 --
>  .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c |  17 ---
>  .../amd/pm/powerplay/inc/hardwaremanager.h    |   3 -
>  drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h  |   4 -
>  24 files changed, 11 insertions(+), 608 deletions(-)
> 

Re: [PATCH 00/14] drm/amd: Delete defunct DAL power level code

[Alex Deucher]

Applied the series.

Alex

On Tue, May 19, 2026 at 9:14 AM Christian König
<christian.koenig@amd.com> wrote:
>
> On 5/19/26 12:21, Timur Kristóf wrote:
> > Delete unused code related to DAL power levels.
> > It seems that the DAL power level concept has been
> > never fully implemented and was thus non-functional
> > in amdgpu.
> >
> > DCE 11.0 and 11.2 never actually relied on the
> > power level because they calculate all necessary
> > power requirements in dce_calcs and communicate
> > that using dm_pp_apply_display_requirements() to
> > the power management code.
> >
> > DCE 6, 8 and 10 also didn't rely on power levels
> > because they always just set the maximum possible
> > display clock and the power management code
> > already takes that into account when setting the
> > power state. This was somewhat improved recently
> > by also using dm_pp_apply_display_requirements()
> > on these DCE versions.
> >
> > The code base for newer GPUs doesn't use the
> > concept of power levels anymore either, so
> > this change reduces the maintenance burden
> > of the old DCE code.
> >
> > On the DC side:
> >
> > dm_pp_apply_power_level_change_request() was never
> > implemented in amdgpu_dm, and DC has been working
> > fine for years without it. Let's delete the dummy
> > function and the code that calls it.
> >
> > With that, we can also delete the power levels
> > and the static arrays containing hardcoded power
> > level values. These were never used for anything,
> > only for finding the maximum supported display clock.
> >
> > On the AMDGPU PM side:
> >
> > The get_dal_power_level() implementations were
> > dummy on SMU10, Vega10, Vega12 and Vega20 meaning
> > that they didn't return an actual DAL power level,
> > and were non-functional on SMU8 which always
> > returned the highest possible power level.
> > Nothing actually relied on the power level
> > returned by these functions. Let's delete them.
> >
> > What's next:
> >
> > After this code cleanup lands, I have plans to
> > further improve display power management on old DCE.
> >
> > Changes in v2:
> >
> > Applied review suggestions.
>
> Acked-by: Christian König <christian.koenig@amd.com> to the full series.
>
> Thanks a lot for taking care of that.
>
> Regards,
> Christian.
>
> >
> > Timur Kristóf (14):
> >   drm/amd/display: Delete unimplemented
> >     dm_pp_apply_power_level_change_request() (v2)
> >   drm/amd/display: Delete dce_get_required_clocks_state()
> >   drm/amd/display: Remove min/max clock levels from clk_mgr (v2)
> >   drm/amd/display: Delete max_clocks_state
> >   drm/amd/display: Set max supported display clock without
> >     max_clks_by_state (v2)
> >   drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2)
> >   drm/amd/display: Delete disp_clk_voltage from integrated info (v2)
> >   drm/amd/display: Delete dm_pp_clocks_state
> >   drm/amd/pm: Delete unused get_display_power_level() function
> >   drm/amd/pm: Delete dummy get_dal_power_level implementations
> >   drm/amd/pm: Delete non-functional SMU8 get_dal_power_level
> >     implementation
> >   drm/amd/pm: Delete vddc_dep_on_dal_pwrl
> >   drm/amd/pm: Delete get_dal_power_level
> >   drm/amd/pm: Delete PP_DAL_POWERLEVEL
> >
> >  .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  55 -------
> >  .../gpu/drm/amd/display/dc/bios/bios_parser.c |  36 -----
> >  .../drm/amd/display/dc/bios/bios_parser2.c    |  18 ---
> >  .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 144 ++----------------
> >  .../display/dc/clk_mgr/dce100/dce_clk_mgr.h   |   3 -
> >  .../dc/clk_mgr/dce110/dce110_clk_mgr.c        |  25 ---
> >  .../dc/clk_mgr/dce112/dce112_clk_mgr.c        |  41 -----
> >  .../dc/clk_mgr/dce120/dce120_clk_mgr.c        |  16 --
> >  drivers/gpu/drm/amd/display/dc/dm_services.h  |   8 -
> >  .../drm/amd/display/dc/dm_services_types.h    |  30 ----
> >  .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 --
> >  .../display/include/grph_object_ctrl_defs.h   |   9 --
> >  drivers/gpu/drm/amd/include/dm_pp_interface.h |  19 ---
> >  .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 -
> >  .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |  22 ---
> >  .../amd/pm/powerplay/hwmgr/hardwaremanager.c  |  10 --
> >  .../amd/pm/powerplay/hwmgr/processpptables.c  |   1 -
> >  .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  |  48 ------
> >  .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   |  64 --------
> >  .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c |  18 ---
> >  .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c |  16 --
> >  .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c |  17 ---
> >  .../amd/pm/powerplay/inc/hardwaremanager.h    |   3 -
> >  drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h  |   4 -
> >  24 files changed, 11 insertions(+), 608 deletions(-)
> >
>