From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: vkoul@kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org
Subject: Re: [PATCH v3 05/13] dmaengine: dw-edma: Add partial channel ownership mode
Date: Sat, 20 Jun 2026 17:16:03 +0000 [thread overview]
Message-ID: <20260620171603.DA6211F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260620170040.3756043-6-den@valinux.co.jp>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [High] In partial ownership mode, `dw_edma_probe()` skips the global core reset but fails to quiesce the DMA channels it owns, exposing the driver to fatal race conditions if the hardware is active from a prior state.
Pre-existing issues:
- [High] Teardown order in `dw_edma_remove()` disables hardware and frees IRQs before unregistering the DMA device.
--
commit b3810423aa75ab232c8bec54552ca8cb72acd420
Author: Koichiro Den <den@valinux.co.jp>
dmaengine: dw-edma: Add partial channel ownership mode
This commit adds a partial ownership flag to allow a dw-edma instance to
represent a subset of a controller shared with another OS instance. It skips
the initial core reset during probe and uses a limited quiesce path during
remove, while enforcing ownership granularity for shared registers.
> diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
> index c782eaa12021e..d87791205837b 100644
> --- a/drivers/dma/dw-edma/dw-edma-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-core.c
[ ... ]
> @@ -1128,8 +1156,10 @@ int dw_edma_probe(struct dw_edma_chip *chip)
> snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%s",
> dev_name(chip->dev));
>
> - /* Disable eDMA, only to establish the ideal initial conditions */
> - dw_edma_core_off(dw);
> + if (!(chip->flags & DW_EDMA_CHIP_PARTIAL)) {
> + /* Disable eDMA only when this instance owns the controller. */
> + dw_edma_core_off(dw);
> + }
[Severity: High]
If the instance is in partial ownership mode, could the hardware be
active from a prior state (e.g. kexec or an endpoint driver)?
By skipping the global core reset without calling dw_edma_core_quiesce()
in its place, the hardware remains active. The driver requests IRQs via
dw_edma_irq_request() just below this, before calling
dw_edma_channel_setup().
If a pending interrupt fires during this window, the handler will invoke
dw_edma_done_interrupt(), which locks and dereferences uninitialized
vchan structures:
dw_edma_interrupt_write()
dw_edma_done_interrupt()
spin_lock_irqsave(&chan->vc.lock, flags)
vchan_next_desc()
Since vchan_init() has not been called yet during dw_edma_channel_setup(),
does this sequence lead to a kernel panic or NULL pointer dereference?
>
> /* Request IRQs */
> err = dw_edma_irq_request(dw, &wr_alloc, &rd_alloc);
[ ... ]
> @@ -1173,8 +1203,10 @@ int dw_edma_remove(struct dw_edma_chip *chip)
> if (!dw)
> return -ENODEV;
>
> - /* Disable eDMA */
> - dw_edma_core_off(dw);
> + if (chip->flags & DW_EDMA_CHIP_PARTIAL)
> + dw_edma_core_quiesce(dw);
> + else
> + dw_edma_core_off(dw);
>
> /* Free irqs */
> for (i = (dw->nr_irqs - 1); i >= 0; i--)
> free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]);
> dw_edma_emul_irq_free(dw);
>
> /* Deregister eDMA device */
> dma_async_device_unregister(&dw->dma);
[Severity: High]
This is a pre-existing issue, but does the teardown order in
dw_edma_remove() expose the driver to a race condition?
The hardware is disabled or quiesced and the IRQs are freed before
dma_async_device_unregister() is called. By leaving the dmaengine device
registered during this teardown, clients can still issue new transfers via
vchan_issue_pending().
This would invoke dw_edma_v0_core_start(), writing to registers of a
disabled DMA engine, potentially racing with dw_edma_core_quiesce().
Additionally, transfers submitted after free_irq() will hang indefinitely
since completion interrupts are no longer available.
Should dma_async_device_unregister() be called before tearing down the
underlying hardware and interrupts?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260620170040.3756043-1-den@valinux.co.jp?part=5
next prev parent reply other threads:[~2026-06-20 17:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-20 17:00 [PATCH v3 00/13] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-06-20 17:00 ` [PATCH v3 01/13] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-06-20 17:13 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 02/13] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-06-20 17:15 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 03/13] dmaengine: dw-edma: Add delegated channel request helpers Koichiro Den
2026-06-20 17:25 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 04/13] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-06-20 17:16 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 05/13] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-06-20 17:16 ` sashiko-bot [this message]
2026-06-20 17:00 ` [PATCH v3 06/13] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-06-20 17:15 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 07/13] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-06-20 17:11 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 08/13] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-06-20 17:11 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 09/13] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-06-20 17:13 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 10/13] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-06-20 17:18 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 11/13] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-06-20 17:00 ` [PATCH v3 12/13] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-06-20 17:14 ` sashiko-bot
2026-06-20 17:00 ` [PATCH v3 13/13] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-06-20 17:16 ` sashiko-bot
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