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From: Rahul Bhansali <rbhansali@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	Kiran Kumar K <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>,
	Harman Kalra <hkalra@marvell.com>,
	Rahul Bhansali <rbhansali@marvell.com>
Cc: <jerinj@marvell.com>, Alok Mishra <almishra@marvell.com>,
	<stable@dpdk.org>
Subject: [PATCH 11/14] common/cnxk: fix CPT CQ base address calculation
Date: Thu, 17 Sep 2026 12:40:13 +0530	[thread overview]
Message-ID: <20260917071016.2366467-11-rbhansali@marvell.com> (raw)
In-Reply-To: <20260917071016.2366467-1-rbhansali@marvell.com>

From: Alok Mishra <almishra@marvell.com>

In nix_inl_cpt_cq_cb(), the CPT CQ base address is reconstructed by
left-shifting CPT_LF_CQ_BASE.s.addr by 7 bits. Since s.addr is a 46-bit
field, the shift operation truncates the result to 46 bits, discarding
any higher address bits.

This produces an incorrect CQ base address for higher virtual
addresses, causing invalid memory access.

Fixed by casting s.addr to uint64_t before shifting, ensuring the full
64-bit address is preserved.

Fixes: 63b16e267106 ("common/cnxk: fix CPT CQ roll over handling")
Cc: stable@dpdk.org

Signed-off-by: Alok Mishra <almishra@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index dcf77a29a5..977b5e05e2 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -103,7 +103,8 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 	}
 
 	for (i = 0; i < count; i++) {
-		cq_s = (struct cpt_cq_s *)(uintptr_t)(((cq_base.s.addr << 7)) + (head << 5));
+		cq_s = (struct cpt_cq_s *)(uintptr_t)((((uint64_t)cq_base.s.addr << 7)) +
+						      (head << 5));
 
 		if (cq_s->w0.s.uc_compcode && cq_s->w0.s.compcode) {
 			switch (cq_s->w2.s.fmt & fmt_msk) {
-- 
2.34.1


  parent reply	other threads:[~2026-09-17  7:15 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-17  7:10 [PATCH 01/14] net/cnxk: fix packet length handling Rahul Bhansali
2026-09-17  7:10 ` [PATCH 02/14] common/cnxk: disable CPT drop error in CQ Rahul Bhansali
2026-09-17 16:14   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 03/14] common/cnxk: fix NIX QINT count reset Rahul Bhansali
2026-09-17 16:14   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 04/14] common/cnxk: update channel mask for cn20k Rahul Bhansali
2026-09-17  7:10 ` [PATCH 05/14] common/cnxk: update macro " Rahul Bhansali
2026-09-17  7:10 ` [PATCH 06/14] common/cnxk: fix null deref and irq ack in CPT CQ handler Rahul Bhansali
2026-09-17 16:15   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 07/14] common/cnxk: derive mbuf from CPT CQ in inline IRQ path Rahul Bhansali
2026-09-17 16:15   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 08/14] net/cnxk: resolve mbuf from CPT CQ format in SSO work cb Rahul Bhansali
2026-09-17 16:16   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 09/14] common/cnxk: update bpid config for cn20k Rahul Bhansali
2026-09-17 16:16   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 10/14] net/cnxk: add MSNS inb SA and CN20K CPT result struct Rahul Bhansali
2026-09-17 16:16   ` Stephen Hemminger
2026-09-17  7:10 ` Rahul Bhansali [this message]
2026-09-17  7:10 ` [PATCH 12/14] common/cnxk: update mode param for link speed Rahul Bhansali
2026-09-17 16:17   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 13/14] common/cnxk: support for cn20k legacy msns mode Rahul Bhansali
2026-09-17 16:18   ` Stephen Hemminger
2026-09-17  7:10 ` [PATCH 14/14] net/cnxk: fix custom inbound SA condition check Rahul Bhansali
2026-09-17 16:12 ` [PATCH 01/14] net/cnxk: fix packet length handling Stephen Hemminger
2026-09-17 16:29 ` Stephen Hemminger

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