From: Rahul Bhansali <rbhansali@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>
Cc: <jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>
Subject: [PATCH 09/14] common/cnxk: update bpid config for cn20k
Date: Thu, 17 Sep 2026 12:40:11 +0530 [thread overview]
Message-ID: <20260917071016.2366467-9-rbhansali@marvell.com> (raw)
In-Reply-To: <20260917071016.2366467-1-rbhansali@marvell.com>
For cn20k, Rx chan bpid config range increased to 10 bit from 8
bits. These extra bits are reserved in cn10k platform so separate
platform specific bpid range mask is not required.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_fc.c | 30 +++++++++++++++--------------
drivers/common/cnxk/roc_nix_queue.c | 1 +
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index ddabd15a5d..abf923b722 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -51,7 +51,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)
nix->chan_cnt = rsp->chan_cnt;
for (i = 0; i < rsp->chan_cnt; i++)
- nix->bpid[i] = rsp->chan_bpid[i] & 0x1FF;
+ nix->bpid[i] = rsp->chan_bpid[i] & 0x7FF;
} else {
req = mbox_alloc_msg_nix_bp_disable(mbox);
if (req == NULL)
@@ -86,7 +86,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)
rc = mbox_process_msg(mbox, (void *)&rsp);
if (rc)
goto exit;
- nix->cpt_lbpid = rsp->chan_bpid[0] & 0x1FF;
+ nix->cpt_lbpid = rsp->chan_bpid[0] & 0x7FF;
}
/* CPT to NIX BP on all channels */
@@ -333,6 +333,8 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
if (fc_cfg->cq_cfg.enable) {
aq->cq.bpid = nix->bpid[fc_cfg->cq_cfg.tc];
aq->cq_mask.bpid = ~(aq->cq_mask.bpid);
+ aq->cq.bpid_ext = (nix->bpid[fc_cfg->cq_cfg.tc] >> 9) & 0x3;
+ aq->cq_mask.bpid_ext = ~(aq->cq_mask.bpid_ext);
aq->cq.bp = fc_cfg->cq_cfg.cq_bp;
aq->cq_mask.bp = ~(aq->cq_mask.bp);
}
@@ -903,33 +905,33 @@ roc_nix_chan_bpid_set(struct roc_nix *roc_nix, uint16_t chan, uint64_t bpid, int
return rc;
if (ena) {
- if ((((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) ||
- (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) ||
- (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid))
+ if ((((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(10, 0)) == bpid) ||
+ (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(10, 0)) == bpid) ||
+ (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(10, 0)) == bpid))
return 0;
if (!(cfg & BIT_ULL(NIX_BPID1_ENA))) {
- cfg &= ~GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF);
+ cfg &= ~GENMASK_ULL(NIX_BPID1_OFF + 10, NIX_BPID1_OFF);
cfg |= (((uint64_t)bpid << NIX_BPID1_OFF) | BIT_ULL(NIX_BPID1_ENA));
} else if (!(cfg & BIT_ULL(NIX_BPID2_ENA))) {
- cfg &= ~GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF);
+ cfg &= ~GENMASK_ULL(NIX_BPID2_OFF + 10, NIX_BPID2_OFF);
cfg |= (((uint64_t)bpid << NIX_BPID2_OFF) | BIT_ULL(NIX_BPID2_ENA));
} else if (!(cfg & BIT_ULL(NIX_BPID3_ENA))) {
- cfg &= ~GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF);
+ cfg &= ~GENMASK_ULL(NIX_BPID3_OFF + 10, NIX_BPID3_OFF);
cfg |= (((uint64_t)bpid << NIX_BPID3_OFF) | BIT_ULL(NIX_BPID3_ENA));
} else {
plt_nix_dbg("Exceed maximum BPIDs");
return -ENOSPC;
}
} else {
- if (((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) {
- cfg &= ~(GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF) |
+ if (((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(10, 0)) == bpid) {
+ cfg &= ~(GENMASK_ULL(NIX_BPID1_OFF + 10, NIX_BPID1_OFF) |
BIT_ULL(NIX_BPID1_ENA));
- } else if (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) {
- cfg &= ~(GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF) |
+ } else if (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(10, 0)) == bpid) {
+ cfg &= ~(GENMASK_ULL(NIX_BPID2_OFF + 10, NIX_BPID2_OFF) |
BIT_ULL(NIX_BPID2_ENA));
- } else if (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid) {
- cfg &= ~(GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF) |
+ } else if (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(10, 0)) == bpid) {
+ cfg &= ~(GENMASK_ULL(NIX_BPID3_OFF + 10, NIX_BPID3_OFF) |
BIT_ULL(NIX_BPID3_ENA));
} else {
plt_nix_dbg("BPID not found");
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index ad8f62f38f..8e7e597be2 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -1258,6 +1258,7 @@ roc_nix_cn20k_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
cq_ctx->lbpid_low = cpt_lbpid & 0x7;
cq_ctx->lbpid_med = (cpt_lbpid >> 3) & 0x7;
cq_ctx->lbpid_high = (cpt_lbpid >> 6) & 0x7;
+ cq_ctx->lbpid_ext = (cpt_lbpid >> 9) & 0x3;
cq_ctx->lbp_frac = NIX_CQ_LBP_THRESH_FRAC;
}
drop_thresh = NIX_CQ_SEC_BP_THRESH_LEVEL;
--
2.34.1
next prev parent reply other threads:[~2026-09-17 7:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 7:10 [PATCH 01/14] net/cnxk: fix packet length handling Rahul Bhansali
2026-09-17 7:10 ` [PATCH 02/14] common/cnxk: disable CPT drop error in CQ Rahul Bhansali
2026-09-17 16:14 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 03/14] common/cnxk: fix NIX QINT count reset Rahul Bhansali
2026-09-17 16:14 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 04/14] common/cnxk: update channel mask for cn20k Rahul Bhansali
2026-09-17 7:10 ` [PATCH 05/14] common/cnxk: update macro " Rahul Bhansali
2026-09-17 7:10 ` [PATCH 06/14] common/cnxk: fix null deref and irq ack in CPT CQ handler Rahul Bhansali
2026-09-17 16:15 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 07/14] common/cnxk: derive mbuf from CPT CQ in inline IRQ path Rahul Bhansali
2026-09-17 16:15 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 08/14] net/cnxk: resolve mbuf from CPT CQ format in SSO work cb Rahul Bhansali
2026-09-17 16:16 ` Stephen Hemminger
2026-09-17 7:10 ` Rahul Bhansali [this message]
2026-09-17 16:16 ` [PATCH 09/14] common/cnxk: update bpid config for cn20k Stephen Hemminger
2026-09-17 7:10 ` [PATCH 10/14] net/cnxk: add MSNS inb SA and CN20K CPT result struct Rahul Bhansali
2026-09-17 16:16 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 11/14] common/cnxk: fix CPT CQ base address calculation Rahul Bhansali
2026-09-17 7:10 ` [PATCH 12/14] common/cnxk: update mode param for link speed Rahul Bhansali
2026-09-17 16:17 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 13/14] common/cnxk: support for cn20k legacy msns mode Rahul Bhansali
2026-09-17 16:18 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 14/14] net/cnxk: fix custom inbound SA condition check Rahul Bhansali
2026-09-17 16:12 ` [PATCH 01/14] net/cnxk: fix packet length handling Stephen Hemminger
2026-09-17 16:29 ` Stephen Hemminger
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