From: Stephen Hemminger <stephen@networkplumber.org>
To: Rahul Bhansali <rbhansali@marvell.com>
Cc: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>,
Jerin Jacob <jerinj@marvell.com>, <stable@dpdk.org>
Subject: Re: [PATCH 03/14] common/cnxk: fix NIX QINT count reset
Date: Thu, 17 Sep 2026 09:14:43 -0700 [thread overview]
Message-ID: <20260917091443.0649942e@phoenix.local> (raw)
In-Reply-To: <20260917071016.2366467-3-rbhansali@marvell.com>
On Thu, 17 Sep 2026 12:40:05 +0530
Rahul Bhansali <rbhansali@marvell.com> wrote:
> Fix QINT count reset on NIX queue IRQs register and
> unregister.
> Queue interrupt will be cleared by individual queue
> interrupt operation register update.
>
> Fixes: f6d567b03d28 ("common/cnxk: support NIX IRQ")
> Fixes: 3c100e0e6b9c ("common/cnxk: support per-port RQ in inline device")
> Cc: stable@dpdk.org
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
More detailed AI review:
Patch 3/14 common/cnxk: fix NIX QINT count reset
------------------------------------------------
Warning: the inline dev path now clears QINTX_INT with ~0ull (W1C),
but roc_nix_register_queue_irqs() still does
plt_write64(0, nix->base + NIX_LF_QINTX_INT(q));
before ENA_W1S, and roc_nix_unregister_queue_irqs() does the same.
Writing 0 to a W1C register clears nothing, so a stale QINT is still
pending when the interrupt is enabled. Use ~0ull in both places.
Info: the roc_nix path uses "int64_t val; plt_write64(-val, ...)"
while the inl path casts explicitly. Pick one form.
next prev parent reply other threads:[~2026-09-17 16:19 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 7:10 [PATCH 01/14] net/cnxk: fix packet length handling Rahul Bhansali
2026-09-17 7:10 ` [PATCH 02/14] common/cnxk: disable CPT drop error in CQ Rahul Bhansali
2026-09-17 16:14 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 03/14] common/cnxk: fix NIX QINT count reset Rahul Bhansali
2026-09-17 16:14 ` Stephen Hemminger [this message]
2026-09-17 7:10 ` [PATCH 04/14] common/cnxk: update channel mask for cn20k Rahul Bhansali
2026-09-17 7:10 ` [PATCH 05/14] common/cnxk: update macro " Rahul Bhansali
2026-09-17 7:10 ` [PATCH 06/14] common/cnxk: fix null deref and irq ack in CPT CQ handler Rahul Bhansali
2026-09-17 16:15 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 07/14] common/cnxk: derive mbuf from CPT CQ in inline IRQ path Rahul Bhansali
2026-09-17 16:15 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 08/14] net/cnxk: resolve mbuf from CPT CQ format in SSO work cb Rahul Bhansali
2026-09-17 16:16 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 09/14] common/cnxk: update bpid config for cn20k Rahul Bhansali
2026-09-17 16:16 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 10/14] net/cnxk: add MSNS inb SA and CN20K CPT result struct Rahul Bhansali
2026-09-17 16:16 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 11/14] common/cnxk: fix CPT CQ base address calculation Rahul Bhansali
2026-09-17 7:10 ` [PATCH 12/14] common/cnxk: update mode param for link speed Rahul Bhansali
2026-09-17 16:17 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 13/14] common/cnxk: support for cn20k legacy msns mode Rahul Bhansali
2026-09-17 16:18 ` Stephen Hemminger
2026-09-17 7:10 ` [PATCH 14/14] net/cnxk: fix custom inbound SA condition check Rahul Bhansali
2026-09-17 16:12 ` [PATCH 01/14] net/cnxk: fix packet length handling Stephen Hemminger
2026-09-17 16:29 ` Stephen Hemminger
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