[igt-dev] [PATCH i-g-t v3] lib/igt_draw: Change MOCS settings for MTL

[igt-dev] [PATCH i-g-t v3] lib/igt_draw: Change MOCS settings for MTL

[Jeevan B]

On MTL, we want the table entry labelled "UC (GO:Mem)"
which has index 5.  This means that the MOCS value is 10.

v2: Add define for MOCS settings. (Lucas)

Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/igt_draw.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 975d65cd..e9b427f7 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -651,13 +651,16 @@ static struct intel_buf *create_buf(int fd, struct buf_ops *bops,
 	return buf;
 }
 
+#define DG2_MOCS_UC_GO_MEM	2	/* MOCS index 0x1 */
+#define MTL_MOCS_UC_GO_MEM	10	/* MOCS index 0x5 */
+
 static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 			  struct buf_data *buf, struct rect *rect,
 			  uint32_t tiling, uint32_t color)
 {
 	struct intel_bb *ibb;
 	struct intel_buf *dst;
-	int blt_cmd_len, blt_cmd_tiling, blt_cmd_depth;
+	int blt_cmd_len, blt_cmd_tiling, blt_cmd_depth, mocs_val;
 	uint32_t devid = intel_get_drm_devid(fd);
 	int gen = intel_gen(devid);
 	int pitch;
@@ -699,11 +702,15 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 			igt_assert(false);
 		}
 
+		if (IS_METEORLAKE(intel_get_drm_devid(fd)))
+			mocs_val = MTL_MOCS_UC_GO_MEM;
+		else
+			mocs_val = DG2_MOCS_UC_GO_MEM;
+
 		pitch = tiling ? buf->stride / 4 : buf->stride;
 
 		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
-		/* DG2 MOCS entry 2 is "UC - Non-Coherent; GO:Memory" */
-		intel_bb_out(ibb, blt_cmd_tiling | 2 << 21 | (pitch-1));
+		intel_bb_out(ibb, blt_cmd_tiling | mocs_val << 21 | (pitch-1));
 		intel_bb_out(ibb, (rect->y << 16) | rect->x);
 		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
 		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0,
-- 
2.36.0

[igt-dev] [PATCH i-g-t v3] lib/igt_draw: Change MOCS settings for MTL

[Jeevan B]

On MTL, we want the table entry labelled "UC (GO:Mem)"
which has index 5.  This means that the MOCS value is 10.

v2: Add define for MOCS settings. (Lucas)
v3: Extending get_mocs_index and using get_mocs_index
    to get mocs val. (Zbigniew)

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/i915/intel_mocs.c | 6 +++++-
 lib/igt_draw.c        | 7 +++++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
index df541ab0..d2994480 100644
--- a/lib/i915/intel_mocs.c
+++ b/lib/i915/intel_mocs.c
@@ -11,6 +11,8 @@
 #define DG1_MOCS_WB_IDX				5
 #define DG2_MOCS_UC_IDX				1
 #define DG2_MOCS_WB_IDX				3
+#define MTL_MOCS_UC_IDX				5
+#define MTL_MOCS_WB_IDX				10
 #define GEN12_MOCS_UC_IDX			3
 #define GEN12_MOCS_WB_IDX			2
 #define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
@@ -38,7 +40,9 @@ static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
 	} else if (IS_DG2(devid)) {
 		mocs->uc_index = DG2_MOCS_UC_IDX;
 		mocs->wb_index = DG2_MOCS_WB_IDX;
-
+	} else if (IS_METEORLAKE(devid)) {
+		mocs->uc_index = MTL_MOCS_UC_IDX;
+		mocs->wb_index = MTL_MOCS_WB_IDX;
 	} else if (IS_GEN12(devid)) {
 		mocs->uc_index = GEN12_MOCS_UC_IDX;
 		mocs->wb_index = GEN12_MOCS_WB_IDX;
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 975d65cd..a2c79944 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -36,6 +36,7 @@
 #include "i830_reg.h"
 #include "i915/gem_create.h"
 #include "i915/gem_mman.h"
+#include "i915/intel_mocs.h"
 
 #ifndef PAGE_ALIGN
 #ifndef PAGE_SIZE
@@ -651,6 +652,9 @@ static struct intel_buf *create_buf(int fd, struct buf_ops *bops,
 	return buf;
 }
 
+#define DG2_MOCS_UC_GO_MEM	2	/* MOCS index 0x1 */
+#define MTL_MOCS_UC_GO_MEM	10	/* MOCS index 0x5 */
+
 static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 			  struct buf_data *buf, struct rect *rect,
 			  uint32_t tiling, uint32_t color)
@@ -702,8 +706,7 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 		pitch = tiling ? buf->stride / 4 : buf->stride;
 
 		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
-		/* DG2 MOCS entry 2 is "UC - Non-Coherent; GO:Memory" */
-		intel_bb_out(ibb, blt_cmd_tiling | 2 << 21 | (pitch-1));
+		intel_bb_out(ibb, blt_cmd_tiling | intel_get_wb_mocs(fd) << 21 | (pitch-1));
 		intel_bb_out(ibb, (rect->y << 16) | rect->x);
 		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
 		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0,
-- 
2.36.0

[igt-dev] [PATCH i-g-t v3] lib/igt_draw: Change MOCS settings for MTL

[Jeevan B]

On MTL, we want the table entry labelled "UC (GO:Mem)"
which has index 5.  This means that the MOCS value is 10.

v2: Add define for MOCS settings. (Lucas)
v3: Extending get_mocs_index and using get_mocs_index
    to get mocs val. (Zbigniew)

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/i915/intel_mocs.c | 6 +++++-
 lib/igt_draw.c        | 4 ++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
index df541ab0..d2994480 100644
--- a/lib/i915/intel_mocs.c
+++ b/lib/i915/intel_mocs.c
@@ -11,6 +11,8 @@
 #define DG1_MOCS_WB_IDX				5
 #define DG2_MOCS_UC_IDX				1
 #define DG2_MOCS_WB_IDX				3
+#define MTL_MOCS_UC_IDX				5
+#define MTL_MOCS_WB_IDX				10
 #define GEN12_MOCS_UC_IDX			3
 #define GEN12_MOCS_WB_IDX			2
 #define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
@@ -38,7 +40,9 @@ static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
 	} else if (IS_DG2(devid)) {
 		mocs->uc_index = DG2_MOCS_UC_IDX;
 		mocs->wb_index = DG2_MOCS_WB_IDX;
-
+	} else if (IS_METEORLAKE(devid)) {
+		mocs->uc_index = MTL_MOCS_UC_IDX;
+		mocs->wb_index = MTL_MOCS_WB_IDX;
 	} else if (IS_GEN12(devid)) {
 		mocs->uc_index = GEN12_MOCS_UC_IDX;
 		mocs->wb_index = GEN12_MOCS_WB_IDX;
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 975d65cd..b02ad2a8 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -36,6 +36,7 @@
 #include "i830_reg.h"
 #include "i915/gem_create.h"
 #include "i915/gem_mman.h"
+#include "i915/intel_mocs.h"
 
 #ifndef PAGE_ALIGN
 #ifndef PAGE_SIZE
@@ -702,8 +703,7 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 		pitch = tiling ? buf->stride / 4 : buf->stride;
 
 		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
-		/* DG2 MOCS entry 2 is "UC - Non-Coherent; GO:Memory" */
-		intel_bb_out(ibb, blt_cmd_tiling | 2 << 21 | (pitch-1));
+		intel_bb_out(ibb, blt_cmd_tiling | intel_get_wb_mocs(fd) << 21 | (pitch-1));
 		intel_bb_out(ibb, (rect->y << 16) | rect->x);
 		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
 		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0,
-- 
2.36.0

[igt-dev] ✗ Fi.CI.BAT: failure for lib/igt_draw: Change MOCS settings for MTL (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5501 bytes --]

== Series Details ==

Series: lib/igt_draw: Change MOCS settings for MTL (rev6)
URL   : https://patchwork.freedesktop.org/series/111958/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7102 -> IGTPW_8262
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_8262 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_8262, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/index.html

Participating hosts (44 -> 43)
------------------------------

  Additional (1): fi-ilk-650 
  Missing    (2): fi-skl-6700k2 fi-pnv-d510 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8262:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_lrc:
    - fi-rkl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_frontbuffer_tracking@basic:
    - {bat-dg2-11}:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/bat-dg2-11/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/bat-dg2-11/igt@kms_frontbuffer_tracking@basic.html
    - {bat-dg2-9}:        [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/bat-dg2-9/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/bat-dg2-9/igt@kms_frontbuffer_tracking@basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_8262 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-ilk-650:         NOTRUN -> [SKIP][7] ([fdo#109271]) +20 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-ilk-650/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-soraka:      [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [PASS][10] -> [DMESG-FAIL][11] ([i915#5334])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       [PASS][12] -> [INCOMPLETE][13] ([i915#4817])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-ilk-650:         NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-kefka:       [PASS][15] -> [FAIL][16] ([i915#6298])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7102/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7554]: https://gitlab.freedesktop.org/drm/intel/issues/7554


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7102 -> IGTPW_8262

  CI-20190529: 20190529
  CI_DRM_12521: 584eb294ab7b1273c5ef505a33f2a5d89c877fcd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8262: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/index.html
  IGT_7102: bacfdc84a9c02556c5441deb21e3a3f18a07347d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8262/index.html

[-- Attachment #2: Type: text/html, Size: 6078 bytes --]

Re: [igt-dev] [PATCH i-g-t v3] lib/igt_draw: Change MOCS settings for MTL

[Lucas De Marchi]

On Thu, Dec 22, 2022 at 03:08:21PM +0530, Jeevan B wrote:
>On MTL, we want the table entry labelled "UC (GO:Mem)"
>which has index 5.  This means that the MOCS value is 10.
>
>v2: Add define for MOCS settings. (Lucas)
>v3: Extending get_mocs_index and using get_mocs_index
>    to get mocs val. (Zbigniew)
>
>Signed-off-by: Jeevan B <jeevan.b@intel.com>
>---
> lib/i915/intel_mocs.c | 6 +++++-
> lib/igt_draw.c        | 4 ++--
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
>diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
>index df541ab0..d2994480 100644
>--- a/lib/i915/intel_mocs.c
>+++ b/lib/i915/intel_mocs.c
>@@ -11,6 +11,8 @@
> #define DG1_MOCS_WB_IDX				5
> #define DG2_MOCS_UC_IDX				1
> #define DG2_MOCS_WB_IDX				3
>+#define MTL_MOCS_UC_IDX				5
>+#define MTL_MOCS_WB_IDX				10
> #define GEN12_MOCS_UC_IDX			3
> #define GEN12_MOCS_WB_IDX			2
> #define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
>@@ -38,7 +40,9 @@ static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> 	} else if (IS_DG2(devid)) {
> 		mocs->uc_index = DG2_MOCS_UC_IDX;
> 		mocs->wb_index = DG2_MOCS_WB_IDX;
>-
>+	} else if (IS_METEORLAKE(devid)) {
>+		mocs->uc_index = MTL_MOCS_UC_IDX;
>+		mocs->wb_index = MTL_MOCS_WB_IDX;

convention is latest platform first, so this needs to come above  DG2.

MTL
DG2
DG1
GEN12
..

> 	} else if (IS_GEN12(devid)) {
> 		mocs->uc_index = GEN12_MOCS_UC_IDX;
> 		mocs->wb_index = GEN12_MOCS_WB_IDX;
>diff --git a/lib/igt_draw.c b/lib/igt_draw.c
>index 975d65cd..b02ad2a8 100644
>--- a/lib/igt_draw.c
>+++ b/lib/igt_draw.c
>@@ -36,6 +36,7 @@
> #include "i830_reg.h"
> #include "i915/gem_create.h"
> #include "i915/gem_mman.h"
>+#include "i915/intel_mocs.h"
>
> #ifndef PAGE_ALIGN
> #ifndef PAGE_SIZE
>@@ -702,8 +703,7 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
> 		pitch = tiling ? buf->stride / 4 : buf->stride;
>
> 		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
>-		/* DG2 MOCS entry 2 is "UC - Non-Coherent; GO:Memory" */
>-		intel_bb_out(ibb, blt_cmd_tiling | 2 << 21 | (pitch-1));
>+		intel_bb_out(ibb, blt_cmd_tiling | intel_get_wb_mocs(fd) << 21 | (pitch-1));

weren't you supposed to use the intel_get_uc_mocs()?

Lucas De Marchi

> 		intel_bb_out(ibb, (rect->y << 16) | rect->x);
> 		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
> 		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0,
>-- 
>2.36.0
>