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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t 04/10] tools/intel_watermark: Read LP usage from FPGA_DBG on ivb
Date: Wed, 25 Jan 2023 06:55:16 +0200	[thread overview]
Message-ID: <20230125045522.18169-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230125045522.18169-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On ivb FPGA_DBG contains the similar LP level sticky bits that
are present in WM_DBG on hsw+. Let's dump these out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 863261e823a5..eac40e4a5d17 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -763,6 +763,22 @@ static void ilk_wm_dump(void)
 		printf("\n");
 		/* clear the sticky bits */
 		write_reg(0x45280, wm_dbg);
+	} else if (IS_IVYBRIDGE(devid)) {
+		uint32_t fpga_dbg;
+
+		fpga_dbg = read_reg(0x42300);
+		printf("FPGA_DBG: 0x%08x\n", fpga_dbg);
+		printf(" LP used:");
+		if (fpga_dbg & (1 << 18))
+			printf(" LP0.5");
+		for (i = 1; i < 4; i++) {
+			if (fpga_dbg & (1 << (18+i)))
+				printf(" LP%d", i);
+		}
+		printf("\n");
+		/* clear the sticky LP bits */
+		fpga_dbg &= 1 << 21 | 1 << 20 | 1 << 19 | 1 << 18;
+		write_reg(0x42300, fpga_dbg);
 	}
 
 	intel_register_access_fini(&mmio_data);
-- 
2.39.1

  parent reply	other threads:[~2023-01-25  4:55 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25  4:55 [igt-dev] [PATCH i-g-t 01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Ville Syrjala
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 02/10] tools/intel_watermark: Don't do intel_register_access_fini() too early on hsw/bdw Ville Syrjala
2023-02-06  8:14   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 03/10] tools/intel_watermark: Add missing newline Ville Syrjala
2023-02-06  8:15   ` Govindapillai, Vinod
2023-01-25  4:55 ` Ville Syrjala [this message]
2023-02-06 11:43   ` [igt-dev] [PATCH i-g-t 04/10] tools/intel_watermark: Read LP usage from FPGA_DBG on ivb Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 05/10] tools/intel_watermark: Extract is_cursor() Ville Syrjala
2023-02-06  8:37   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 06/10] tools/intel_watermark: Decode plane enable bits for ilk-bdw Ville Syrjala
2023-02-06  8:53   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 07/10] tools/intel_watermark: Dump all ARB_CTL registers on skl+ Ville Syrjala
2023-02-06 11:26   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 08/10] tools/intel_watermark: Use intel_display_ver() Ville Syrjala
2023-02-06 11:30   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 09/10] tools/intel_watermark: Introduce skl_has_nv12_buf_cfg() Ville Syrjala
2023-02-06 11:32   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 10/10] tools/intel_watermark: Decode SAGV WM usage correctly on ADL+ Ville Syrjala
2023-02-06 11:40   ` Govindapillai, Vinod
2023-01-25  6:02 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Patchwork
2023-01-25 12:27 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-02-06  8:12 ` [igt-dev] [PATCH i-g-t 01/10] " Govindapillai, Vinod

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