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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t 07/10] tools/intel_watermark: Dump all ARB_CTL registers on skl+
Date: Wed, 25 Jan 2023 06:55:19 +0200	[thread overview]
Message-ID: <20230125045522.18169-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230125045522.18169-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Dump the ARB_CTL registers on all skl+ platforms as well,
and decode the "FBC watermark disable" and "IPC enable"
bits from therein. Those at least are relevant for the
watermark state.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 66e76e0dd3ef..7e957f0c8e9a 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -321,10 +321,13 @@ static void skl_wm_dump(void)
 	uint32_t nv12_buf_cfg[num_pipes][max_planes];
 	uint32_t plane_ctl[num_pipes][max_planes];
 	uint32_t wm_linetime[num_pipes];
-	uint32_t wm_dbg;
+	uint32_t arb_ctl, arb_ctl2, wm_dbg;
 
 	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
+	arb_ctl = read_reg(0x45000);
+	arb_ctl2 = read_reg(0x45004);
+
 	for (pipe = 0; pipe < num_pipes; pipe++) {
 		int num_planes = skl_num_planes(devid, pipe);
 
@@ -453,6 +456,22 @@ static void skl_wm_dump(void)
 	}
 	printf("\n");
 
+	if (intel_gen(devid) >= 13) {
+		printf(" ARB_LP_CTL 0x%08x\n", arb_ctl);
+		printf(" ARB_HP_CTL 0x%08x\n", arb_ctl2);
+	} else if (intel_gen(devid) >= 12) {
+		printf("        ARB_CTL 0x%08x\n", arb_ctl);
+		printf("  ARB_CTL_ABOX1 0x%08x\n", read_reg(0x45800));
+		printf("  ARB_CTL_ABOX2 0x%08x\n", read_reg(0x45808));
+		printf("       ARB_CTL2 0x%08x\n", arb_ctl2);
+		printf(" ARB_CTL2_ABOX1 0x%08x\n", read_reg(0x45804));
+		printf(" ARB_CTL2_ABOX2 0x%08x\n", read_reg(0x4580c));
+	} else {
+		printf("  ARB_CTL 0x%08x\n", arb_ctl);
+		printf(" ARB_CTL2 0x%08x\n", arb_ctl2);
+	}
+	printf("\n");
+
 	for (pipe = 0; pipe < num_pipes; pipe++) {
 		uint32_t start, end, size;
 		uint32_t lines, blocks, enable;
@@ -583,6 +602,12 @@ static void skl_wm_dump(void)
 		printf("\n\n\n");
 	}
 
+	if (intel_gen(devid) < 13)
+		printf("FBC watermark: %s\n", endis(!REG_DECODE1(arb_ctl, 15, 1)));
+	printf("IPC: %s\n", endis(REG_DECODE1(arb_ctl2, 3, 1)));
+
+	printf("\n");
+
 	printf("* plane watermark enabled\n");
 	printf("(x) line watermark if enabled\n");
 
-- 
2.39.1

  parent reply	other threads:[~2023-01-25  4:55 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25  4:55 [igt-dev] [PATCH i-g-t 01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Ville Syrjala
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 02/10] tools/intel_watermark: Don't do intel_register_access_fini() too early on hsw/bdw Ville Syrjala
2023-02-06  8:14   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 03/10] tools/intel_watermark: Add missing newline Ville Syrjala
2023-02-06  8:15   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 04/10] tools/intel_watermark: Read LP usage from FPGA_DBG on ivb Ville Syrjala
2023-02-06 11:43   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 05/10] tools/intel_watermark: Extract is_cursor() Ville Syrjala
2023-02-06  8:37   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 06/10] tools/intel_watermark: Decode plane enable bits for ilk-bdw Ville Syrjala
2023-02-06  8:53   ` Govindapillai, Vinod
2023-01-25  4:55 ` Ville Syrjala [this message]
2023-02-06 11:26   ` [igt-dev] [PATCH i-g-t 07/10] tools/intel_watermark: Dump all ARB_CTL registers on skl+ Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 08/10] tools/intel_watermark: Use intel_display_ver() Ville Syrjala
2023-02-06 11:30   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 09/10] tools/intel_watermark: Introduce skl_has_nv12_buf_cfg() Ville Syrjala
2023-02-06 11:32   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 10/10] tools/intel_watermark: Decode SAGV WM usage correctly on ADL+ Ville Syrjala
2023-02-06 11:40   ` Govindapillai, Vinod
2023-01-25  6:02 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Patchwork
2023-01-25 12:27 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-02-06  8:12 ` [igt-dev] [PATCH i-g-t 01/10] " Govindapillai, Vinod

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