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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t 02/10] tools/intel_watermark: Don't do intel_register_access_fini() too early on hsw/bdw
Date: Wed, 25 Jan 2023 06:55:14 +0200	[thread overview]
Message-ID: <20230125045522.18169-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230125045522.18169-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The tool will segfault if we try to the WM_DBG read/write after
intel_register_access_fini(). So move intel_register_access_fini()
to the very end.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 1818d79d0bee..d61379c6dc7f 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -644,8 +644,6 @@ static void ilk_wm_dump(void)
 	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
 		wm_misc = read_reg(0x45260);
 
-	intel_register_access_fini(&mmio_data);
-
 	for (i = 0; i < num_pipes; i++)
 		printf("    WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]);
 	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
@@ -765,6 +763,8 @@ static void ilk_wm_dump(void)
 		/* clear the sticky bits */
 		write_reg(0x45280, wm_dbg);
 	}
+
+	intel_register_access_fini(&mmio_data);
 }
 
 static void vlv_wm_dump(void)
-- 
2.39.1

  reply	other threads:[~2023-01-25  4:55 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25  4:55 [igt-dev] [PATCH i-g-t 01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Ville Syrjala
2023-01-25  4:55 ` Ville Syrjala [this message]
2023-02-06  8:14   ` [igt-dev] [PATCH i-g-t 02/10] tools/intel_watermark: Don't do intel_register_access_fini() too early on hsw/bdw Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 03/10] tools/intel_watermark: Add missing newline Ville Syrjala
2023-02-06  8:15   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 04/10] tools/intel_watermark: Read LP usage from FPGA_DBG on ivb Ville Syrjala
2023-02-06 11:43   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 05/10] tools/intel_watermark: Extract is_cursor() Ville Syrjala
2023-02-06  8:37   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 06/10] tools/intel_watermark: Decode plane enable bits for ilk-bdw Ville Syrjala
2023-02-06  8:53   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 07/10] tools/intel_watermark: Dump all ARB_CTL registers on skl+ Ville Syrjala
2023-02-06 11:26   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 08/10] tools/intel_watermark: Use intel_display_ver() Ville Syrjala
2023-02-06 11:30   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 09/10] tools/intel_watermark: Introduce skl_has_nv12_buf_cfg() Ville Syrjala
2023-02-06 11:32   ` Govindapillai, Vinod
2023-01-25  4:55 ` [igt-dev] [PATCH i-g-t 10/10] tools/intel_watermark: Decode SAGV WM usage correctly on ADL+ Ville Syrjala
2023-02-06 11:40   ` Govindapillai, Vinod
2023-01-25  6:02 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Patchwork
2023-01-25 12:27 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-02-06  8:12 ` [igt-dev] [PATCH i-g-t 01/10] " Govindapillai, Vinod

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