From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t 09/10] tools/intel_watermark: Introduce skl_has_nv12_buf_cfg()
Date: Wed, 25 Jan 2023 06:55:21 +0200 [thread overview]
Message-ID: <20230125045522.18169-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230125045522.18169-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace the hand rolled display_ver>=11 checks with
a more descriptive helper.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 7991e80ac876..e598cf122159 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -179,6 +179,11 @@ static bool skl_has_sagv_wm(uint32_t d)
return intel_display_ver(d) >= 13;
}
+static bool skl_has_nv12_buf_cfg(uint32_t d)
+{
+ return intel_display_ver(d) < 11;
+}
+
static int skl_num_wm_levels(uint32_t d)
{
if (skl_has_sagv_wm(d))
@@ -339,7 +344,7 @@ static void skl_wm_dump(void)
plane_ctl[pipe][plane] = read_reg(addr + 0x80);
wm_trans[pipe][plane] = read_reg(addr + 0x00168);
buf_cfg[pipe][plane] = read_reg(addr + 0x0017C);
- if (!is_cursor(plane) && intel_display_ver(devid) < 11)
+ if (!is_cursor(plane) && skl_has_nv12_buf_cfg(devid))
nv12_buf_cfg[pipe][plane] = read_reg(addr + 0x00178);
else
nv12_buf_cfg[pipe][plane] = 0;
@@ -439,7 +444,7 @@ static void skl_wm_dump(void)
}
printf("\n");
- if (intel_display_ver(devid) >= 11)
+ if (!skl_has_nv12_buf_cfg(devid))
continue;
if (is_cursor(plane))
@@ -575,7 +580,7 @@ static void skl_wm_dump(void)
}
printf("\n");
- if (intel_display_ver(devid) < 11) {
+ if (skl_has_nv12_buf_cfg(devid)) {
printf("\nNV12 DDB allocation:");
printf("\nstart");
--
2.39.1
next prev parent reply other threads:[~2023-01-25 4:55 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 4:55 [igt-dev] [PATCH i-g-t 01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Ville Syrjala
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 02/10] tools/intel_watermark: Don't do intel_register_access_fini() too early on hsw/bdw Ville Syrjala
2023-02-06 8:14 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 03/10] tools/intel_watermark: Add missing newline Ville Syrjala
2023-02-06 8:15 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 04/10] tools/intel_watermark: Read LP usage from FPGA_DBG on ivb Ville Syrjala
2023-02-06 11:43 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 05/10] tools/intel_watermark: Extract is_cursor() Ville Syrjala
2023-02-06 8:37 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 06/10] tools/intel_watermark: Decode plane enable bits for ilk-bdw Ville Syrjala
2023-02-06 8:53 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 07/10] tools/intel_watermark: Dump all ARB_CTL registers on skl+ Ville Syrjala
2023-02-06 11:26 ` Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 08/10] tools/intel_watermark: Use intel_display_ver() Ville Syrjala
2023-02-06 11:30 ` Govindapillai, Vinod
2023-01-25 4:55 ` Ville Syrjala [this message]
2023-02-06 11:32 ` [igt-dev] [PATCH i-g-t 09/10] tools/intel_watermark: Introduce skl_has_nv12_buf_cfg() Govindapillai, Vinod
2023-01-25 4:55 ` [igt-dev] [PATCH i-g-t 10/10] tools/intel_watermark: Decode SAGV WM usage correctly on ADL+ Ville Syrjala
2023-02-06 11:40 ` Govindapillai, Vinod
2023-01-25 6:02 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/10] tools/intel_watermark: Add missing intel_register_access_fini() for skl+ Patchwork
2023-01-25 12:27 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-02-06 8:12 ` [igt-dev] [PATCH i-g-t 01/10] " Govindapillai, Vinod
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