[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 +++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  96 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 326 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/igt_dummyload.c | 38 +++++++++++++++---
 lib/igt_dummyload.h | 11 ++++++
 lib/xe/xe_spin.c    | 96 +++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_spin.h    |  6 ++-
 4 files changed, 145 insertions(+), 6 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 740a58f3..60c4f679 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -46,6 +46,7 @@
 #include "intel_reg.h"
 #include "ioctl_wrappers.h"
 #include "sw_sync.h"
+#include "xe/xe_spin.h"
 
 /**
  * SECTION:igt_dummyload
@@ -447,7 +448,18 @@ spin_create(int fd, const struct igt_spin_factory *opts)
 igt_spin_t *
 __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 {
-	return spin_create(fd, opts);
+	if (is_xe_device(fd)) {
+		igt_spin_t *spin;
+
+		spin = xe_spin_create(fd, opts);
+
+		pthread_mutex_lock(&list_lock);
+		igt_list_add(&spin->link, &spin_list);
+		pthread_mutex_unlock(&list_lock);
+
+		return spin;
+	} else
+		return spin_create(fd, opts);
 }
 
 /**
@@ -467,6 +479,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 {
 	igt_spin_t *spin;
 
+	if (is_xe_device(fd)) {
+		spin = xe_spin_create(fd, opts);
+
+		pthread_mutex_lock(&list_lock);
+		igt_list_add(&spin->link, &spin_list);
+		pthread_mutex_unlock(&list_lock);
+
+		return spin;
+	}
+
 	if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
 		unsigned int class;
 
@@ -597,8 +619,12 @@ void igt_spin_end(igt_spin_t *spin)
 	if (!spin)
 		return;
 
-	igt_gettime(&spin->last_signal);
-	sync_write(spin, MI_BATCH_BUFFER_END);
+	if ((spin->driver = DRIVER_XE)) {
+		xe_spin_end(spin->xe_spin);
+	} else {
+		igt_gettime(&spin->last_signal);
+		sync_write(spin, MI_BATCH_BUFFER_END);
+	}
 }
 
 static void __igt_spin_free(int fd, igt_spin_t *spin)
@@ -646,12 +672,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
 {
 	if (!spin)
 		return;
-
 	pthread_mutex_lock(&list_lock);
 	igt_list_del(&spin->link);
 	pthread_mutex_unlock(&list_lock);
 
-	__igt_spin_free(fd, spin);
+	if (is_xe_device(fd))
+		xe_spin_free(fd, spin);
+	else
+		__igt_spin_free(fd, spin);
 }
 
 void igt_terminate_spins(void)
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index b247ab02..ebed19bb 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -54,6 +54,8 @@ typedef struct igt_spin_factory {
 	unsigned int flags;
 	int fence;
 	uint64_t ahnd;
+	struct drm_xe_engine_class_instance *hwe;
+	uint32_t vm;
 } igt_spin_factory_t;
 
 typedef struct igt_spin {
@@ -83,6 +85,15 @@ typedef struct igt_spin {
 #define SPIN_CLFLUSH (1 << 0)
 
 	struct igt_spin_factory opts;
+
+	struct xe_spin *xe_spin;
+	int driver;
+	size_t bo_size;
+	uint64_t address;
+	unsigned int engine;
+	uint32_t vm;
+	uint32_t syncobj;
+
 } igt_spin_t;
 
 
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 856d0ba2..b375463a 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -82,6 +82,102 @@ void xe_spin_end(struct xe_spin *spin)
 	spin->end = 0;
 }
 
+/**
+ * xe_spin_create:
+ *@opt: controlling options such as allocator handle, engine, vmetc
+ *
+ * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
+ * which wraps around vm bind and unbinding the object associated to it.
+ * This returs a spinner after submitting a dummy load.
+ *
+ */
+igt_spin_t *
+xe_spin_create(int fd, const struct igt_spin_factory *opt)
+{
+	size_t bo_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = opt->ahnd, addr;
+	struct igt_spin *spin;
+	struct xe_spin *xe_spin;
+	struct drm_xe_sync sync = {
+		.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+
+	igt_assert(ahnd);
+	spin = calloc(1, sizeof(struct igt_spin));
+	igt_assert(spin);
+
+	spin->driver = DRIVER_XE;
+	spin->syncobj = syncobj_create(fd, 0);
+	spin->vm = opt->vm;
+	spin->engine = opt->engine;
+
+	if (!spin->vm)
+		spin->vm = xe_vm_create(fd, 0, 0);
+
+	if (!spin->engine) {
+		if (opt->hwe)
+			spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
+		else
+			spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
+	}
+
+	spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
+	xe_spin = xe_bo_map(fd, spin->handle, bo_size);
+	addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
+	xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
+
+	xe_spin_init(xe_spin, addr, true);
+	exec.engine_id = spin->engine;
+	exec.address = addr;
+	sync.handle = spin->syncobj;
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+	xe_spin_wait_started(xe_spin);
+
+	spin->bo_size = bo_size;
+	spin->address = addr;
+	spin->xe_spin = xe_spin;
+	spin->opts = *opt;
+
+	return spin;
+}
+
+void xe_spin_sync_wait(int fd, struct igt_spin *spin)
+{
+	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
+}
+
+/*
+ * xe_spin_free:
+ *@spin: spin state from igt_spin_new()
+ *
+ * Wrapper to free spinner whhich is triggered by xe_spin_create.
+ * which distroys vm, engine and unbinds the vm which is binded to
+ * the engine and bo.
+ *
+ */
+void xe_spin_free(int fd, struct igt_spin *spin)
+{
+	xe_spin_end(spin->xe_spin);
+	xe_spin_sync_wait(fd, spin);
+	xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
+	syncobj_destroy(fd, spin->syncobj);
+	gem_munmap(spin->xe_spin, spin->bo_size);
+	gem_close(fd, spin->handle);
+
+	if (!spin->opts.engine)
+		xe_engine_destroy(fd, spin->engine);
+
+	if (!spin->opts.vm)
+		xe_vm_destroy(fd, spin->vm);
+
+	free(spin);
+}
+
 void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
 		  struct xe_cork *cork)
 {
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 73f9a026..60f6e751 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -13,6 +13,7 @@
 #include <stdbool.h>
 
 #include "xe_query.h"
+#include "lib/igt_dummyload.h"
 
 /* Mapped GPU object */
 struct xe_spin {
@@ -21,11 +22,14 @@ struct xe_spin {
 	uint32_t start;
 	uint32_t end;
 };
-
+void xe_spin_user_vm_engine(int fd, const struct igt_spin_factory *opt, struct igt_spin *spin);
+igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
 void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
 bool xe_spin_started(struct xe_spin *spin);
+void xe_spin_sync_wait(int fd, struct igt_spin *spin);
 void xe_spin_wait_started(struct xe_spin *spin);
 void xe_spin_end(struct xe_spin *spin);
+void xe_spin_free(int fd, struct igt_spin *spin);
 
 struct xe_cork {
 	struct xe_spin *spin;
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe

[Zbigniew Kempczyński]

On Mon, Jun 12, 2023 at 02:29:47PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Extending the spin_create implementation and allocator handle support in xe,
> where it submits dummy work loads to engine. This Implementation is wrapped
> around vm_bind and unbind as we are supposed to do it manually for xe.
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  lib/igt_dummyload.c | 38 +++++++++++++++---
>  lib/igt_dummyload.h | 11 ++++++
>  lib/xe/xe_spin.c    | 96 +++++++++++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_spin.h    |  6 ++-
>  4 files changed, 145 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 740a58f3..60c4f679 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -46,6 +46,7 @@
>  #include "intel_reg.h"
>  #include "ioctl_wrappers.h"
>  #include "sw_sync.h"
> +#include "xe/xe_spin.h"
>  
>  /**
>   * SECTION:igt_dummyload
> @@ -447,7 +448,18 @@ spin_create(int fd, const struct igt_spin_factory *opts)
>  igt_spin_t *
>  __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
>  {
> -	return spin_create(fd, opts);
> +	if (is_xe_device(fd)) {
> +		igt_spin_t *spin;
> +
> +		spin = xe_spin_create(fd, opts);
> +
> +		pthread_mutex_lock(&list_lock);
> +		igt_list_add(&spin->link, &spin_list);
> +		pthread_mutex_unlock(&list_lock);
> +
> +		return spin;
> +	} else
> +		return spin_create(fd, opts);
>  }
>  
>  /**
> @@ -467,6 +479,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
>  {
>  	igt_spin_t *spin;
>  
> +	if (is_xe_device(fd)) {
> +		spin = xe_spin_create(fd, opts);
> +
> +		pthread_mutex_lock(&list_lock);
> +		igt_list_add(&spin->link, &spin_list);
> +		pthread_mutex_unlock(&list_lock);
> +
> +		return spin;
> +	}
> +
>  	if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
>  		unsigned int class;
>  
> @@ -597,8 +619,12 @@ void igt_spin_end(igt_spin_t *spin)
>  	if (!spin)
>  		return;
>  
> -	igt_gettime(&spin->last_signal);
> -	sync_write(spin, MI_BATCH_BUFFER_END);
> +	if ((spin->driver = DRIVER_XE)) {

Uaa, this hurts!

--
Zbigniew

> +		xe_spin_end(spin->xe_spin);
> +	} else {
> +		igt_gettime(&spin->last_signal);
> +		sync_write(spin, MI_BATCH_BUFFER_END);
> +	}
>  }
>  
>  static void __igt_spin_free(int fd, igt_spin_t *spin)
> @@ -646,12 +672,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
>  {
>  	if (!spin)
>  		return;
> -
>  	pthread_mutex_lock(&list_lock);
>  	igt_list_del(&spin->link);
>  	pthread_mutex_unlock(&list_lock);
>  
> -	__igt_spin_free(fd, spin);
> +	if (is_xe_device(fd))
> +		xe_spin_free(fd, spin);
> +	else
> +		__igt_spin_free(fd, spin);
>  }
>  
>  void igt_terminate_spins(void)
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index b247ab02..ebed19bb 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -54,6 +54,8 @@ typedef struct igt_spin_factory {
>  	unsigned int flags;
>  	int fence;
>  	uint64_t ahnd;
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint32_t vm;
>  } igt_spin_factory_t;
>  
>  typedef struct igt_spin {
> @@ -83,6 +85,15 @@ typedef struct igt_spin {
>  #define SPIN_CLFLUSH (1 << 0)
>  
>  	struct igt_spin_factory opts;
> +
> +	struct xe_spin *xe_spin;
> +	int driver;
> +	size_t bo_size;
> +	uint64_t address;
> +	unsigned int engine;
> +	uint32_t vm;
> +	uint32_t syncobj;
> +
>  } igt_spin_t;
>  
>  
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..b375463a 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -82,6 +82,102 @@ void xe_spin_end(struct xe_spin *spin)
>  	spin->end = 0;
>  }
>  
> +/**
> + * xe_spin_create:
> + *@opt: controlling options such as allocator handle, engine, vmetc
> + *
> + * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
> + * which wraps around vm bind and unbinding the object associated to it.
> + * This returs a spinner after submitting a dummy load.
> + *
> + */
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt)
> +{
> +	size_t bo_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = opt->ahnd, addr;
> +	struct igt_spin *spin;
> +	struct xe_spin *xe_spin;
> +	struct drm_xe_sync sync = {
> +		.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +
> +	igt_assert(ahnd);
> +	spin = calloc(1, sizeof(struct igt_spin));
> +	igt_assert(spin);
> +
> +	spin->driver = DRIVER_XE;
> +	spin->syncobj = syncobj_create(fd, 0);
> +	spin->vm = opt->vm;
> +	spin->engine = opt->engine;
> +
> +	if (!spin->vm)
> +		spin->vm = xe_vm_create(fd, 0, 0);
> +
> +	if (!spin->engine) {
> +		if (opt->hwe)
> +			spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> +		else
> +			spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
> +	}
> +
> +	spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
> +	xe_spin = xe_bo_map(fd, spin->handle, bo_size);
> +	addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> +	xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> +
> +	xe_spin_init(xe_spin, addr, true);
> +	exec.engine_id = spin->engine;
> +	exec.address = addr;
> +	sync.handle = spin->syncobj;
> +	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> +	xe_spin_wait_started(xe_spin);
> +
> +	spin->bo_size = bo_size;
> +	spin->address = addr;
> +	spin->xe_spin = xe_spin;
> +	spin->opts = *opt;
> +
> +	return spin;
> +}
> +
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +{
> +	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
> +}
> +
> +/*
> + * xe_spin_free:
> + *@spin: spin state from igt_spin_new()
> + *
> + * Wrapper to free spinner whhich is triggered by xe_spin_create.
> + * which distroys vm, engine and unbinds the vm which is binded to
> + * the engine and bo.
> + *
> + */
> +void xe_spin_free(int fd, struct igt_spin *spin)
> +{
> +	xe_spin_end(spin->xe_spin);
> +	xe_spin_sync_wait(fd, spin);
> +	xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> +	syncobj_destroy(fd, spin->syncobj);
> +	gem_munmap(spin->xe_spin, spin->bo_size);
> +	gem_close(fd, spin->handle);
> +
> +	if (!spin->opts.engine)
> +		xe_engine_destroy(fd, spin->engine);
> +
> +	if (!spin->opts.vm)
> +		xe_vm_destroy(fd, spin->vm);
> +
> +	free(spin);
> +}
> +
>  void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>  		  struct xe_cork *cork)
>  {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 73f9a026..60f6e751 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -13,6 +13,7 @@
>  #include <stdbool.h>
>  
>  #include "xe_query.h"
> +#include "lib/igt_dummyload.h"
>  
>  /* Mapped GPU object */
>  struct xe_spin {
> @@ -21,11 +22,14 @@ struct xe_spin {
>  	uint32_t start;
>  	uint32_t end;
>  };
> -
> +void xe_spin_user_vm_engine(int fd, const struct igt_spin_factory *opt, struct igt_spin *spin);
> +igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
>  void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
>  bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>  void xe_spin_wait_started(struct xe_spin *spin);
>  void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_free(int fd, struct igt_spin *spin);
>  
>  struct xe_cork {
>  	struct xe_spin *spin;
> -- 
> 2.39.1
> 

[igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

xe_spin_batch test exercises igt_spin_new submissions with different
combination.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 181 insertions(+)
 create mode 100644 tests/xe/xe_spin_batch.c

diff --git a/tests/meson.build b/tests/meson.build
index f908ae88..454b0060 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
 	'xe_query',
 	'xe_vm',
 	'xe_waitfence',
+	'xe_spin_batch',
 ]
 
 msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..6ce7e741
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,180 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+	uint64_t ahnd;
+	igt_spin_t *spin;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+	spin = __igt_spin_new(fd, .ahnd = ahnd);
+	igt_assert(spin);
+
+	igt_spin_free(fd, spin);
+	put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+	uint64_t ahnd;
+	unsigned int engine;
+	uint32_t vm;
+	igt_spin_t *spin;
+
+	vm = xe_vm_create(fd, 0, 0);
+	engine = xe_engine_create(fd, vm, hwe, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+	igt_assert(spin);
+
+	igt_spin_free(fd, spin);
+	xe_engine_destroy(fd, engine);
+	xe_vm_destroy(fd, vm);
+
+	put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	uint64_t ahnd;
+	uint32_t vm;
+	igt_spin_t **spin;
+	int i = 0;
+
+	vm = xe_vm_create(fd, 0, 0);
+	ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+	spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+	xe_for_each_hw_engine(fd, hwe) {
+		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+		igt_assert(spin[i]);
+		i++;
+	}
+
+	while (--i>=0)
+		igt_spin_free(fd, spin[i]);
+
+	put_ahnd(ahnd);
+	xe_vm_destroy(fd, vm);
+	free(spin);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all(int fd, int gt, int class)
+{
+	uint64_t ahnd;
+	uint32_t engines[MAX_INSTANCE], vm;
+	int i, num_placements = 0;
+	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+	igt_spin_t *spin[MAX_INSTANCE];
+	struct drm_xe_engine_class_instance *hwe;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	xe_for_each_hw_engine(fd, hwe) {
+		if (hwe->engine_class != class || hwe->gt_id != gt)
+			continue;
+		eci[num_placements++] = *hwe;
+	}
+	if (num_placements < 2)
+		return;
+	vm = xe_vm_create(fd, 0, 0);
+
+	for (i = 0; i < num_placements; i++) {
+		struct drm_xe_engine_create create;
+
+		create.vm_id = vm;
+		create.width = 1;
+		create.num_placements = num_placements;
+		create.instances = to_user_pointer(eci);
+
+		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+					&create), 0);
+		engines[i] = create.engine_id;
+		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
+	}
+
+	for (i = 0; i < num_placements; i++) {
+		igt_assert(spin[i]);
+		igt_spin_free(fd, spin[i]);
+	}
+
+	put_ahnd(ahnd);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	struct drm_xe_engine_class_instance *hwe;
+	int fd;
+	int gt, class;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		xe_device_get(fd);
+	}
+
+	igt_subtest("spin-basic")
+		spin_basic(fd);
+
+	igt_subtest("spin-batch")
+		xe_for_each_hw_engine(fd, hwe)
+			spin(fd, hwe);
+
+	igt_subtest("spin-basic-all")
+		spin_basic_all(fd);
+
+	igt_subtest("spin-all") {
+		xe_for_each_gt(fd, gt)
+			xe_for_each_hw_engine_class(class)
+				spin_all(fd, gt, class);
+	}
+
+	igt_fixture {
+		xe_device_put(fd);
+		close(fd);
+	}
+}
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

[Zbigniew Kempczyński]

On Mon, Jun 12, 2023 at 02:29:48PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/meson.build        |   1 +
>  tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 181 insertions(+)
>  create mode 100644 tests/xe/xe_spin_batch.c
> 
> diff --git a/tests/meson.build b/tests/meson.build
> index f908ae88..454b0060 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
>  	'xe_query',
>  	'xe_vm',
>  	'xe_waitfence',
> +	'xe_spin_batch',
>  ]
>  
>  msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..6ce7e741
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,180 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> +	uint64_t ahnd;
> +	igt_spin_t *spin;
> +
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +	spin = __igt_spin_new(fd, .ahnd = ahnd);
> +	igt_assert(spin);
> +
> +	igt_spin_free(fd, spin);
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> +	uint64_t ahnd;
> +	unsigned int engine;
> +	uint32_t vm;
> +	igt_spin_t *spin;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	engine = xe_engine_create(fd, vm, hwe, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> +	spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> +	igt_assert(spin);
> +
> +	igt_spin_free(fd, spin);
> +	xe_engine_destroy(fd, engine);
> +	xe_vm_destroy(fd, vm);
> +
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd)
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint64_t ahnd;
> +	uint32_t vm;
> +	igt_spin_t **spin;
> +	int i = 0;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
> +	spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
> +	xe_for_each_hw_engine(fd, hwe) {
> +		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
> +		igt_assert(spin[i]);
> +		i++;
> +	}
> +
> +	while (--i>=0)
> +		igt_spin_free(fd, spin[i]);
> +
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +	free(spin);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all(int fd, int gt, int class)
> +{
> +	uint64_t ahnd;
> +	uint32_t engines[MAX_INSTANCE], vm;
> +	int i, num_placements = 0;
> +	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> +	igt_spin_t *spin[MAX_INSTANCE];
> +	struct drm_xe_engine_class_instance *hwe;
> +
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> +	xe_for_each_hw_engine(fd, hwe) {
> +		if (hwe->engine_class != class || hwe->gt_id != gt)
> +			continue;
> +		eci[num_placements++] = *hwe;
> +	}
> +	if (num_placements < 2)
> +		return;
> +	vm = xe_vm_create(fd, 0, 0);
> +
> +	for (i = 0; i < num_placements; i++) {
> +		struct drm_xe_engine_create create;

This line is still buggy causing:

(xe_spin_batch:27808) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
(xe_spin_batch:27808) CRITICAL: Last errno: 22, Invalid argument

Hint: it's on the stack

--
Zbigniew

> +
> +		create.vm_id = vm;
> +		create.width = 1;
> +		create.num_placements = num_placements;
> +		create.instances = to_user_pointer(eci);
> +
> +		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> +					&create), 0);
> +		engines[i] = create.engine_id;
> +		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
> +	}
> +
> +	for (i = 0; i < num_placements; i++) {
> +		igt_assert(spin[i]);
> +		igt_spin_free(fd, spin[i]);
> +	}
> +
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	int fd;
> +	int gt, class;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		xe_device_get(fd);
> +	}
> +
> +	igt_subtest("spin-basic")
> +		spin_basic(fd);
> +
> +	igt_subtest("spin-batch")
> +		xe_for_each_hw_engine(fd, hwe)
> +			spin(fd, hwe);
> +
> +	igt_subtest("spin-basic-all")
> +		spin_basic_all(fd);
> +
> +	igt_subtest("spin-all") {
> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				spin_all(fd, gt, class);
> +	}
> +
> +	igt_fixture {
> +		xe_device_put(fd);
> +		close(fd);
> +	}
> +}
> -- 
> 2.39.1
> 

[igt-dev] ✗ Fi.CI.BAT: failure for Integrate igt_spin_new with Xe (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 27303 bytes --]

== Series Details ==

Series: Integrate igt_spin_new with Xe (rev4)
URL   : https://patchwork.freedesktop.org/series/118837/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7326 -> IGTPW_9147
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_9147 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_9147, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/index.html

Participating hosts (41 -> 40)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_9147:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_busy@busy@all-engines:
    - fi-hsw-4770:        [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-hsw-4770/igt@gem_busy@busy@all-engines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-hsw-4770/igt@gem_busy@busy@all-engines.html
    - bat-rpls-2:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-rpls-2/igt@gem_busy@busy@all-engines.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-rpls-2/igt@gem_busy@busy@all-engines.html
    - bat-jsl-1:          [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-jsl-1/igt@gem_busy@busy@all-engines.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-jsl-1/igt@gem_busy@busy@all-engines.html
    - fi-cfl-8700k:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-8700k/igt@gem_busy@busy@all-engines.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-8700k/igt@gem_busy@busy@all-engines.html
    - fi-blb-e6850:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-blb-e6850/igt@gem_busy@busy@all-engines.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-blb-e6850/igt@gem_busy@busy@all-engines.html
    - bat-rpls-1:         [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-rpls-1/igt@gem_busy@busy@all-engines.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-rpls-1/igt@gem_busy@busy@all-engines.html
    - bat-adlp-6:         [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-6/igt@gem_busy@busy@all-engines.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-6/igt@gem_busy@busy@all-engines.html
    - fi-rkl-11600:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-rkl-11600/igt@gem_busy@busy@all-engines.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-rkl-11600/igt@gem_busy@busy@all-engines.html
    - fi-skl-6600u:       [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-skl-6600u/igt@gem_busy@busy@all-engines.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-skl-6600u/igt@gem_busy@busy@all-engines.html
    - bat-adls-5:         [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adls-5/igt@gem_busy@busy@all-engines.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adls-5/igt@gem_busy@busy@all-engines.html
    - fi-apl-guc:         [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-apl-guc/igt@gem_busy@busy@all-engines.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-apl-guc/igt@gem_busy@busy@all-engines.html
    - bat-dg1-5:          [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg1-5/igt@gem_busy@busy@all-engines.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg1-5/igt@gem_busy@busy@all-engines.html
    - fi-pnv-d510:        NOTRUN -> [FAIL][25]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-pnv-d510/igt@gem_busy@busy@all-engines.html
    - bat-atsm-1:         [PASS][26] -> [FAIL][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-atsm-1/igt@gem_busy@busy@all-engines.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-atsm-1/igt@gem_busy@busy@all-engines.html
    - bat-dg1-7:          [PASS][28] -> [FAIL][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg1-7/igt@gem_busy@busy@all-engines.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg1-7/igt@gem_busy@busy@all-engines.html
    - bat-jsl-3:          [PASS][30] -> [FAIL][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-jsl-3/igt@gem_busy@busy@all-engines.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-jsl-3/igt@gem_busy@busy@all-engines.html
    - fi-glk-j4005:       [PASS][32] -> [FAIL][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-glk-j4005/igt@gem_busy@busy@all-engines.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-glk-j4005/igt@gem_busy@busy@all-engines.html
    - bat-adlp-9:         [PASS][34] -> [FAIL][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-9/igt@gem_busy@busy@all-engines.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-9/igt@gem_busy@busy@all-engines.html
    - fi-skl-guc:         [PASS][36] -> [FAIL][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-skl-guc/igt@gem_busy@busy@all-engines.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-skl-guc/igt@gem_busy@busy@all-engines.html
    - bat-dg2-11:         [PASS][38] -> [FAIL][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-11/igt@gem_busy@busy@all-engines.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-11/igt@gem_busy@busy@all-engines.html
    - fi-cfl-8109u:       [PASS][40] -> [FAIL][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-8109u/igt@gem_busy@busy@all-engines.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-8109u/igt@gem_busy@busy@all-engines.html
    - fi-kbl-7567u:       [PASS][42] -> [FAIL][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-7567u/igt@gem_busy@busy@all-engines.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-7567u/igt@gem_busy@busy@all-engines.html
    - bat-adln-1:         [PASS][44] -> [FAIL][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adln-1/igt@gem_busy@busy@all-engines.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adln-1/igt@gem_busy@busy@all-engines.html
    - fi-kbl-8809g:       [PASS][46] -> [FAIL][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-8809g/igt@gem_busy@busy@all-engines.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-8809g/igt@gem_busy@busy@all-engines.html
    - fi-ivb-3770:        [PASS][48] -> [FAIL][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-ivb-3770/igt@gem_busy@busy@all-engines.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-ivb-3770/igt@gem_busy@busy@all-engines.html
    - fi-elk-e7500:       [PASS][50] -> [FAIL][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-elk-e7500/igt@gem_busy@busy@all-engines.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-elk-e7500/igt@gem_busy@busy@all-engines.html
    - bat-dg2-8:          [PASS][52] -> [FAIL][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-8/igt@gem_busy@busy@all-engines.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-8/igt@gem_busy@busy@all-engines.html
    - fi-bsw-nick:        [PASS][54] -> [FAIL][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-bsw-nick/igt@gem_busy@busy@all-engines.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-bsw-nick/igt@gem_busy@busy@all-engines.html
    - fi-kbl-guc:         [PASS][56] -> [FAIL][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-guc/igt@gem_busy@busy@all-engines.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-guc/igt@gem_busy@busy@all-engines.html
    - bat-adlm-1:         [PASS][58] -> [FAIL][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlm-1/igt@gem_busy@busy@all-engines.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlm-1/igt@gem_busy@busy@all-engines.html
    - fi-ilk-650:         [PASS][60] -> [FAIL][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-ilk-650/igt@gem_busy@busy@all-engines.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-ilk-650/igt@gem_busy@busy@all-engines.html
    - fi-tgl-1115g4:      [PASS][62] -> [FAIL][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-tgl-1115g4/igt@gem_busy@busy@all-engines.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-tgl-1115g4/igt@gem_busy@busy@all-engines.html
    - fi-bsw-n3050:       [PASS][64] -> [FAIL][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-bsw-n3050/igt@gem_busy@busy@all-engines.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-bsw-n3050/igt@gem_busy@busy@all-engines.html
    - fi-cfl-guc:         [PASS][66] -> [FAIL][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-guc/igt@gem_busy@busy@all-engines.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-guc/igt@gem_busy@busy@all-engines.html
    - bat-dg2-9:          [PASS][68] -> [FAIL][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-9/igt@gem_busy@busy@all-engines.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-9/igt@gem_busy@busy@all-engines.html
    - fi-kbl-x1275:       [PASS][70] -> [FAIL][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-x1275/igt@gem_busy@busy@all-engines.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-x1275/igt@gem_busy@busy@all-engines.html

  * igt@gem_exec_fence@basic-await@rcs0:
    - fi-cfl-guc:         [PASS][72] -> [CRASH][73] +6 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-guc/igt@gem_exec_fence@basic-await@rcs0.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-guc/igt@gem_exec_fence@basic-await@rcs0.html
    - bat-dg2-9:          [PASS][74] -> [CRASH][75] +6 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-9/igt@gem_exec_fence@basic-await@rcs0.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-9/igt@gem_exec_fence@basic-await@rcs0.html
    - fi-hsw-4770:        [PASS][76] -> [CRASH][77] +8 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-hsw-4770/igt@gem_exec_fence@basic-await@rcs0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-hsw-4770/igt@gem_exec_fence@basic-await@rcs0.html

  * igt@gem_exec_fence@basic-busy@rcs0:
    - bat-rpls-2:         [PASS][78] -> [CRASH][79] +5 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-rpls-2/igt@gem_exec_fence@basic-busy@rcs0.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-rpls-2/igt@gem_exec_fence@basic-busy@rcs0.html
    - bat-jsl-1:          [PASS][80] -> [CRASH][81] +6 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-jsl-1/igt@gem_exec_fence@basic-busy@rcs0.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-jsl-1/igt@gem_exec_fence@basic-busy@rcs0.html
    - fi-blb-e6850:       [PASS][82] -> [CRASH][83] +7 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-blb-e6850/igt@gem_exec_fence@basic-busy@rcs0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-blb-e6850/igt@gem_exec_fence@basic-busy@rcs0.html
    - bat-rpls-1:         [PASS][84] -> [CRASH][85] +5 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-rpls-1/igt@gem_exec_fence@basic-busy@rcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-rpls-1/igt@gem_exec_fence@basic-busy@rcs0.html

  * igt@gem_exec_fence@basic-wait@rcs0:
    - fi-apl-guc:         [PASS][86] -> [CRASH][87] +6 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-apl-guc/igt@gem_exec_fence@basic-wait@rcs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-apl-guc/igt@gem_exec_fence@basic-wait@rcs0.html
    - bat-dg1-5:          [PASS][88] -> [CRASH][89] +6 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg1-5/igt@gem_exec_fence@basic-wait@rcs0.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg1-5/igt@gem_exec_fence@basic-wait@rcs0.html
    - fi-pnv-d510:        NOTRUN -> [CRASH][90] +7 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-pnv-d510/igt@gem_exec_fence@basic-wait@rcs0.html
    - bat-dg1-7:          [PASS][91] -> [CRASH][92] +5 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg1-7/igt@gem_exec_fence@basic-wait@rcs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg1-7/igt@gem_exec_fence@basic-wait@rcs0.html
    - bat-jsl-3:          [PASS][93] -> [CRASH][94] +6 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-jsl-3/igt@gem_exec_fence@basic-wait@rcs0.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-jsl-3/igt@gem_exec_fence@basic-wait@rcs0.html
    - fi-glk-j4005:       [PASS][95] -> [CRASH][96] +6 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-glk-j4005/igt@gem_exec_fence@basic-wait@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-glk-j4005/igt@gem_exec_fence@basic-wait@rcs0.html
    - bat-adlp-9:         [PASS][97] -> [CRASH][98] +6 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-9/igt@gem_exec_fence@basic-wait@rcs0.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-9/igt@gem_exec_fence@basic-wait@rcs0.html

  * igt@gem_exec_fence@nb-await@rcs0:
    - fi-bsw-n3050:       [PASS][99] -> [CRASH][100] +8 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-bsw-n3050/igt@gem_exec_fence@nb-await@rcs0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-bsw-n3050/igt@gem_exec_fence@nb-await@rcs0.html

  * igt@gem_exec_gttfill@basic:
    - fi-hsw-4770:        [PASS][101] -> [TIMEOUT][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-hsw-4770/igt@gem_exec_gttfill@basic.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-hsw-4770/igt@gem_exec_gttfill@basic.html

  * igt@gem_wait@busy@all-engines:
    - fi-skl-guc:         [PASS][103] -> [CRASH][104] +6 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-skl-guc/igt@gem_wait@busy@all-engines.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-skl-guc/igt@gem_wait@busy@all-engines.html
    - bat-dg2-11:         [PASS][105] -> [CRASH][106] +6 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-11/igt@gem_wait@busy@all-engines.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-11/igt@gem_wait@busy@all-engines.html
    - fi-kbl-x1275:       [PASS][107] -> [CRASH][108] +5 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-x1275/igt@gem_wait@busy@all-engines.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-x1275/igt@gem_wait@busy@all-engines.html
    - fi-cfl-8109u:       [PASS][109] -> [CRASH][110] +6 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-8109u/igt@gem_wait@busy@all-engines.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-8109u/igt@gem_wait@busy@all-engines.html
    - fi-kbl-8809g:       [PASS][111] -> [CRASH][112] +5 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-8809g/igt@gem_wait@busy@all-engines.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-8809g/igt@gem_wait@busy@all-engines.html
    - fi-ivb-3770:        [PASS][113] -> [CRASH][114] +8 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-ivb-3770/igt@gem_wait@busy@all-engines.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-ivb-3770/igt@gem_wait@busy@all-engines.html
    - bat-dg2-8:          [PASS][115] -> [CRASH][116] +6 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-8/igt@gem_wait@busy@all-engines.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-8/igt@gem_wait@busy@all-engines.html
    - fi-bsw-nick:        [PASS][117] -> [CRASH][118] +5 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-bsw-nick/igt@gem_wait@busy@all-engines.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-bsw-nick/igt@gem_wait@busy@all-engines.html
    - fi-kbl-guc:         [PASS][119] -> [CRASH][120] +5 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-guc/igt@gem_wait@busy@all-engines.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-guc/igt@gem_wait@busy@all-engines.html
    - bat-adlm-1:         [PASS][121] -> [CRASH][122] +5 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlm-1/igt@gem_wait@busy@all-engines.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlm-1/igt@gem_wait@busy@all-engines.html
    - fi-ilk-650:         [PASS][123] -> [CRASH][124] +8 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-ilk-650/igt@gem_wait@busy@all-engines.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-ilk-650/igt@gem_wait@busy@all-engines.html

  * igt@gem_wait@wait@all-engines:
    - bat-adlp-6:         [PASS][125] -> [CRASH][126] +6 similar issues
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-6/igt@gem_wait@wait@all-engines.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-6/igt@gem_wait@wait@all-engines.html
    - fi-rkl-11600:       [PASS][127] -> [CRASH][128] +6 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-rkl-11600/igt@gem_wait@wait@all-engines.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-rkl-11600/igt@gem_wait@wait@all-engines.html
    - fi-skl-6600u:       [PASS][129] -> [CRASH][130] +6 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-skl-6600u/igt@gem_wait@wait@all-engines.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-skl-6600u/igt@gem_wait@wait@all-engines.html
    - bat-adls-5:         [PASS][131] -> [CRASH][132] +5 similar issues
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adls-5/igt@gem_wait@wait@all-engines.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adls-5/igt@gem_wait@wait@all-engines.html
    - bat-atsm-1:         [PASS][133] -> [CRASH][134] +5 similar issues
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-atsm-1/igt@gem_wait@wait@all-engines.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-atsm-1/igt@gem_wait@wait@all-engines.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-7567u:       [PASS][135] -> [CRASH][136] +6 similar issues
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-kbl-7567u/igt@kms_busy@basic@flip.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-kbl-7567u/igt@kms_busy@basic@flip.html
    - bat-adln-1:         [PASS][137] -> [CRASH][138] +6 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adln-1/igt@kms_busy@basic@flip.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adln-1/igt@kms_busy@basic@flip.html
    - fi-cfl-8700k:       [PASS][139] -> [CRASH][140] +6 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-cfl-8700k/igt@kms_busy@basic@flip.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-cfl-8700k/igt@kms_busy@basic@flip.html
    - fi-elk-e7500:       [PASS][141] -> [CRASH][142] +8 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-elk-e7500/igt@kms_busy@basic@flip.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-elk-e7500/igt@kms_busy@basic@flip.html
    - fi-tgl-1115g4:      [PASS][143] -> [CRASH][144] +6 similar issues
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/fi-tgl-1115g4/igt@kms_busy@basic@flip.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-tgl-1115g4/igt@kms_busy@basic@flip.html

  * igt@kms_flip@basic-flip-vs-dpms@b-edp1:
    - bat-adln-1:         [PASS][145] -> [ABORT][146]
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adln-1/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adln-1/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html

  * igt@kms_force_connector_basic@force-edid:
    - bat-adlp-9:         [PASS][147] -> [ABORT][148]
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-9/igt@kms_force_connector_basic@force-edid.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-9/igt@kms_force_connector_basic@force-edid.html

  
#### Warnings ####

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - bat-adlp-6:         [SKIP][149] ([i915#7828]) -> [ABORT][150]
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-adlp-6/igt@kms_chamelium_frames@hdmi-crc-fast.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-adlp-6/igt@kms_chamelium_frames@hdmi-crc-fast.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_busy@busy@all-engines:
    - {bat-mtlp-8}:       [PASS][151] -> [FAIL][152]
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-mtlp-8/igt@gem_busy@busy@all-engines.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-mtlp-8/igt@gem_busy@busy@all-engines.html
    - {bat-kbl-2}:        [PASS][153] -> [FAIL][154]
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-kbl-2/igt@gem_busy@busy@all-engines.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-kbl-2/igt@gem_busy@busy@all-engines.html
    - {bat-mtlp-6}:       [PASS][155] -> [FAIL][156]
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-mtlp-6/igt@gem_busy@busy@all-engines.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-mtlp-6/igt@gem_busy@busy@all-engines.html

  * igt@gem_exec_fence@basic-await@rcs0:
    - {bat-mtlp-6}:       [PASS][157] -> [CRASH][158] +5 similar issues
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-mtlp-6/igt@gem_exec_fence@basic-await@rcs0.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-mtlp-6/igt@gem_exec_fence@basic-await@rcs0.html

  * igt@gem_exec_fence@basic-busy@rcs0:
    - {bat-mtlp-8}:       [PASS][159] -> [CRASH][160] +6 similar issues
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-mtlp-8/igt@gem_exec_fence@basic-busy@rcs0.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-mtlp-8/igt@gem_exec_fence@basic-busy@rcs0.html

  * igt@gem_wait@wait@all-engines:
    - {bat-kbl-2}:        [PASS][161] -> [CRASH][162] +5 similar issues
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-kbl-2/igt@gem_wait@wait@all-engines.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-kbl-2/igt@gem_wait@wait@all-engines.html

  * igt@i915_pm_rpm@basic-rte:
    - {bat-mtlp-8}:       [PASS][163] -> [ABORT][164]
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html

  
Known issues
------------

  Here are the changes found in IGTPW_9147 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@guc:
    - bat-rpls-2:         [PASS][165] -> [DMESG-WARN][166] ([i915#7852])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-rpls-2/igt@i915_selftest@live@guc.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-rpls-2/igt@i915_selftest@live@guc.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][167] ([fdo#109271]) +36 similar issues
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-pnv-d510:        NOTRUN -> [SKIP][168] ([fdo#109271] / [i915#4579])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/fi-pnv-d510/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
    - bat-dg2-8:          [FAIL][169] ([i915#7932]) -> [PASS][170] +1 similar issue
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7326/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7326 -> IGTPW_9147

  CI-20190529: 20190529
  CI_DRM_13261: 05a9d13d90594f3e592f5992a05b00641c936350 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9147: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/index.html
  IGT_7326: 02c2cf17628b6203d6105d4a91dfe8a101d482ce @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_spin_batch@spin-all
+igt@xe_spin_batch@spin-basic
+igt@xe_spin_batch@spin-basic-all
+igt@xe_spin_batch@spin-batch

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9147/index.html

[-- Attachment #2: Type: text/html, Size: 29169 bytes --]

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  40 +++++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         |  97 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   5 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 328 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 ++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  96 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 182 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 328 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 +++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  97 ++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 315 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         | 121 ++++++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 325 insertions(+), 7 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         | 121 ++++++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 325 insertions(+), 7 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  10 +++
 lib/xe/xe_spin.c         |  91 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 ++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 295 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 +++++--
 lib/igt_dummyload.h      |  10 +++
 lib/xe/xe_spin.c         |  89 +++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 ++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 138 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 263 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 ++++++---
 lib/igt_dummyload.h      |  11 ++++
 lib/xe/xe_spin.c         |  68 +++++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 +++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 218 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1