[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 ++++++---
 lib/igt_dummyload.h      |  11 ++++
 lib/xe/xe_spin.c         |  68 +++++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 +++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 218 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 +++++--
 lib/igt_dummyload.h      |  10 +++
 lib/xe/xe_spin.c         |  89 +++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 ++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 138 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 263 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe.
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  10 +++
 lib/xe/xe_spin.c         |  91 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   7 ++
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 295 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         | 121 ++++++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 325 insertions(+), 7 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  24 ++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         | 121 ++++++++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 325 insertions(+), 7 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 +++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  97 ++++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 315 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 +++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  96 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 326 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  38 ++++++--
 lib/igt_dummyload.h      |  11 +++
 lib/xe/xe_spin.c         |  96 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   6 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 182 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 328 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/xe/xe_spin: Integrate igt_spin_new with Xe
  tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

 lib/igt_dummyload.c      |  40 +++++++--
 lib/igt_dummyload.h      |  12 +++
 lib/xe/xe_spin.c         |  97 +++++++++++++++++++++
 lib/xe/xe_spin.h         |   5 +-
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 328 insertions(+), 6 deletions(-)
 create mode 100644 tests/xe/xe_spin_batch.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/igt_dummyload.c | 40 ++++++++++++++++---
 lib/igt_dummyload.h | 12 ++++++
 lib/xe/xe_spin.c    | 97 +++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_spin.h    |  5 ++-
 4 files changed, 148 insertions(+), 6 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 740a58f3..9f941cef 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -46,6 +46,7 @@
 #include "intel_reg.h"
 #include "ioctl_wrappers.h"
 #include "sw_sync.h"
+#include "xe/xe_spin.h"
 
 /**
  * SECTION:igt_dummyload
@@ -434,6 +435,7 @@ spin_create(int fd, const struct igt_spin_factory *opts)
 	spin = calloc(1, sizeof(struct igt_spin));
 	igt_assert(spin);
 
+	spin->driver = INTEL_DRIVER_I915;
 	spin->timerfd = -1;
 	spin->out_fence = emit_recursive_batch(spin, fd, opts);
 
@@ -447,7 +449,19 @@ spin_create(int fd, const struct igt_spin_factory *opts)
 igt_spin_t *
 __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 {
-	return spin_create(fd, opts);
+	if (is_xe_device(fd)) {
+		igt_spin_t *spin;
+
+		spin = xe_spin_create(fd, opts);
+
+		pthread_mutex_lock(&list_lock);
+		igt_list_add(&spin->link, &spin_list);
+		pthread_mutex_unlock(&list_lock);
+
+		return spin;
+	} else {
+		return spin_create(fd, opts);
+	}
 }
 
 /**
@@ -467,6 +481,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 {
 	igt_spin_t *spin;
 
+	if (is_xe_device(fd)) {
+		spin = xe_spin_create(fd, opts);
+
+		pthread_mutex_lock(&list_lock);
+		igt_list_add(&spin->link, &spin_list);
+		pthread_mutex_unlock(&list_lock);
+
+		return spin;
+	}
+
 	if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
 		unsigned int class;
 
@@ -597,8 +621,12 @@ void igt_spin_end(igt_spin_t *spin)
 	if (!spin)
 		return;
 
-	igt_gettime(&spin->last_signal);
-	sync_write(spin, MI_BATCH_BUFFER_END);
+	if (spin->driver == INTEL_DRIVER_XE) {
+		xe_spin_end(spin->xe_spin);
+	} else {
+		igt_gettime(&spin->last_signal);
+		sync_write(spin, MI_BATCH_BUFFER_END);
+	}
 }
 
 static void __igt_spin_free(int fd, igt_spin_t *spin)
@@ -646,12 +674,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
 {
 	if (!spin)
 		return;
-
 	pthread_mutex_lock(&list_lock);
 	igt_list_del(&spin->link);
 	pthread_mutex_unlock(&list_lock);
 
-	__igt_spin_free(fd, spin);
+	if (spin->driver == INTEL_DRIVER_XE)
+		xe_spin_free(fd, spin);
+	else
+		__igt_spin_free(fd, spin);
 }
 
 void igt_terminate_spins(void)
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index b247ab02..6eb3f2e6 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -28,6 +28,7 @@
 #include <stdint.h>
 #include <time.h>
 
+#include "drmtest.h"
 #include "igt_core.h"
 #include "igt_list.h"
 #include "i915_drm.h"
@@ -54,6 +55,8 @@ typedef struct igt_spin_factory {
 	unsigned int flags;
 	int fence;
 	uint64_t ahnd;
+	struct drm_xe_engine_class_instance *hwe;
+	uint32_t vm;
 } igt_spin_factory_t;
 
 typedef struct igt_spin {
@@ -83,6 +86,15 @@ typedef struct igt_spin {
 #define SPIN_CLFLUSH (1 << 0)
 
 	struct igt_spin_factory opts;
+
+	struct xe_spin *xe_spin;
+	enum intel_driver driver;
+	size_t bo_size;
+	uint64_t address;
+	unsigned int engine;
+	uint32_t vm;
+	uint32_t syncobj;
+
 } igt_spin_t;
 
 
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 856d0ba2..9f511e14 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -82,6 +82,103 @@ void xe_spin_end(struct xe_spin *spin)
 	spin->end = 0;
 }
 
+/**
+ * xe_spin_create:
+ *@opt: controlling options such as allocator handle, engine, vm etc
+ *
+ * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
+ * which wraps around vm bind and unbinding the object associated to it.
+ * This returs a spinner after submitting a dummy load.
+ *
+ */
+igt_spin_t *
+xe_spin_create(int fd, const struct igt_spin_factory *opt)
+{
+	size_t bo_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = opt->ahnd, addr;
+	struct igt_spin *spin;
+	struct xe_spin *xe_spin;
+	struct drm_xe_sync sync = {
+		.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+
+	igt_assert(ahnd);
+	spin = calloc(1, sizeof(struct igt_spin));
+	igt_assert(spin);
+
+	spin->driver = INTEL_DRIVER_XE;
+	spin->syncobj = syncobj_create(fd, 0);
+	spin->vm = opt->vm;
+	spin->engine = opt->engine;
+
+	if (!spin->vm)
+		spin->vm = xe_vm_create(fd, 0, 0);
+
+	if (!spin->engine) {
+		if (opt->hwe)
+			spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
+		else
+			spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
+	}
+
+	spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
+	xe_spin = xe_bo_map(fd, spin->handle, bo_size);
+	addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
+	xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
+
+	xe_spin_init(xe_spin, addr, true);
+	exec.engine_id = spin->engine;
+	exec.address = addr;
+	sync.handle = spin->syncobj;
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+	xe_spin_wait_started(xe_spin);
+
+	spin->bo_size = bo_size;
+	spin->address = addr;
+	spin->xe_spin = xe_spin;
+	spin->opts = *opt;
+
+	return spin;
+}
+
+void xe_spin_sync_wait(int fd, struct igt_spin *spin)
+{
+	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
+}
+
+/*
+ * xe_spin_free:
+ *@spin: spin state from igt_spin_new()
+ *
+ * Wrapper to free spinner whhich is triggered by xe_spin_create.
+ * which distroys vm, engine and unbinds the vm which is binded to
+ * the engine and bo.
+ *
+ */
+void xe_spin_free(int fd, struct igt_spin *spin)
+{
+	igt_assert(spin->driver == INTEL_DRIVER_XE);
+	xe_spin_end(spin->xe_spin);
+	xe_spin_sync_wait(fd, spin);
+	xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
+	syncobj_destroy(fd, spin->syncobj);
+	gem_munmap(spin->xe_spin, spin->bo_size);
+	gem_close(fd, spin->handle);
+
+	if (!spin->opts.engine)
+		xe_engine_destroy(fd, spin->engine);
+
+	if (!spin->opts.vm)
+		xe_vm_destroy(fd, spin->vm);
+
+	free(spin);
+}
+
 void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
 		  struct xe_cork *cork)
 {
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 73f9a026..54a52b40 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -13,6 +13,7 @@
 #include <stdbool.h>
 
 #include "xe_query.h"
+#include "lib/igt_dummyload.h"
 
 /* Mapped GPU object */
 struct xe_spin {
@@ -21,11 +22,13 @@ struct xe_spin {
 	uint32_t start;
 	uint32_t end;
 };
-
+igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
 void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
 bool xe_spin_started(struct xe_spin *spin);
+void xe_spin_sync_wait(int fd, struct igt_spin *spin);
 void xe_spin_wait_started(struct xe_spin *spin);
 void xe_spin_end(struct xe_spin *spin);
+void xe_spin_free(int fd, struct igt_spin *spin);
 
 struct xe_cork {
 	struct xe_spin *spin;
-- 
2.39.1

[igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

xe_spin_batch test exercises igt_spin_new submissions with different
combination.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/meson.build        |   1 +
 tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+)
 create mode 100644 tests/xe/xe_spin_batch.c

diff --git a/tests/meson.build b/tests/meson.build
index 61dcc076..85ea7e74 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -269,6 +269,7 @@ xe_progs = [
 	'xe_query',
 	'xe_vm',
 	'xe_waitfence',
+	'xe_spin_batch',
 ]
 
 msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..b930bc7e
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,179 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+	uint64_t ahnd;
+	igt_spin_t *spin;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+	spin = igt_spin_new(fd, .ahnd = ahnd);
+
+	igt_spin_free(fd, spin);
+	put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+	uint64_t ahnd;
+	unsigned int engine;
+	uint32_t vm;
+	igt_spin_t *spin;
+
+	vm = xe_vm_create(fd, 0, 0);
+	engine = xe_engine_create(fd, vm, hwe, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+
+	igt_spin_free(fd, spin);
+	xe_engine_destroy(fd, engine);
+	xe_vm_destroy(fd, vm);
+
+	put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	uint64_t ahnd;
+	uint32_t vm;
+	igt_spin_t **spin;
+	int i = 0;
+
+	vm = xe_vm_create(fd, 0, 0);
+	ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+	spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+	xe_for_each_hw_engine(fd, hwe) {
+		igt_debug("Run on engine: %s:%d\n",
+				xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
+		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+		i++;
+	}
+
+	while (--i >= 0)
+		igt_spin_free(fd, spin[i]);
+
+	put_ahnd(ahnd);
+	xe_vm_destroy(fd, vm);
+	free(spin);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all(int fd, int gt, int class)
+{
+	uint64_t ahnd;
+	uint32_t engines[MAX_INSTANCE], vm;
+	int i, num_placements = 0;
+	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+	igt_spin_t *spin[MAX_INSTANCE];
+	struct drm_xe_engine_class_instance *hwe;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	xe_for_each_hw_engine(fd, hwe) {
+		if (hwe->engine_class != class || hwe->gt_id != gt)
+			continue;
+		eci[num_placements++] = *hwe;
+	}
+	if (num_placements < 2)
+		return;
+	vm = xe_vm_create(fd, 0, 0);
+
+	for (i = 0; i < num_placements; i++) {
+		struct drm_xe_engine_create create = {
+			.vm_id = vm,
+			.width = 1,
+			.num_placements = num_placements,
+			.instances = to_user_pointer(eci),
+		};
+
+		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+					&create), 0);
+		engines[i] = create.engine_id;
+		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
+	}
+
+	for (i = 0; i < num_placements; i++) {
+		igt_spin_free(fd, spin[i]);
+		xe_engine_destroy(fd, engines[i]);
+	}
+
+	put_ahnd(ahnd);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	struct drm_xe_engine_class_instance *hwe;
+	int fd;
+	int gt, class;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		xe_device_get(fd);
+	}
+
+	igt_subtest("spin-basic")
+		spin_basic(fd);
+
+	igt_subtest("spin-batch")
+		xe_for_each_hw_engine(fd, hwe)
+			spin(fd, hwe);
+
+	igt_subtest("spin-basic-all")
+		spin_basic_all(fd);
+
+	igt_subtest("spin-all") {
+		xe_for_each_gt(fd, gt)
+			xe_for_each_hw_engine_class(class)
+				spin_all(fd, gt, class);
+	}
+
+	igt_fixture {
+		xe_device_put(fd);
+		close(fd);
+	}
+}
-- 
2.39.1

[igt-dev] ✗ GitLab.Pipeline: warning for Integrate igt_spin_new with Xe (rev6)

[Patchwork]

== Series Details ==

Series: Integrate igt_spin_new with Xe (rev6)
URL   : https://patchwork.freedesktop.org/series/118837/
State : warning

== Summary ==

Pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/909912 for the overview.

containers:igt has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43825536):
  Downloading artifacts from coordinator... ok        host=gitlab.freedesktop.org id=43825521 responseStatus=200 OK token=64_SartG
  section_end:1686832687:download_artifacts
  section_start:1686832687:step_script
  Executing "step_script" stage of the job script
  Using docker image sha256:594aa868d31ee3304dee8cae8a3433c89a6fcfcf6c7d420c04cce22f60147176 for registry.freedesktop.org/wayland/ci-templates/buildah:2019-08-13.0 with digest registry.freedesktop.org/wayland/ci-templates/buildah@sha256:7dbcf22cd2c1c7d49db0dc7b4ab207c3d6a4a09bd81cc3b71a688d3727d8749f ...
  $ /host/bin/curl -s -L --cacert /host/ca-certificates.crt --retry 4 -f --retry-delay 60 https://gitlab.freedesktop.org/freedesktop/helm-gitlab-infra/-/raw/main/runner-gating/runner-gating.sh | sh
  Checking if the user of the pipeline is allowed...
  Checking if the job's project is part of a well-known group...
  Thank you for contributing to freedesktop.org
  $ podman login -u gitlab-ci-token -p $CI_JOB_TOKEN $CI_REGISTRY
  Login Succeeded!
  $ .gitlab-ci/pull-or-rebuild.sh igt Dockerfile igt
  STEP 1: FROM registry.freedesktop.org/gfx-ci/igt-ci-tags/build-fedora:commit-fd3a5c12c7c852b10edc4a7c54c96362c7100dd4
  Error: error creating build container: Error initializing source docker://registry.freedesktop.org/gfx-ci/igt-ci-tags/build-fedora:commit-fd3a5c12c7c852b10edc4a7c54c96362c7100dd4: Error reading manifest commit-fd3a5c12c7c852b10edc4a7c54c96362c7100dd4 in registry.freedesktop.org/gfx-ci/igt-ci-tags/build-fedora: received unexpected HTTP status: 500 Internal Server Error
  section_end:1686832689:step_script
  section_start:1686832689:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1686832690:cleanup_file_variables
  ERROR: Job failed: exit code 1

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/909912

[igt-dev] ✗ Fi.CI.BAT: failure for Integrate igt_spin_new with Xe (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9108 bytes --]

== Series Details ==

Series: Integrate igt_spin_new with Xe (rev6)
URL   : https://patchwork.freedesktop.org/series/118837/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7331 -> IGTPW_9179
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_9179 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_9179, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/index.html

Participating hosts (42 -> 42)
------------------------------

  Additional (1): bat-dg1-8 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_9179:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@basic-rte:
    - bat-mtlp-8:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html

  * {igt@xe_live_ktest@.*} (NEW):
    - {bat-dg1-8}:        NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-dg1-8/igt@xe_live_ktest@.*.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@hang-read-crc:
    - {bat-dg1-8}:        NOTRUN -> [SKIP][4] +73 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-dg1-8/igt@kms_pipe_crc_basic@hang-read-crc.html

  * igt@xe_guc_pc@freq_fixed_idle:
    - {bat-dg1-8}:        NOTRUN -> [FAIL][5] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-dg1-8/igt@xe_guc_pc@freq_fixed_idle.html

  
New tests
---------

  New tests have been introduced between IGT_7331 and IGTPW_9179:

### New IGT tests (1) ###

  * igt@xe_live_ktest@.*:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_9179 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_backlight@basic-brightness@edp-1:
    - bat-rplp-1:         NOTRUN -> [ABORT][6] ([i915#7077])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html

  * igt@i915_selftest@live@gt_pm:
    - bat-rpls-2:         [PASS][7] -> [DMESG-FAIL][8] ([i915#4258] / [i915#7913])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-2:         NOTRUN -> [ABORT][9] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         NOTRUN -> [DMESG-WARN][10] ([i915#6367])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-rpls-1:         NOTRUN -> [ABORT][11] ([i915#6687] / [i915#7978])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
    - bat-dg2-8:          [PASS][12] -> [FAIL][13] ([i915#7932])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - fi-bsw-nick:        NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/fi-bsw-nick/igt@kms_pipe_crc_basic@suspend-read-crc.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@engines@userptr:
    - bat-mtlp-6:         [FAIL][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-mtlp-6/igt@gem_exec_parallel@engines@userptr.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-mtlp-6/igt@gem_exec_parallel@engines@userptr.html

  * igt@i915_selftest@live@execlists:
    - fi-kbl-soraka:      [INCOMPLETE][17] ([i915#7156] / [i915#7913]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
    - fi-bsw-nick:        [ABORT][19] ([i915#7911] / [i915#7913]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [DMESG-WARN][21] ([i915#7699]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [ABORT][23] ([i915#4983] / [i915#7913]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-rpls-2/igt@i915_selftest@live@requests.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-2/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-1:         [ABORT][25] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-rpls-1/igt@i915_selftest@live@reset.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rpls-1/igt@i915_selftest@live@reset.html

  
#### Warnings ####

  * igt@i915_module_load@load:
    - bat-adlp-11:        [DMESG-WARN][27] ([i915#4423]) -> [ABORT][28] ([i915#4423])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-adlp-11/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-adlp-11/igt@i915_module_load@load.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rplp-1:         [ABORT][29] ([i915#4579] / [i915#8260]) -> [SKIP][30] ([i915#3555] / [i915#4579])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7331/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
  [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
  [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7331 -> IGTPW_9179

  CI-20190529: 20190529
  CI_DRM_13270: a8b181a60198ccf04a1ad1c34f46be4c2a5e64b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9179: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/index.html
  IGT_7331: 4604cc18a2e7af126996d3b56ad0168e7258e8e9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_spin_batch@spin-all
+igt@xe_spin_batch@spin-basic
+igt@xe_spin_batch@spin-basic-all
+igt@xe_spin_batch@spin-batch

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9179/index.html

[-- Attachment #2: Type: text/html, Size: 10924 bytes --]

Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe

[Zbigniew Kempczyński]

On Thu, Jun 15, 2023 at 04:29:53PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Extending the spin_create implementation and allocator handle support in xe,
> where it submits dummy work loads to engine. This Implementation is wrapped
> around vm_bind and unbind as we are supposed to do it manually for xe.
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  lib/igt_dummyload.c | 40 ++++++++++++++++---
>  lib/igt_dummyload.h | 12 ++++++
>  lib/xe/xe_spin.c    | 97 +++++++++++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_spin.h    |  5 ++-
>  4 files changed, 148 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 740a58f3..9f941cef 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -46,6 +46,7 @@
>  #include "intel_reg.h"
>  #include "ioctl_wrappers.h"
>  #include "sw_sync.h"
> +#include "xe/xe_spin.h"
>  
>  /**
>   * SECTION:igt_dummyload
> @@ -434,6 +435,7 @@ spin_create(int fd, const struct igt_spin_factory *opts)
>  	spin = calloc(1, sizeof(struct igt_spin));
>  	igt_assert(spin);
>  
> +	spin->driver = INTEL_DRIVER_I915;
>  	spin->timerfd = -1;
>  	spin->out_fence = emit_recursive_batch(spin, fd, opts);
>  
> @@ -447,7 +449,19 @@ spin_create(int fd, const struct igt_spin_factory *opts)
>  igt_spin_t *
>  __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
>  {
> -	return spin_create(fd, opts);
> +	if (is_xe_device(fd)) {
> +		igt_spin_t *spin;
> +
> +		spin = xe_spin_create(fd, opts);
> +
> +		pthread_mutex_lock(&list_lock);
> +		igt_list_add(&spin->link, &spin_list);
> +		pthread_mutex_unlock(&list_lock);
> +
> +		return spin;
> +	} else {
> +		return spin_create(fd, opts);
> +	}
>  }
>  
>  /**
> @@ -467,6 +481,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
>  {
>  	igt_spin_t *spin;
>  
> +	if (is_xe_device(fd)) {
> +		spin = xe_spin_create(fd, opts);
> +
> +		pthread_mutex_lock(&list_lock);
> +		igt_list_add(&spin->link, &spin_list);
> +		pthread_mutex_unlock(&list_lock);
> +
> +		return spin;
> +	}
> +
>  	if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
>  		unsigned int class;
>  
> @@ -597,8 +621,12 @@ void igt_spin_end(igt_spin_t *spin)
>  	if (!spin)
>  		return;
>  
> -	igt_gettime(&spin->last_signal);
> -	sync_write(spin, MI_BATCH_BUFFER_END);
> +	if (spin->driver == INTEL_DRIVER_XE) {
> +		xe_spin_end(spin->xe_spin);
> +	} else {
> +		igt_gettime(&spin->last_signal);
> +		sync_write(spin, MI_BATCH_BUFFER_END);
> +	}
>  }
>  
>  static void __igt_spin_free(int fd, igt_spin_t *spin)
> @@ -646,12 +674,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
>  {
>  	if (!spin)
>  		return;
> -
>  	pthread_mutex_lock(&list_lock);
>  	igt_list_del(&spin->link);
>  	pthread_mutex_unlock(&list_lock);
>  
> -	__igt_spin_free(fd, spin);
> +	if (spin->driver == INTEL_DRIVER_XE)
> +		xe_spin_free(fd, spin);
> +	else
> +		__igt_spin_free(fd, spin);
>  }
>  
>  void igt_terminate_spins(void)
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index b247ab02..6eb3f2e6 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -28,6 +28,7 @@
>  #include <stdint.h>
>  #include <time.h>
>  
> +#include "drmtest.h"
>  #include "igt_core.h"
>  #include "igt_list.h"
>  #include "i915_drm.h"
> @@ -54,6 +55,8 @@ typedef struct igt_spin_factory {
>  	unsigned int flags;
>  	int fence;
>  	uint64_t ahnd;
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint32_t vm;
>  } igt_spin_factory_t;
>  
>  typedef struct igt_spin {
> @@ -83,6 +86,15 @@ typedef struct igt_spin {
>  #define SPIN_CLFLUSH (1 << 0)
>  
>  	struct igt_spin_factory opts;
> +
> +	struct xe_spin *xe_spin;
> +	enum intel_driver driver;
> +	size_t bo_size;
> +	uint64_t address;
> +	unsigned int engine;
> +	uint32_t vm;
> +	uint32_t syncobj;
> +
>  } igt_spin_t;
>  
>  
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..9f511e14 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -82,6 +82,103 @@ void xe_spin_end(struct xe_spin *spin)
>  	spin->end = 0;
>  }
>  
> +/**
> + * xe_spin_create:
> + *@opt: controlling options such as allocator handle, engine, vm etc
> + *
> + * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
> + * which wraps around vm bind and unbinding the object associated to it.
> + * This returs a spinner after submitting a dummy load.
> + *
> + */
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt)
> +{
> +	size_t bo_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = opt->ahnd, addr;
> +	struct igt_spin *spin;
> +	struct xe_spin *xe_spin;
> +	struct drm_xe_sync sync = {
> +		.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +
> +	igt_assert(ahnd);
> +	spin = calloc(1, sizeof(struct igt_spin));
> +	igt_assert(spin);
> +
> +	spin->driver = INTEL_DRIVER_XE;
> +	spin->syncobj = syncobj_create(fd, 0);
> +	spin->vm = opt->vm;
> +	spin->engine = opt->engine;
> +
> +	if (!spin->vm)
> +		spin->vm = xe_vm_create(fd, 0, 0);
> +
> +	if (!spin->engine) {
> +		if (opt->hwe)
> +			spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> +		else
> +			spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
> +	}
> +
> +	spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
> +	xe_spin = xe_bo_map(fd, spin->handle, bo_size);
> +	addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> +	xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> +
> +	xe_spin_init(xe_spin, addr, true);
> +	exec.engine_id = spin->engine;
> +	exec.address = addr;
> +	sync.handle = spin->syncobj;
> +	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> +	xe_spin_wait_started(xe_spin);
> +
> +	spin->bo_size = bo_size;
> +	spin->address = addr;
> +	spin->xe_spin = xe_spin;
> +	spin->opts = *opt;
> +
> +	return spin;
> +}
> +
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +{
> +	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
> +}
> +
> +/*
> + * xe_spin_free:
> + *@spin: spin state from igt_spin_new()
> + *
> + * Wrapper to free spinner whhich is triggered by xe_spin_create.
> + * which distroys vm, engine and unbinds the vm which is binded to
> + * the engine and bo.
> + *
> + */
> +void xe_spin_free(int fd, struct igt_spin *spin)
> +{
> +	igt_assert(spin->driver == INTEL_DRIVER_XE);
> +	xe_spin_end(spin->xe_spin);
> +	xe_spin_sync_wait(fd, spin);
> +	xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> +	syncobj_destroy(fd, spin->syncobj);
> +	gem_munmap(spin->xe_spin, spin->bo_size);
> +	gem_close(fd, spin->handle);
> +
> +	if (!spin->opts.engine)
> +		xe_engine_destroy(fd, spin->engine);
> +
> +	if (!spin->opts.vm)
> +		xe_vm_destroy(fd, spin->vm);
> +
> +	free(spin);
> +}
> +
>  void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>  		  struct xe_cork *cork)
>  {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 73f9a026..54a52b40 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -13,6 +13,7 @@
>  #include <stdbool.h>
>  
>  #include "xe_query.h"
> +#include "lib/igt_dummyload.h"
>  
>  /* Mapped GPU object */
>  struct xe_spin {
> @@ -21,11 +22,13 @@ struct xe_spin {
>  	uint32_t start;
>  	uint32_t end;
>  };
> -
> +igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
>  void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
>  bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>  void xe_spin_wait_started(struct xe_spin *spin);
>  void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_free(int fd, struct igt_spin *spin);
>  
>  struct xe_cork {
>  	struct xe_spin *spin;
> -- 
> 2.39.1
> 

Ok, now it looks good for me. If someone would need some additional
feature we may add this later.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe

[Zbigniew Kempczyński]

On Thu, Jun 15, 2023 at 04:29:54PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/meson.build        |   1 +
>  tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 180 insertions(+)
>  create mode 100644 tests/xe/xe_spin_batch.c
> 
> diff --git a/tests/meson.build b/tests/meson.build
> index 61dcc076..85ea7e74 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -269,6 +269,7 @@ xe_progs = [
>  	'xe_query',
>  	'xe_vm',
>  	'xe_waitfence',
> +	'xe_spin_batch',
>  ]
>  
>  msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..b930bc7e
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,179 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> +	uint64_t ahnd;
> +	igt_spin_t *spin;
> +
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +	spin = igt_spin_new(fd, .ahnd = ahnd);
> +
> +	igt_spin_free(fd, spin);
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> +	uint64_t ahnd;
> +	unsigned int engine;
> +	uint32_t vm;
> +	igt_spin_t *spin;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	engine = xe_engine_create(fd, vm, hwe, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> +	spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> +
> +	igt_spin_free(fd, spin);
> +	xe_engine_destroy(fd, engine);
> +	xe_vm_destroy(fd, vm);
> +
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd)
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint64_t ahnd;
> +	uint32_t vm;
> +	igt_spin_t **spin;
> +	int i = 0;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
> +	spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
> +	xe_for_each_hw_engine(fd, hwe) {
> +		igt_debug("Run on engine: %s:%d\n",
> +				xe_engine_class_string(hwe->engine_class), hwe->engine_instance);

Just minor nit - invalid indentation. Try to not neglect this in the future.
I'm going to fix this before merge.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> +		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
> +		i++;
> +	}
> +
> +	while (--i >= 0)
> +		igt_spin_free(fd, spin[i]);
> +
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +	free(spin);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all(int fd, int gt, int class)
> +{
> +	uint64_t ahnd;
> +	uint32_t engines[MAX_INSTANCE], vm;
> +	int i, num_placements = 0;
> +	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> +	igt_spin_t *spin[MAX_INSTANCE];
> +	struct drm_xe_engine_class_instance *hwe;
> +
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> +	xe_for_each_hw_engine(fd, hwe) {
> +		if (hwe->engine_class != class || hwe->gt_id != gt)
> +			continue;
> +		eci[num_placements++] = *hwe;
> +	}
> +	if (num_placements < 2)
> +		return;
> +	vm = xe_vm_create(fd, 0, 0);
> +
> +	for (i = 0; i < num_placements; i++) {
> +		struct drm_xe_engine_create create = {
> +			.vm_id = vm,
> +			.width = 1,
> +			.num_placements = num_placements,
> +			.instances = to_user_pointer(eci),
> +		};
> +
> +		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> +					&create), 0);
> +		engines[i] = create.engine_id;
> +		spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
> +	}
> +
> +	for (i = 0; i < num_placements; i++) {
> +		igt_spin_free(fd, spin[i]);
> +		xe_engine_destroy(fd, engines[i]);
> +	}
> +
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	int fd;
> +	int gt, class;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		xe_device_get(fd);
> +	}
> +
> +	igt_subtest("spin-basic")
> +		spin_basic(fd);
> +
> +	igt_subtest("spin-batch")
> +		xe_for_each_hw_engine(fd, hwe)
> +			spin(fd, hwe);
> +
> +	igt_subtest("spin-basic-all")
> +		spin_basic_all(fd);
> +
> +	igt_subtest("spin-all") {
> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				spin_all(fd, gt, class);
> +	}
> +
> +	igt_fixture {
> +		xe_device_put(fd);
> +		close(fd);
> +	}
> +}
> -- 
> 2.39.1
>