* [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands
@ 2023-08-18 5:19 sai.gowtham.ch
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib sai.gowtham.ch
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: sai.gowtham.ch @ 2023-08-18 5:19 UTC (permalink / raw)
To: igt-dev, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test to exercise copy commands like mem-copy and mem-set.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
lib/intel_reg: Add copy commands in the lib
tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_mocs.h | 2 +
lib/intel_reg.h | 4 +
tests/meson.build | 1 +
tests/xe/xe_copy_basic.c | 262 +++++++++++++++++++++++++++++++++++++++
4 files changed, 269 insertions(+)
create mode 100644 tests/xe/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
@ 2023-08-18 5:19 ` sai.gowtham.ch
2023-08-18 13:40 ` Karolina Stolarek
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: sai.gowtham.ch @ 2023-08-18 5:19 UTC (permalink / raw)
To: igt-dev, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add memory copy and set commands to the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
lib/intel_mocs.h | 2 ++
lib/intel_reg.h | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
index 255eac0ff..4f4cf53e0 100644
--- a/lib/intel_mocs.h
+++ b/lib/intel_mocs.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_MOCS_H
#define _INTEL_MOCS_H
+#define MEM_COPY_MOCS_SHIFT 25
+
uint8_t intel_get_wb_mocs(int fd);
uint8_t intel_get_uc_mocs(int fd);
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 3bf3676dc..322aec9fd 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2564,6 +2564,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define XY_FAST_COLOR_BLT ((0x2<<29)|(0x44<<22)|0xe)
+/* RAW memory commands */
+#define MEM_COPY_CMD ((0x2 << 29)|(0x5a << 22)|0x8)
+#define MEM_SET_CMD ((0x2 << 29)|(0x5b << 22)|0x5)
+
#define XY_FAST_COPY_BLT ((2<<29)|(0x42<<22)|0x8)
/* dword 0 */
#define XY_FAST_COPY_SRC_TILING_LINEAR (0 << 20)
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib sai.gowtham.ch
@ 2023-08-18 5:19 ` sai.gowtham.ch
2023-08-18 13:40 ` Karolina Stolarek
2023-08-18 6:24 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: sai.gowtham.ch @ 2023-08-18 5:19 UTC (permalink / raw)
To: igt-dev, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test to exercise copy commands like mem-copy and mem-set.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_copy_basic.c | 262 +++++++++++++++++++++++++++++++++++++++
2 files changed, 263 insertions(+)
create mode 100644 tests/xe/xe_copy_basic.c
diff --git a/tests/meson.build b/tests/meson.build
index 58061dbc2..323c2108a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -266,6 +266,7 @@ xe_progs = [
'xe_ccs',
'xe_create',
'xe_compute',
+ 'xe_copy_basic',
'xe_dma_buf_sync',
'xe_debugfs',
'xe_evict',
diff --git a/tests/xe/xe_copy_basic.c b/tests/xe/xe_copy_basic.c
new file mode 100644
index 000000000..ce1223eb1
--- /dev/null
+++ b/tests/xe/xe_copy_basic.c
@@ -0,0 +1,262 @@
+/* SPDX-License-Identifier: MIT */
+/*
+* Copyright © 2023 Intel Corporation
+*
+* Authors:
+* Sai Gowtham Ch <sai.gowtham.ch@intel.com>
+*/
+
+#include "igt.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "lib/intel_mocs.h"
+#include "lib/intel_reg.h"
+#include "lib/igt_syncobj.h"
+#include "lib/xe/xe_util.h"
+
+/**
+ * TEST: Test to valiudate copy commands on xe
+ * Category: Software building block
+ * Sub-category: Copy
+ * Functionality: blitter
+ * Test category: functionality test
+ */
+
+enum command {
+ MEM_COPY,
+ MEM_SET,
+};
+
+static int objcmp(int fd, uint32_t src, uint32_t dst,
+ uint32_t src_size, uint32_t dst_size)
+{
+ void *buf_src, *buf_dst;
+ int ret = 0;
+
+ buf_src = xe_bo_map(fd, src, src_size);
+ buf_dst = xe_bo_map(fd, dst, dst_size);
+
+ ret = memcmp(buf_src, buf_dst , src_size);
+
+ munmap(buf_src, src_size);
+ munmap(buf_dst, dst_size);
+
+ return ret;
+}
+
+/**
+ * SUBTEST: mem-copy
+ * Description: Test validates MEM_COPY command, it takes various
+ * parameters needed for the filling batch buffer for MEM_COPY command.
+ * Run type: FULL
+ */
+
+static void
+igt_mem_copy(int fd, uint32_t src, uint32_t dst,
+ uint32_t size, uint32_t col_size, uint32_t src_pitch,
+ uint32_t dst_pitch, uint32_t vm, uint32_t engine)
+{
+ struct drm_xe_sync sync = {
+ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ };
+
+ uint32_t bb_handle, syncobj;
+ struct {
+ uint32_t batch[12];
+ uint32_t data;
+ } *data;
+
+ uint64_t bb_offset, src_offset, dst_offset;
+ uint64_t alignment;
+ uint8_t src_mocs = intel_get_uc_mocs(fd);
+ uint64_t bb_size = xe_get_default_alignment(fd);
+ uint8_t dst_mocs = src_mocs;
+ uint64_t ahnd;
+ int i;
+
+ alignment = xe_get_default_alignment(fd);
+
+ bb_handle = xe_bo_create_flags(fd, 0, bb_size, visible_vram_if_possible(fd, 0));
+ data = xe_bo_map(fd, bb_handle, bb_size);
+
+ ahnd = intel_allocator_open_full(fd, vm, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ src_offset = get_offset(ahnd, src, size, alignment);
+ dst_offset = get_offset(ahnd, dst, size, alignment);
+ bb_offset = get_offset(ahnd, bb_handle, bb_size, alignment);
+
+ i = 0;
+ data->batch[i++] = MEM_COPY_CMD;
+ data->batch[i++] = size - 1;
+ data->batch[i++] = col_size - 1;
+ data->batch[i++] = src_pitch;
+ data->batch[i++] = dst_pitch;
+ data->batch[i++] = src_offset;
+ data->batch[i++] = src_offset << 32;
+ data->batch[i++] = dst_offset;
+ data->batch[i++] = dst_offset << 32;
+ data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
+ data->batch[i++] = MI_BATCH_BUFFER_END;
+ data->batch[i++] = MI_NOOP;
+
+ syncobj = syncobj_create(fd, 0);
+ sync.handle = syncobj;
+
+ xe_vm_bind_sync(fd, vm, bb_handle, 0, bb_offset, bb_size);
+
+ exec.exec_queue_id = engine;
+ exec.address = bb_offset;
+ sync.handle = syncobj;
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+
+ gem_close(fd, bb_handle);
+ put_ahnd(ahnd);
+ munmap(data, bb_size);
+
+}
+
+/**
+ * SUBTEST: mem-set
+ * Description: Test validates MEM_SET command.
+ * RUN type: FULL
+ */
+
+static void igt_mem_set(int fd, uint32_t dst, size_t size, uint32_t height,
+ uint32_t fill_data, uint32_t vm, uint32_t engine)
+{
+ struct drm_xe_sync sync = {
+ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ };
+ struct {
+ uint32_t batch[12];
+ uint32_t data;
+ } *data;
+
+ uint32_t syncobj;
+ uint64_t dst_offset, ahnd;
+ uint8_t dst_mocs = intel_get_uc_mocs(fd);
+ int b;
+
+ data = xe_bo_map(fd, dst, size);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ dst_offset = intel_allocator_alloc_with_strategy(ahnd, dst, size, 0,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+
+ b = 0;
+ data->batch[b++] = MEM_SET_CMD;
+ data->batch[b++] = size - 1;
+ data->batch[b++] = height;
+ data->batch[b++] = 2 * size - 1;
+ data->batch[b++] = dst_offset;
+ data->batch[b++] = dst_offset << 32;
+ data->batch[b++] = (fill_data << 24) | dst_mocs;
+ data->batch[b++] = MI_BATCH_BUFFER_END;
+ data->batch[b++] = MI_NOOP;
+ igt_assert(b <= ARRAY_SIZE(data->batch));
+
+ syncobj = syncobj_create(fd, 0);
+ sync.handle = syncobj;
+
+ xe_vm_bind_sync(fd, vm, dst, 0, dst_offset, size);
+
+ exec.exec_queue_id = engine;
+ exec.address = dst_offset;
+ sync.handle = syncobj;
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+
+ munmap(data, size);
+ put_ahnd(ahnd);
+}
+
+static void copy_test(int fd, enum command cmd,
+ struct drm_xe_engine_class_instance *hwe)
+{
+ uint32_t src_size, dst_size;
+ uint32_t src, dst, vm, engine;
+ char c = 'a';
+ size_t bo_size = xe_get_default_alignment(fd);
+ uint32_t temp_buffer[bo_size];
+
+ src = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
+ dst = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_exec_queue_create(fd, vm, hwe, 0);
+
+ /* Fill a pattern in the buffer */
+ for (int i = 0; i < bo_size; i++) {
+ temp_buffer[i] = c++ % 16;
+ temp_buffer[i] |= (c++ % 16) << 8;
+ temp_buffer[i] |= (c++ % 16) << 16;
+ temp_buffer[i] |= (c++ % 16) << 24;
+ }
+
+ src_size = bo_size;
+ dst_size = bo_size;
+
+ switch (cmd) {
+ case MEM_COPY: /* MEM_COPY_CMD */
+ igt_mem_copy(fd,
+ src,
+ dst,
+ bo_size,
+ 1,
+ 0,
+ 0,
+ vm,
+ engine);
+ break;
+
+ case MEM_SET:
+ igt_mem_set(fd,
+ dst,
+ bo_size,
+ 1,
+ temp_buffer[0] & 0xff,
+ vm,
+ engine);
+ src_size = 1;
+ break;
+ }
+
+ igt_assert_eq(objcmp(fd, src, src_size, dst, dst_size), 0);
+ gem_close(fd, src);
+ gem_close(fd, dst);
+
+ xe_exec_queue_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("mem-set")
+ xe_for_each_hw_engine(fd, hwe)
+ copy_test(fd, MEM_SET, hwe);
+
+ igt_subtest("mem-copy")
+ xe_for_each_hw_engine(fd, hwe)
+ copy_test(fd, MEM_COPY, hwe);
+
+ igt_fixture {
+ drm_close_driver(fd);
+ }
+}
+
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for Add copy basic test to exercise blt commands
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib sai.gowtham.ch
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch
@ 2023-08-18 6:24 ` Patchwork
2023-08-18 6:41 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-08-18 6:24 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
== Series Details ==
Series: Add copy basic test to exercise blt commands
URL : https://patchwork.freedesktop.org/series/122615/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/964492 for the overview.
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47645333):
section_start:1692339331:prepare_script
Preparing environment
Running on runner-yyhtcik-project-3185-concurrent-5 via 541e14f02aa1...
section_end:1692339331:prepare_script
section_start:1692339331:get_sources
Getting source from Git repository
$ /host/bin/curl -s -L --cacert /host/ca-certificates.crt --retry 4 -f --retry-delay 60 https://gitlab.freedesktop.org/freedesktop/helm-gitlab-infra/-/raw/main/runner-gating/runner-gating.sh | sh -s -- pre_get_sources_script
Checking if the user of the pipeline is allowed...
Checking if the job's project is part of a well-known group...
Thank you for contributing to freedesktop.org
Fetching changes...
Reinitialized existing Git repository in /builds/gfx-ci/igt-ci-tags/.git/
error: RPC failed; curl 55 Failed sending data to the peer
fatal: expected 'acknowledgments'
section_end:1692339408:get_sources
section_start:1692339408:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1692339408:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/964492
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for Add copy basic test to exercise blt commands
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
` (2 preceding siblings ...)
2023-08-18 6:24 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
@ 2023-08-18 6:41 ` Patchwork
2023-08-18 6:55 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-08-19 8:56 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-08-18 6:41 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 332 bytes --]
== Series Details ==
Series: Add copy basic test to exercise blt commands
URL : https://patchwork.freedesktop.org/series/122615/
State : info
== Summary ==
Participating hosts:
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9618](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9618/index.html)
[-- Attachment #2: Type: text/html, Size: 842 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
` (3 preceding siblings ...)
2023-08-18 6:41 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
@ 2023-08-18 6:55 ` Patchwork
2023-08-19 8:56 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-08-18 6:55 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 9437 bytes --]
== Series Details ==
Series: Add copy basic test to exercise blt commands
URL : https://patchwork.freedesktop.org/series/122615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13535 -> IGTPW_9618
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (1): bat-dg2-8
Missing (2): bat-adlp-11 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9618 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-8: NOTRUN -> [INCOMPLETE][1] ([i915#8011])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_mmap@basic:
- bat-dg2-8: NOTRUN -> [SKIP][2] ([i915#4083])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#5354] / [i915#7561])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#6621])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [PASS][9] -> [DMESG-FAIL][10] ([i915#4258] / [i915#7913])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#6645])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#5190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4215] / [i915#5190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#5274])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#1845] / [i915#5354])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_psr@cursor_plane_move:
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#1072]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: NOTRUN -> [ABORT][20] ([i915#8442] / [i915#8668] / [i915#8712])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-8: NOTRUN -> [SKIP][21] ([i915#3555])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#3708])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][23] ([i915#3708] / [i915#4077]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][24] ([i915#3291] / [i915#3708]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9: [INCOMPLETE][25] ([i915#8011]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/bat-dg2-9/igt@gem_exec_suspend@basic-s0@lmem0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-dg2-9/igt@gem_exec_suspend@basic-s0@lmem0.html
#### Warnings ####
* igt@kms_psr@cursor_plane_move:
- bat-rplp-1: [ABORT][27] ([i915#8469] / [i915#8668]) -> [SKIP][28] ([i915#1072])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
[i915#8879]: https://gitlab.freedesktop.org/drm/intel/issues/8879
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7443 -> IGTPW_9618
CI-20190529: 20190529
CI_DRM_13535: d3fd5e38264df85151b6deba3df6ee80c745c9ce @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9618: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
IGT_7443: 953448dbf2e63918a8eced9707f65fc0a19a9c85 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_copy_basic@mem-copy
+igt@xe_copy_basic@mem-set
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
[-- Attachment #2: Type: text/html, Size: 10953 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch
@ 2023-08-18 13:40 ` Karolina Stolarek
2023-08-21 9:51 ` Kamil Konieczny
2023-08-21 13:29 ` Ch, Sai Gowtham
0 siblings, 2 replies; 14+ messages in thread
From: Karolina Stolarek @ 2023-08-18 13:40 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
Hi Sai,
On 18.08.2023 07:19, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> Add copy basic test to exercise copy commands like mem-copy and mem-set.
>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_copy_basic.c | 262 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 263 insertions(+)
> create mode 100644 tests/xe/xe_copy_basic.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index 58061dbc2..323c2108a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -266,6 +266,7 @@ xe_progs = [
> 'xe_ccs',
> 'xe_create',
> 'xe_compute',
> + 'xe_copy_basic',
> 'xe_dma_buf_sync',
> 'xe_debugfs',
> 'xe_evict',
> diff --git a/tests/xe/xe_copy_basic.c b/tests/xe/xe_copy_basic.c
> new file mode 100644
> index 000000000..ce1223eb1
> --- /dev/null
> +++ b/tests/xe/xe_copy_basic.c
> @@ -0,0 +1,262 @@
> +/* SPDX-License-Identifier: MIT */
Nit: this line uses formatting dedicated for header files, use // instead
> +/* > +* Copyright © 2023 Intel Corporation
Nit: Add spaces to align *s to /*
> +*
> +* Authors:
> +* Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> +*/
> +
> +#include "igt.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "lib/intel_mocs.h"
> +#include "lib/intel_reg.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/xe/xe_util.h"
> +
> +/**
> + * TEST: Test to valiudate copy commands on xe
From what I understand, the TEST field is just the name of the specific
test, the rest should go to Description. Also, s/valiudate/validate/
> + * Category: Software building block
> + * Sub-category: Copy
> + * Functionality: blitter
> + * Test category: functionality test
> + */
> +
> +enum command {
> + MEM_COPY,
> + MEM_SET,
> +};
> +
> +static int objcmp(int fd, uint32_t src, uint32_t dst,
> + uint32_t src_size, uint32_t dst_size)
^-- misaligned line
> +{
> + void *buf_src, *buf_dst;
> + int ret = 0;
> +
> + buf_src = xe_bo_map(fd, src, src_size);
> + buf_dst = xe_bo_map(fd, dst, dst_size);
> +
> + ret = memcmp(buf_src, buf_dst , src_size);
Whoops, an extra space before ","
> +
> + munmap(buf_src, src_size);
> + munmap(buf_dst, dst_size);
> +
> + return ret;
> +}
> +
> +/**
> + * SUBTEST: mem-copy
> + * Description: Test validates MEM_COPY command, it takes various
> + * parameters needed for the filling batch buffer for MEM_COPY command.
> + * Run type: FULL
> + */
> +
I _think_ that an empty line before this and the other doc is not
needed, but I'd need to double-check in other tests.
> +static void
> +igt_mem_copy(int fd, uint32_t src, uint32_t dst,
> + uint32_t size, uint32_t col_size, uint32_t src_pitch,
Nit: misaligned line that uses spaces instead of tabs, could you correct
it in the next version?
Also, I have a question about src_pitch and dst_pitch arguments -- is
there a test case where they are different from 0? If not, could we drop
them from the arguments list?
> + uint32_t dst_pitch, uint32_t vm, uint32_t engine)
> +{
> + struct drm_xe_sync sync = {
> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&sync),
> + };
> +
> + uint32_t bb_handle, syncobj;
> + struct {
> + uint32_t batch[12];
> + uint32_t data;
> + } *data;
> +
> + uint64_t bb_offset, src_offset, dst_offset;
> + uint64_t alignment;
> + uint8_t src_mocs = intel_get_uc_mocs(fd);
> + uint64_t bb_size = xe_get_default_alignment(fd);
> + uint8_t dst_mocs = src_mocs;
> + uint64_t ahnd;
> + int i;
> +
> + alignment = xe_get_default_alignment(fd);
> +
> + bb_handle = xe_bo_create_flags(fd, 0, bb_size, visible_vram_if_possible(fd, 0));
> + data = xe_bo_map(fd, bb_handle, bb_size);
> +
> + ahnd = intel_allocator_open_full(fd, vm, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
Slightly misaligned, from what I can see. You can check these with
scripts/checkpatch.pl from the kernel repo.
> + src_offset = get_offset(ahnd, src, size, alignment);
> + dst_offset = get_offset(ahnd, dst, size, alignment);
> + bb_offset = get_offset(ahnd, bb_handle, bb_size, alignment);
> +
> + i = 0;
> + data->batch[i++] = MEM_COPY_CMD;
> + data->batch[i++] = size - 1;
> + data->batch[i++] = col_size - 1;
> + data->batch[i++] = src_pitch;
> + data->batch[i++] = dst_pitch;
> + data->batch[i++] = src_offset;
> + data->batch[i++] = src_offset << 32;
> + data->batch[i++] = dst_offset;
> + data->batch[i++] = dst_offset << 32;
> + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
> + data->batch[i++] = MI_BATCH_BUFFER_END;
> + data->batch[i++] = MI_NOOP;
I see that in both batches we use MI_NOOP -- is there a reason for doing
that?
> +
> + syncobj = syncobj_create(fd, 0);
> + sync.handle = syncobj;
> +
> + xe_vm_bind_sync(fd, vm, bb_handle, 0, bb_offset, bb_size);
> +
> + exec.exec_queue_id = engine;
> + exec.address = bb_offset;
> + sync.handle = syncobj;
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> +
> + gem_close(fd, bb_handle);
> + put_ahnd(ahnd);
> + munmap(data, bb_size);
> +
^--- extra empty line, it would be good to delete it
Also, that's the comment that applies both to mem_copy and mem_set --
shouldn't we call syncobj_destroy() at the end of the test?
> +}
> +
> +/**
> + * SUBTEST: mem-set
> + * Description: Test validates MEM_SET command.
> + * RUN type: FULL
> + */
> +
> +static void igt_mem_set(int fd, uint32_t dst, size_t size, uint32_t height,
> + uint32_t fill_data, uint32_t vm, uint32_t engine)
> +{
> + struct drm_xe_sync sync = {
> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&sync),
> + };
> + struct {
> + uint32_t batch[12];
> + uint32_t data;
> + } *data;
> +
> + uint32_t syncobj;
> + uint64_t dst_offset, ahnd;
> + uint8_t dst_mocs = intel_get_uc_mocs(fd);
> + int b;
> +
> + data = xe_bo_map(fd, dst, size);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
Before we had a simple allocator, why do we pick a different one in this
one?
> + dst_offset = intel_allocator_alloc_with_strategy(ahnd, dst, size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
Alignment is slightly off here
> +
> + b = 0;
> + data->batch[b++] = MEM_SET_CMD;
> + data->batch[b++] = size - 1;
> + data->batch[b++] = height;
> + data->batch[b++] = 2 * size - 1;
From what I understand, this filed is ignored for linear fill and we
have no matrix case. Do you have a plans of adding one? If not, I think
it should be fine to set it to 0, but you'd need to test my assumption.
> + data->batch[b++] = dst_offset;
> + data->batch[b++] = dst_offset << 32;
> + data->batch[b++] = (fill_data << 24) | dst_mocs;
> + data->batch[b++] = MI_BATCH_BUFFER_END;
> + data->batch[b++] = MI_NOOP;
> + igt_assert(b <= ARRAY_SIZE(data->batch));
> +
> + syncobj = syncobj_create(fd, 0);
> + sync.handle = syncobj;
> +
> + xe_vm_bind_sync(fd, vm, dst, 0, dst_offset, size);
> +
> + exec.exec_queue_id = engine;
> + exec.address = dst_offset;
> + sync.handle = syncobj;
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> +
> + munmap(data, size);
> + put_ahnd(ahnd);
Is gem_close() call missing from here?
> +}
> +
> +static void copy_test(int fd, enum command cmd,
> + struct drm_xe_engine_class_instance *hwe)
> +{
> + uint32_t src_size, dst_size;
> + uint32_t src, dst, vm, engine;
> + char c = 'a';
> + size_t bo_size = xe_get_default_alignment(fd);
> + uint32_t temp_buffer[bo_size];
> +
> + src = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
> + dst = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
This test only tests lmem<->lmem scenario, what about smem<->smem and
lmem<->smem?
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_exec_queue_create(fd, vm, hwe, 0);
Given the recent rename from xe_engine to xe_exec_queue, would it be
possible to rename this variable and param names to match it? Leaving
engine here is slightly confusing.
> +
> + /* Fill a pattern in the buffer */
> + for (int i = 0; i < bo_size; i++) {
> + temp_buffer[i] = c++ % 16;
> + temp_buffer[i] |= (c++ % 16) << 8;
> + temp_buffer[i] |= (c++ % 16) << 16;
> + temp_buffer[i] |= (c++ % 16) << 24;
For each byte, we're using a different value. It's more of a nit, but I
wonder if we could just increment c for each 4 byte chunk, not every byte.
> + }
> +
> + src_size = bo_size;
> + dst_size = bo_size;
> +
> + switch (cmd) {
> + case MEM_COPY: /* MEM_COPY_CMD */
> + igt_mem_copy(fd,
> + src,
> + dst,
> + bo_size,
> + 1,
> + 0,
> + 0,
> + vm,
> + engine);
> + break;
> +
> + case MEM_SET:
> + igt_mem_set(fd,
> + dst,
> + bo_size,
> + 1,
> + temp_buffer[0] & 0xff,
> + vm,
> + engine);
> + src_size = 1;
> + break;
> + }
It's more of a suggestion -- could we add comments to each argument what
it stands for? That would ease the reading process, it took some time
for me to map each value with the specific parameter.
> +
> + igt_assert_eq(objcmp(fd, src, src_size, dst, dst_size), 0);
> + gem_close(fd, src);
> + gem_close(fd, dst);
> +
> + xe_exec_queue_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
How is this test going to be run? As a part of CI or manually? If the
former, I think we should add a check to see if a specific platform
supports MEM_COPY or MEM_SET and skip if it doesn't. We could do it by
adding information on supported commands to intel_cmd_info.c and
implementing a helper to check for it, something similar to
blt_fast_copy_supports_tiling() function.
All the best,
Karolina
> + }
> +
> + igt_subtest("mem-set")
> + xe_for_each_hw_engine(fd, hwe)
> + copy_test(fd, MEM_SET, hwe);
> +
> + igt_subtest("mem-copy")
> + xe_for_each_hw_engine(fd, hwe)
> + copy_test(fd, MEM_COPY, hwe);
> +
> + igt_fixture {
> + drm_close_driver(fd);
> + }
> +}
> +
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib sai.gowtham.ch
@ 2023-08-18 13:40 ` Karolina Stolarek
0 siblings, 0 replies; 14+ messages in thread
From: Karolina Stolarek @ 2023-08-18 13:40 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
Hi Sai,
On 18.08.2023 07:19, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> Add memory copy and set commands to the lib.
>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> lib/intel_mocs.h | 2 ++
> lib/intel_reg.h | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
> index 255eac0ff..4f4cf53e0 100644
> --- a/lib/intel_mocs.h
> +++ b/lib/intel_mocs.h
> @@ -6,6 +6,8 @@
> #ifndef _INTEL_MOCS_H
> #define _INTEL_MOCS_H
>
> +#define MEM_COPY_MOCS_SHIFT 25
> +
From what I can see, this flag is only used in the xe_copy_basic test.
Would it be possible to keep it local for the time being?
Many thanks,
Karolina
> uint8_t intel_get_wb_mocs(int fd);
> uint8_t intel_get_uc_mocs(int fd);
>
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index 3bf3676dc..322aec9fd 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2564,6 +2564,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>
> #define XY_FAST_COLOR_BLT ((0x2<<29)|(0x44<<22)|0xe)
>
> +/* RAW memory commands */
> +#define MEM_COPY_CMD ((0x2 << 29)|(0x5a << 22)|0x8)
> +#define MEM_SET_CMD ((0x2 << 29)|(0x5b << 22)|0x5)
> +
> #define XY_FAST_COPY_BLT ((2<<29)|(0x42<<22)|0x8)
> /* dword 0 */
> #define XY_FAST_COPY_SRC_TILING_LINEAR (0 << 20)
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add copy basic test to exercise blt commands
2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
` (4 preceding siblings ...)
2023-08-18 6:55 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-08-19 8:56 ` Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-08-19 8:56 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 85115 bytes --]
== Series Details ==
Series: Add copy basic test to exercise blt commands
URL : https://patchwork.freedesktop.org/series/122615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13535_full -> IGTPW_9618_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_9618_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9618_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9618_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
* igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html
Known issues
------------
Here are the changes found in IGTPW_9618_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +20 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@busy@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414]) +5 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@drm_fdinfo@busy@vcs0.html
* igt@drm_fdinfo@virtual-busy:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-17/igt@drm_fdinfo@virtual-busy.html
* igt@drm_mm@drm_mm_test:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#8661])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb4/igt@drm_mm@drm_mm_test.html
* igt@feature_discovery@display-3x:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#1839])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-17/igt@feature_discovery@display-3x.html
* igt@feature_discovery@display-4x:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#1839])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@feature_discovery@display-4x.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8562])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@gem_create@create-ext-set-pat.html
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#8562])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-mtlp: [PASS][11] -> [FAIL][12] ([i915#6121])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-2/igt@gem_ctx_exec@basic-nohangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-snb: NOTRUN -> [DMESG-WARN][13] ([i915#8841]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb1/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#8555]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#5882]) +9 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@gem_ctx_sseu@engines.html
- shard-tglu: NOTRUN -> [SKIP][18] ([i915#280])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-10/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#280])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@hibernate:
- shard-dg2: [PASS][20] -> [ABORT][21] ([i915#7975] / [i915#8213])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-11/igt@gem_eio@hibernate.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@hog:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#4812])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_exec_balancer@hog.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#6334]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_fair@basic-deadline:
- shard-dg1: NOTRUN -> [SKIP][24] ([i915#3539] / [i915#4852])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#2846])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#3539])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][28] -> [FAIL][29] ([i915#2842])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@submit67:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) +5 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#3281]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3281]) +7 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@gem_exec_reloc@basic-wc.html
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#3281])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][35] ([i915#3281]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_schedule@preempt-engines@ccs0:
- shard-mtlp: [PASS][36] -> [FAIL][37] ([i915#9119]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-6/igt@gem_exec_schedule@preempt-engines@ccs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@ccs0.html
* igt@gem_exec_schedule@preempt-engines@rcs0:
- shard-mtlp: [PASS][38] -> [DMESG-FAIL][39] ([i915#8962] / [i915#9121])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-6/igt@gem_exec_schedule@preempt-engines@rcs0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@rcs0.html
* igt@gem_exec_schedule@semaphore-power:
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4812])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-2/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg1: [PASS][41] -> [ABORT][42] ([i915#7975] / [i915#8213])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-18/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_fence_thrash@bo-copy:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4860]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@gem_fence_thrash@bo-copy.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-tglu: NOTRUN -> [SKIP][44] ([i915#4613])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-7/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-random:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4613])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#4565])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4613]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: NOTRUN -> [TIMEOUT][48] ([i915#5493])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [PASS][49] -> [TIMEOUT][50] ([i915#5493])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_fill@media-fill:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#8289])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@gem_media_fill@media-fill.html
* igt@gem_mmap@big-bo:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#4083])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_mmap@big-bo.html
* igt@gem_mmap_wc@coherency:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4083])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-6/igt@gem_mmap_wc@coherency.html
* igt@gem_mmap_wc@write-wc-read-gtt:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#4083]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@gem_mmap_wc@write-wc-read-gtt.html
* igt@gem_pread@exhaustion:
- shard-tglu: NOTRUN -> [WARN][55] ([i915#2658])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-random:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3282]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@gem_pwrite@basic-random.html
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3282]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#4270]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4270]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_readwrite@write-bad-handle:
- shard-snb: [PASS][60] -> [ABORT][61] ([i915#8865])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-snb7/igt@gem_readwrite@write-bad-handle.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb7/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#8428])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#4079])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#8411]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_tiling_max_stride:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#4077]) +17 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@gem_tiling_max_stride.html
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#4077]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_tiling_max_stride.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#3297]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#3297])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-rkl: NOTRUN -> [FAIL][69] ([i915#3318])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@gem_userptr_blits@vma-merge.html
- shard-tglu: NOTRUN -> [FAIL][70] ([i915#3318])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_mixed_blits:
- shard-rkl: NOTRUN -> [SKIP][71] ([fdo#109289]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@gen3_mixed_blits.html
* igt@gen7_exec_parse@basic-offset:
- shard-dg2: NOTRUN -> [SKIP][72] ([fdo#109289]) +8 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@gen7_exec_parse@basic-offset.html
- shard-dg1: NOTRUN -> [SKIP][73] ([fdo#109289]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-snb: NOTRUN -> [SKIP][74] ([fdo#109271]) +177 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb2/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@bb-large:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#2856])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#2527])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@gen9_exec_parse@secure-batches.html
* igt@gen9_exec_parse@unaligned-access:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#2527])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@gen9_exec_parse@unaligned-access.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#2856]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][79] ([i915#4881])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@i915_fb_tiling.html
* igt@i915_hangman@detector@vcs0:
- shard-mtlp: NOTRUN -> [FAIL][80] ([i915#8456]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@i915_hangman@detector@vcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][81] -> [DMESG-WARN][82] ([i915#7061] / [i915#8617])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [PASS][83] -> [ABORT][84] ([i915#8489] / [i915#8668])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [PASS][85] -> [FAIL][86] ([i915#8691])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-6/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_dc@dc6-dpms:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#5978])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@i915_pm_dc@dc6-dpms.html
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#3361])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-mtlp: [PASS][89] -> [SKIP][90] ([i915#8403])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-7/igt@i915_pm_rc6_residency@rc6-accuracy.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-7/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglu: [PASS][91] -> [WARN][92] ([i915#2681])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-fence.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-dg1: [PASS][93] -> [FAIL][94] ([i915#3591]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-dg1: [PASS][95] -> [SKIP][96] ([i915#1397])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][97] -> [SKIP][98] ([i915#1397])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-11/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: [PASS][99] -> [SKIP][100] ([i915#1397])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#1397])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@pc8-residency:
- shard-dg2: NOTRUN -> [SKIP][102] ([fdo#109506])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#4387])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@i915_pm_sseu@full-enable.html
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#4387])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-unsupported:
- shard-rkl: NOTRUN -> [SKIP][105] ([fdo#109302])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@i915_query@query-topology-unsupported.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#8502]) +3 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-dp-2-4-mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#8502] / [i915#8709]) +11 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-dp-2-4-mc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#8502]) +7 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][109] ([i915#8247]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@crc@pipe-b-dp-2:
- shard-dg2: NOTRUN -> [FAIL][110] ([i915#8247]) +3 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_async_flips@crc@pipe-b-dp-2.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][111] ([i915#8247]) +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-snb: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#1769])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#5286]) +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][114] ([fdo#111614])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-6/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][115] -> [FAIL][116] ([i915#3743])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#4538] / [i915#5286]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][118] ([fdo#111615] / [i915#5286])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180:
- shard-mtlp: [PASS][119] -> [DMESG-WARN][120] ([i915#1982])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][121] ([fdo#111614] / [i915#3638])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
- shard-tglu: NOTRUN -> [SKIP][122] ([fdo#111614])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-10/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][123] ([fdo#111614]) +4 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#5190]) +9 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-mtlp: NOTRUN -> [SKIP][125] ([fdo#111615])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#4538])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][127] ([fdo#111615])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-2/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#4538] / [i915#5190]) +5 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-rkl: NOTRUN -> [SKIP][129] ([fdo#110723]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#2705])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_big_joiner@invalid-modeset.html
- shard-dg1: NOTRUN -> [SKIP][131] ([i915#2705])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-17/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][132] ([i915#5354] / [i915#6095]) +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-3/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#5354] / [i915#6095]) +6 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#5354]) +49 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][135] ([fdo#109271] / [i915#3886]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-apl6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#6095]) +3 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#3886] / [i915#5354] / [i915#6095])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#3734] / [i915#5354] / [i915#6095])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#3886] / [i915#6095])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#5354]) +11 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#3689] / [i915#3886] / [i915#5354]) +8 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][142] ([fdo#109271]) +31 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-apl2/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][143] ([i915#3689] / [i915#5354] / [i915#6095]) +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-9/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#5354] / [i915#6095]) +1 similar issue
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#3689] / [i915#5354]) +25 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs.html
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#3689] / [i915#5354] / [i915#6095]) +6 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][147] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-8/igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-rkl: NOTRUN -> [SKIP][148] ([fdo#111827])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_chamelium_color@ctm-blue-to-red.html
- shard-tglu: NOTRUN -> [SKIP][149] ([fdo#111827])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-dg2: NOTRUN -> [SKIP][150] ([fdo#111827]) +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-mtlp: NOTRUN -> [SKIP][151] ([fdo#111827])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#7828]) +10 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#7828])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-2/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#7828]) +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#7828]) +2 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_chamelium_hpd@vga-hpd-fast.html
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#7828]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-7/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#7118]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#3299]) +1 similar issue
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#7118] / [i915#7162])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#3555]) +1 similar issue
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][161] ([i915#3359])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#3359])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-10/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#3359])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#3359])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3359])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-7/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#3555])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#3546]) +2 similar issues
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-rkl: NOTRUN -> [SKIP][168] ([fdo#111825])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-dg2: NOTRUN -> [SKIP][169] ([fdo#109274] / [i915#5354]) +2 similar issues
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-rkl: NOTRUN -> [SKIP][170] ([fdo#111767] / [fdo#111825])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-tglu: NOTRUN -> [SKIP][171] ([fdo#109274] / [fdo#111767])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-10/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][172] -> [FAIL][173] ([i915#2346])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][174] -> [FAIL][175] ([i915#2346])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][176] ([i915#4103])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-tglu: NOTRUN -> [SKIP][177] ([i915#3555])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#3804])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#1257])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][180] ([fdo#109274] / [fdo#111767])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-snb: NOTRUN -> [SKIP][181] ([fdo#109271] / [fdo#111767])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-snb2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#8381]) +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_flip@2x-flip-vs-fences-interruptible.html
- shard-dg1: NOTRUN -> [SKIP][183] ([i915#8381])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][184] ([fdo#109274]) +5 similar issues
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#2672])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][186] ([i915#2587] / [i915#2672])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][187] ([i915#2672])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][188] ([i915#2587] / [i915#2672])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#2672]) +2 similar issues
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][190] ([fdo#111825]) +6 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#8708]) +5 similar issues
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#3458]) +1 similar issue
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][193] ([fdo#111825] / [i915#1825]) +12 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#8708]) +24 similar issues
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][195] ([i915#8708]) +1 similar issue
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#1825]) +5 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][197] ([fdo#110189]) +5 similar issues
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#3458]) +14 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][199] ([fdo#109280]) +6 similar issues
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#3023]) +7 similar issues
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#8228]) +1 similar issue
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#3555] / [i915#8228]) +1 similar issue
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglu: NOTRUN -> [SKIP][203] ([i915#3555] / [i915#8228])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-2/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#6301])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-4:
- shard-dg2: NOTRUN -> [FAIL][205] ([fdo#103375])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-4.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
- shard-mtlp: [PASS][206] -> [FAIL][207] ([i915#1623])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-3/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#6953])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][209] ([i915#8292])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#5176]) +11 similar issues
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#5176]) +5 similar issues
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#5176]) +15 similar issues
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-17/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#5235]) +7 similar issues
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#5235]) +23 similar issues
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#5235]) +7 similar issues
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][216] ([i915#5235]) +7 similar issues
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: NOTRUN -> [SKIP][217] ([i915#658]) +1 similar issue
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2: NOTRUN -> [SKIP][218] ([i915#658]) +1 similar issue
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#1072]) +2 similar issues
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#1072])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][221] ([i915#1072]) +6 similar issues
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][222] ([i915#5289])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-rkl: [PASS][223] -> [ABORT][224] ([i915#7461])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-4/igt@kms_rotation_crc@primary-rotation-270.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#4235])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-mtlp: NOTRUN -> [SKIP][226] ([i915#5289])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#4235] / [i915#5190])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_selftest@drm_plane:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#8661]) +1 similar issue
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_selftest@drm_plane.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][229] ([i915#3555] / [i915#4098]) +1 similar issue
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-tglu: NOTRUN -> [SKIP][230] ([i915#8623])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-6/igt@kms_tiled_display@basic-test-pattern.html
- shard-rkl: NOTRUN -> [SKIP][231] ([i915#8623])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][232] ([fdo#109309])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@kms_tv_load_detect@load-detect.html
- shard-dg1: NOTRUN -> [SKIP][233] ([fdo#109309])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_tv_load_detect@load-detect.html
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-rkl: NOTRUN -> [SKIP][234] ([i915#4070] / [i915#6768]) +4 similar issues
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-c-functional.html
* igt@kms_vblank@pipe-d-query-busy:
- shard-rkl: NOTRUN -> [SKIP][235] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@kms_vblank@pipe-d-query-busy.html
* igt@kms_vrr@negative-basic:
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#3555]) +6 similar issues
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@kms_vrr@negative-basic.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglu: NOTRUN -> [SKIP][237] ([i915#2437])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-8/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][238] ([i915#2437])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_writeback@writeback-invalid-parameters.html
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#2437])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@mi-rpc:
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#2434])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@perf@mi-rpc.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][241] -> [FAIL][242] ([i915#9100])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-rkl: NOTRUN -> [SKIP][243] ([i915#8850])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@perf_pmu@cpu-hotplug.html
- shard-tglu: NOTRUN -> [SKIP][244] ([i915#8850])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-9/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@event-wait@rcs0:
- shard-dg2: NOTRUN -> [SKIP][245] ([fdo#112283])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@rc6@runtime-pm-long-gt1:
- shard-mtlp: [PASS][246] -> [SKIP][247] ([i915#8537]) +2 similar issues
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-4/igt@perf_pmu@rc6@runtime-pm-long-gt1.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-2/igt@perf_pmu@rc6@runtime-pm-long-gt1.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#3708])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@prime_vgem@basic-fence-flip.html
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#3708])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][250] ([i915#3291] / [i915#3708]) +1 similar issue
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-1/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#3708] / [i915#4077])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-2/igt@prime_vgem@basic-gtt.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#4818])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_get_param@get-bad-param:
- shard-dg1: NOTRUN -> [SKIP][253] ([i915#2575]) +2 similar issues
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@v3d/v3d_get_param@get-bad-param.html
* igt@v3d/v3d_job_submission@array-job-submission:
- shard-rkl: NOTRUN -> [SKIP][254] ([fdo#109315]) +2 similar issues
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-3/igt@v3d/v3d_job_submission@array-job-submission.html
* igt@v3d/v3d_perfmon@get-values-invalid-pointer:
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#2575]) +2 similar issues
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html
* igt@v3d/v3d_submit_cl@bad-extension:
- shard-tglu: NOTRUN -> [SKIP][256] ([fdo#109315] / [i915#2575])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-7/igt@v3d/v3d_submit_cl@bad-extension.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#2575]) +12 similar issues
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-10/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@vc4/vc4_create_bo@create-bo-0:
- shard-mtlp: NOTRUN -> [SKIP][258] ([i915#7711]) +1 similar issue
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@vc4/vc4_create_bo@create-bo-0.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg2: NOTRUN -> [SKIP][259] ([i915#7711]) +8 similar issues
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-6/igt@vc4/vc4_label_bo@set-kernel-name.html
- shard-dg1: NOTRUN -> [SKIP][260] ([i915#7711])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_tiling@get-after-free:
- shard-tglu: NOTRUN -> [SKIP][261] ([i915#2575])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-10/igt@vc4/vc4_tiling@get-after-free.html
* igt@vc4/vc4_tiling@get-bad-handle:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#7711]) +2 similar issues
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-4/igt@vc4/vc4_tiling@get-bad-handle.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: [FAIL][263] ([i915#7742]) -> [PASS][264]
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_busy@close-race:
- shard-mtlp: [ABORT][265] ([i915#9151]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-3/igt@gem_busy@close-race.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-8/igt@gem_busy@close-race.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][267] ([i915#6268]) -> [PASS][268]
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-hang@vcs0:
- shard-mtlp: [FAIL][269] ([i915#2410]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-7/igt@gem_ctx_persistence@engines-hang@vcs0.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-7/igt@gem_ctx_persistence@engines-hang@vcs0.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: [FAIL][271] ([i915#5784]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-17/igt@gem_eio@unwedge-stress.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-19/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@vcs0:
- shard-mtlp: [FAIL][273] ([i915#4475]) -> [PASS][274]
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-1/igt@gem_exec_capture@pi@vcs0.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-6/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][275] ([i915#2842]) -> [PASS][276]
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [FAIL][277] ([i915#2842]) -> [PASS][278]
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-mtlp: [DMESG-FAIL][279] ([i915#8962] / [i915#9121]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: [ABORT][281] ([i915#7975] / [i915#8213]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [ABORT][283] ([i915#5566]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-apl4/igt@gen9_exec_parse@allowed-single.html
* igt@i915_hangman@gt-engine-hang@vcs0:
- shard-mtlp: [FAIL][285] ([i915#7069]) -> [PASS][286]
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-3/igt@i915_hangman@gt-engine-hang@vcs0.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@i915_hangman@gt-engine-hang@vcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [SKIP][287] ([fdo#109271]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-apl3/igt@i915_pm_dc@dc9-dpms.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-apl3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: [SKIP][289] ([i915#1937]) -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][291] ([i915#1397]) -> [PASS][292] +2 similar issues
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-1/igt@i915_pm_rpm@dpms-non-lpsp.html
- shard-dg1: [SKIP][293] ([i915#1397]) -> [PASS][294] +1 similar issue
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@system-suspend-devices:
- shard-dg1: [DMESG-WARN][295] ([i915#4423]) -> [PASS][296]
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-18/igt@i915_pm_rpm@system-suspend-devices.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@i915_pm_rpm@system-suspend-devices.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-mtlp: [FAIL][297] ([i915#2521]) -> [PASS][298] +1 similar issue
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][299] ([i915#5138]) -> [PASS][300] +1 similar issue
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: [FAIL][301] ([i915#3743]) -> [PASS][302] +1 similar issue
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
- shard-dg2: [FAIL][303] ([i915#6880]) -> [PASS][304] +1 similar issue
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
* igt@kms_psr@psr2_cursor_blt:
- shard-mtlp: [DMESG-WARN][305] ([i915#2017]) -> [PASS][306]
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-3/igt@kms_psr@psr2_cursor_blt.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-1/igt@kms_psr@psr2_cursor_blt.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-mtlp: [FAIL][307] ([i915#8332]) -> [PASS][308]
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-7/igt@sysfs_heartbeat_interval@precise@vecs0.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-5/igt@sysfs_heartbeat_interval@precise@vecs0.html
#### Warnings ####
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: [SKIP][309] ([i915#4423] / [i915#4565]) -> [SKIP][310] ([i915#4565])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-18/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-14/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglu: [WARN][311] ([i915#2681]) -> [FAIL][312] ([i915#2681] / [i915#3591])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-tglu-6/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][313] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][314] ([i915#8561])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-mtlp-6/igt@kms_async_flips@crc@pipe-a-edp-1.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-mtlp-1/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: [SKIP][315] ([i915#7118]) -> [SKIP][316] ([i915#7118] / [i915#7162])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-2/igt@kms_content_protection@mei_interface.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-12/igt@kms_content_protection@mei_interface.html
- shard-rkl: [SKIP][317] ([i915#7118]) -> [SKIP][318] ([fdo#109300])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-2/igt@kms_content_protection@mei_interface.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_content_protection@mei_interface.html
- shard-dg1: [SKIP][319] ([i915#7116]) -> [SKIP][320] ([fdo#109300])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-14/igt@kms_content_protection@mei_interface.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-18/igt@kms_content_protection@mei_interface.html
- shard-tglu: [SKIP][321] ([i915#6944] / [i915#7116] / [i915#7118]) -> [SKIP][322] ([fdo#109300])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-tglu-8/igt@kms_content_protection@mei_interface.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-tglu-2/igt@kms_content_protection@mei_interface.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][323] ([i915#4816]) -> [SKIP][324] ([i915#4070] / [i915#4816])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@primary_page_flip:
- shard-dg1: [SKIP][325] ([i915#1072] / [i915#4078]) -> [SKIP][326] ([i915#1072])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-16/igt@kms_psr@primary_page_flip.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-17/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- shard-dg1: [SKIP][327] ([i915#1072]) -> [SKIP][328] ([i915#1072] / [i915#4078])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg1-14/igt@kms_psr@sprite_plane_onoff.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg1-16/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][329] ([i915#7331]) -> [INCOMPLETE][330] ([i915#5493])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13535/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8332]: https://gitlab.freedesktop.org/drm/intel/issues/8332
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8403]: https://gitlab.freedesktop.org/drm/intel/issues/8403
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8456]: https://gitlab.freedesktop.org/drm/intel/issues/8456
[i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8537]: https://gitlab.freedesktop.org/drm/intel/issues/8537
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9119]: https://gitlab.freedesktop.org/drm/intel/issues/9119
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
[i915#9151]: https://gitlab.freedesktop.org/drm/intel/issues/9151
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7443 -> IGTPW_9618
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13535: d3fd5e38264df85151b6deba3df6ee80c745c9ce @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9618: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
IGT_7443: 953448dbf2e63918a8eced9707f65fc0a19a9c85 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9618/index.html
[-- Attachment #2: Type: text/html, Size: 104548 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
2023-08-18 13:40 ` Karolina Stolarek
@ 2023-08-21 9:51 ` Kamil Konieczny
2023-08-21 13:29 ` Ch, Sai Gowtham
1 sibling, 0 replies; 14+ messages in thread
From: Kamil Konieczny @ 2023-08-21 9:51 UTC (permalink / raw)
To: igt-dev; +Cc: sai.gowtham.ch
Hi Sai,
On 2023-08-18 at 15:40:18 +0200, Karolina Stolarek wrote:
> Hi Sai,
>
> On 18.08.2023 07:19, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > Add copy basic test to exercise copy commands like mem-copy and mem-set.
> >
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_copy_basic.c | 262 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 263 insertions(+)
> > create mode 100644 tests/xe/xe_copy_basic.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 58061dbc2..323c2108a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -266,6 +266,7 @@ xe_progs = [
> > 'xe_ccs',
> > 'xe_create',
> > 'xe_compute',
> > + 'xe_copy_basic',
> > 'xe_dma_buf_sync',
> > 'xe_debugfs',
> > 'xe_evict',
> > diff --git a/tests/xe/xe_copy_basic.c b/tests/xe/xe_copy_basic.c
> > new file mode 100644
> > index 000000000..ce1223eb1
> > --- /dev/null
> > +++ b/tests/xe/xe_copy_basic.c
> > @@ -0,0 +1,262 @@
> > +/* SPDX-License-Identifier: MIT */
>
> Nit: this line uses formatting dedicated for header files, use // instead
>
> > +/* > +* Copyright © 2023 Intel Corporation
>
> Nit: Add spaces to align *s to /*
>
> > +*
> > +* Authors:
> > +* Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > +*/
> > +
> > +#include "igt.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +#include "lib/intel_mocs.h"
> > +#include "lib/intel_reg.h"
> > +#include "lib/igt_syncobj.h"
> > +#include "lib/xe/xe_util.h"
Please sort headers alphabetically.
Regards,
Kamil
> > +
> > +/**
> > + * TEST: Test to valiudate copy commands on xe
>
> From what I understand, the TEST field is just the name of the specific
> test, the rest should go to Description. Also, s/valiudate/validate/
>
> > + * Category: Software building block
> > + * Sub-category: Copy
> > + * Functionality: blitter
> > + * Test category: functionality test
> > + */
> > +
> > +enum command {
> > + MEM_COPY,
> > + MEM_SET,
> > +};
> > +
> > +static int objcmp(int fd, uint32_t src, uint32_t dst,
> > + uint32_t src_size, uint32_t dst_size)
>
> ^-- misaligned line
>
> > +{
> > + void *buf_src, *buf_dst;
> > + int ret = 0;
> > +
> > + buf_src = xe_bo_map(fd, src, src_size);
> > + buf_dst = xe_bo_map(fd, dst, dst_size);
> > +
> > + ret = memcmp(buf_src, buf_dst , src_size);
>
> Whoops, an extra space before ","
>
> > +
> > + munmap(buf_src, src_size);
> > + munmap(buf_dst, dst_size);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * SUBTEST: mem-copy
> > + * Description: Test validates MEM_COPY command, it takes various
> > + * parameters needed for the filling batch buffer for MEM_COPY command.
> > + * Run type: FULL
> > + */
> > +
>
> I _think_ that an empty line before this and the other doc is not needed,
> but I'd need to double-check in other tests.
>
> > +static void
> > +igt_mem_copy(int fd, uint32_t src, uint32_t dst,
> > + uint32_t size, uint32_t col_size, uint32_t src_pitch,
>
> Nit: misaligned line that uses spaces instead of tabs, could you correct it
> in the next version?
>
> Also, I have a question about src_pitch and dst_pitch arguments -- is there
> a test case where they are different from 0? If not, could we drop them from
> the arguments list?
>
> > + uint32_t dst_pitch, uint32_t vm, uint32_t engine)
> > +{
> > + struct drm_xe_sync sync = {
> > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> > + };
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 1,
> > + .syncs = to_user_pointer(&sync),
> > + };
> > +
> > + uint32_t bb_handle, syncobj;
> > + struct {
> > + uint32_t batch[12];
> > + uint32_t data;
> > + } *data;
> > +
> > + uint64_t bb_offset, src_offset, dst_offset;
> > + uint64_t alignment;
> > + uint8_t src_mocs = intel_get_uc_mocs(fd);
> > + uint64_t bb_size = xe_get_default_alignment(fd);
> > + uint8_t dst_mocs = src_mocs;
> > + uint64_t ahnd;
> > + int i;
> > +
> > + alignment = xe_get_default_alignment(fd);
> > +
> > + bb_handle = xe_bo_create_flags(fd, 0, bb_size, visible_vram_if_possible(fd, 0));
> > + data = xe_bo_map(fd, bb_handle, bb_size);
> > +
> > + ahnd = intel_allocator_open_full(fd, vm, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> > + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>
> Slightly misaligned, from what I can see. You can check these with
> scripts/checkpatch.pl from the kernel repo.
>
> > + src_offset = get_offset(ahnd, src, size, alignment);
> > + dst_offset = get_offset(ahnd, dst, size, alignment);
> > + bb_offset = get_offset(ahnd, bb_handle, bb_size, alignment);
> > +
> > + i = 0;
> > + data->batch[i++] = MEM_COPY_CMD;
> > + data->batch[i++] = size - 1;
> > + data->batch[i++] = col_size - 1;
> > + data->batch[i++] = src_pitch;
> > + data->batch[i++] = dst_pitch;
> > + data->batch[i++] = src_offset;
> > + data->batch[i++] = src_offset << 32;
> > + data->batch[i++] = dst_offset;
> > + data->batch[i++] = dst_offset << 32;
> > + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
> > + data->batch[i++] = MI_BATCH_BUFFER_END;
> > + data->batch[i++] = MI_NOOP;
>
> I see that in both batches we use MI_NOOP -- is there a reason for doing
> that?
>
> > +
> > + syncobj = syncobj_create(fd, 0);
> > + sync.handle = syncobj;
> > +
> > + xe_vm_bind_sync(fd, vm, bb_handle, 0, bb_offset, bb_size);
> > +
> > + exec.exec_queue_id = engine;
> > + exec.address = bb_offset;
> > + sync.handle = syncobj;
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> > +
> > + gem_close(fd, bb_handle);
> > + put_ahnd(ahnd);
> > + munmap(data, bb_size);
> > +
> ^--- extra empty line, it would be good to delete it
>
> Also, that's the comment that applies both to mem_copy and mem_set --
> shouldn't we call syncobj_destroy() at the end of the test?
>
> > +}
> > +
> > +/**
> > + * SUBTEST: mem-set
> > + * Description: Test validates MEM_SET command.
> > + * RUN type: FULL
> > + */
> > +
> > +static void igt_mem_set(int fd, uint32_t dst, size_t size, uint32_t height,
> > + uint32_t fill_data, uint32_t vm, uint32_t engine)
> > +{
> > + struct drm_xe_sync sync = {
> > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> > + };
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 1,
> > + .syncs = to_user_pointer(&sync),
> > + };
> > + struct {
> > + uint32_t batch[12];
> > + uint32_t data;
> > + } *data;
> > +
> > + uint32_t syncobj;
> > + uint64_t dst_offset, ahnd;
> > + uint8_t dst_mocs = intel_get_uc_mocs(fd);
> > + int b;
> > +
> > + data = xe_bo_map(fd, dst, size);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
>
> Before we had a simple allocator, why do we pick a different one in this
> one?
>
> > + dst_offset = intel_allocator_alloc_with_strategy(ahnd, dst, size, 0,
> > + ALLOC_STRATEGY_LOW_TO_HIGH);
>
> Alignment is slightly off here
>
> > +
> > + b = 0;
> > + data->batch[b++] = MEM_SET_CMD;
> > + data->batch[b++] = size - 1;
> > + data->batch[b++] = height;
> > + data->batch[b++] = 2 * size - 1;
>
> From what I understand, this filed is ignored for linear fill and we have no
> matrix case. Do you have a plans of adding one? If not, I think it should be
> fine to set it to 0, but you'd need to test my assumption.
>
> > + data->batch[b++] = dst_offset;
> > + data->batch[b++] = dst_offset << 32;
> > + data->batch[b++] = (fill_data << 24) | dst_mocs;
> > + data->batch[b++] = MI_BATCH_BUFFER_END;
> > + data->batch[b++] = MI_NOOP;
> > + igt_assert(b <= ARRAY_SIZE(data->batch));
> > +
> > + syncobj = syncobj_create(fd, 0);
> > + sync.handle = syncobj;
> > +
> > + xe_vm_bind_sync(fd, vm, dst, 0, dst_offset, size);
> > +
> > + exec.exec_queue_id = engine;
> > + exec.address = dst_offset;
> > + sync.handle = syncobj;
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> > +
> > + munmap(data, size);
> > + put_ahnd(ahnd);
>
> Is gem_close() call missing from here?
>
> > +}
> > +
> > +static void copy_test(int fd, enum command cmd,
> > + struct drm_xe_engine_class_instance *hwe)
> > +{
> > + uint32_t src_size, dst_size;
> > + uint32_t src, dst, vm, engine;
> > + char c = 'a';
> > + size_t bo_size = xe_get_default_alignment(fd);
> > + uint32_t temp_buffer[bo_size];
> > +
> > + src = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
> > + dst = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe->gt_id));
>
> This test only tests lmem<->lmem scenario, what about smem<->smem and
> lmem<->smem?
>
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_exec_queue_create(fd, vm, hwe, 0);
>
> Given the recent rename from xe_engine to xe_exec_queue, would it be
> possible to rename this variable and param names to match it? Leaving engine
> here is slightly confusing.
>
> > +
> > + /* Fill a pattern in the buffer */
> > + for (int i = 0; i < bo_size; i++) {
> > + temp_buffer[i] = c++ % 16;
> > + temp_buffer[i] |= (c++ % 16) << 8;
> > + temp_buffer[i] |= (c++ % 16) << 16;
> > + temp_buffer[i] |= (c++ % 16) << 24;
>
> For each byte, we're using a different value. It's more of a nit, but I
> wonder if we could just increment c for each 4 byte chunk, not every byte.
>
> > + }
> > +
> > + src_size = bo_size;
> > + dst_size = bo_size;
> > +
> > + switch (cmd) {
> > + case MEM_COPY: /* MEM_COPY_CMD */
> > + igt_mem_copy(fd,
> > + src,
> > + dst,
> > + bo_size,
> > + 1,
> > + 0,
> > + 0,
> > + vm,
> > + engine);
> > + break;
> > +
> > + case MEM_SET:
> > + igt_mem_set(fd,
> > + dst,
> > + bo_size,
> > + 1,
> > + temp_buffer[0] & 0xff,
> > + vm,
> > + engine);
> > + src_size = 1;
> > + break;
> > + }
>
> It's more of a suggestion -- could we add comments to each argument what it
> stands for? That would ease the reading process, it took some time for me to
> map each value with the specific parameter.
>
> > +
> > + igt_assert_eq(objcmp(fd, src, src_size, dst, dst_size), 0);
> > + gem_close(fd, src);
> > + gem_close(fd, dst);
> > +
> > + xe_exec_queue_destroy(fd, engine);
> > + xe_vm_destroy(fd, vm);
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
>
> How is this test going to be run? As a part of CI or manually? If the
> former, I think we should add a check to see if a specific platform supports
> MEM_COPY or MEM_SET and skip if it doesn't. We could do it by adding
> information on supported commands to intel_cmd_info.c and implementing a
> helper to check for it, something similar to blt_fast_copy_supports_tiling()
> function.
>
> All the best,
> Karolina
>
> > + }
> > +
> > + igt_subtest("mem-set")
> > + xe_for_each_hw_engine(fd, hwe)
> > + copy_test(fd, MEM_SET, hwe);
> > +
> > + igt_subtest("mem-copy")
> > + xe_for_each_hw_engine(fd, hwe)
> > + copy_test(fd, MEM_COPY, hwe);
> > +
> > + igt_fixture {
> > + drm_close_driver(fd);
> > + }
> > +}
> > +
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
2023-08-18 13:40 ` Karolina Stolarek
2023-08-21 9:51 ` Kamil Konieczny
@ 2023-08-21 13:29 ` Ch, Sai Gowtham
2023-08-22 8:14 ` Karolina Stolarek
1 sibling, 1 reply; 14+ messages in thread
From: Ch, Sai Gowtham @ 2023-08-21 13:29 UTC (permalink / raw)
To: Stolarek, Karolina; +Cc: igt-dev@lists.freedesktop.org
>-----Original Message-----
>From: Stolarek, Karolina <karolina.stolarek@intel.com>
>Sent: Friday, August 18, 2023 7:10 PM
>To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>Cc: igt-dev@lists.freedesktop.org
>Subject: Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic
>test to exercise blt commands
>
>Hi Sai,
>
>On 18.08.2023 07:19, sai.gowtham.ch@intel.com wrote:
>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>
>> Add copy basic test to exercise copy commands like mem-copy and mem-
>set.
>>
>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> ---
>> tests/meson.build | 1 +
>> tests/xe/xe_copy_basic.c | 262
>+++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 263 insertions(+)
>> create mode 100644 tests/xe/xe_copy_basic.c
>>
>> diff --git a/tests/meson.build b/tests/meson.build index
>> 58061dbc2..323c2108a 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -266,6 +266,7 @@ xe_progs = [
>> 'xe_ccs',
>> 'xe_create',
>> 'xe_compute',
>> + 'xe_copy_basic',
>> 'xe_dma_buf_sync',
>> 'xe_debugfs',
>> 'xe_evict',
>> diff --git a/tests/xe/xe_copy_basic.c b/tests/xe/xe_copy_basic.c new
>> file mode 100644 index 000000000..ce1223eb1
>> --- /dev/null
>> +++ b/tests/xe/xe_copy_basic.c
>> @@ -0,0 +1,262 @@
>> +/* SPDX-License-Identifier: MIT */
>
>Nit: this line uses formatting dedicated for header files, use // instead
>
>> +/* > +* Copyright © 2023 Intel Corporation
>
>Nit: Add spaces to align *s to /*
>
>> +*
>> +* Authors:
>> +* Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> +*/
>> +
>> +#include "igt.h"
>> +#include "xe_drm.h"
>> +#include "xe/xe_ioctl.h"
>> +#include "xe/xe_query.h"
>> +#include "lib/intel_mocs.h"
>> +#include "lib/intel_reg.h"
>> +#include "lib/igt_syncobj.h"
>> +#include "lib/xe/xe_util.h"
>> +
>> +/**
>> + * TEST: Test to valiudate copy commands on xe
>
> From what I understand, the TEST field is just the name of the specific test,
>the rest should go to Description. Also, s/valiudate/validate/
I think we are following the same for tests we have.
My bad Will change the Validate spell in next version.
>
>> + * Category: Software building block
>> + * Sub-category: Copy
>> + * Functionality: blitter
>> + * Test category: functionality test
>> + */
>> +
>> +enum command {
>> + MEM_COPY,
>> + MEM_SET,
>> +};
>> +
>> +static int objcmp(int fd, uint32_t src, uint32_t dst,
>> + uint32_t src_size, uint32_t dst_size)
>
> ^-- misaligned line
>
>> +{
>> + void *buf_src, *buf_dst;
>> + int ret = 0;
>> +
>> + buf_src = xe_bo_map(fd, src, src_size);
>> + buf_dst = xe_bo_map(fd, dst, dst_size);
>> +
>> + ret = memcmp(buf_src, buf_dst , src_size);
>
>Whoops, an extra space before ","
>
>> +
>> + munmap(buf_src, src_size);
>> + munmap(buf_dst, dst_size);
>> +
>> + return ret;
>> +}
>> +
>> +/**
>> + * SUBTEST: mem-copy
>> + * Description: Test validates MEM_COPY command, it takes various
>> + * parameters needed for the filling batch buffer for MEM_COPY
>command.
>> + * Run type: FULL
>> + */
>> +
>
>I _think_ that an empty line before this and the other doc is not needed, but
>I'd need to double-check in other tests.
>
>> +static void
>> +igt_mem_copy(int fd, uint32_t src, uint32_t dst,
>> + uint32_t size, uint32_t col_size, uint32_t src_pitch,
>
>Nit: misaligned line that uses spaces instead of tabs, could you correct it in
>the next version?
>
>Also, I have a question about src_pitch and dst_pitch arguments -- is there a
>test case where they are different from 0? If not, could we drop them from
>the arguments list?
We can change it to 0, however intention of having this is to understand bb better.
Will add comments and make them 0.
>
>> + uint32_t dst_pitch, uint32_t vm, uint32_t engine) {
>> + struct drm_xe_sync sync = {
>> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
>> + };
>> + struct drm_xe_exec exec = {
>> + .num_batch_buffer = 1,
>> + .num_syncs = 1,
>> + .syncs = to_user_pointer(&sync),
>> + };
>> +
>> + uint32_t bb_handle, syncobj;
>> + struct {
>> + uint32_t batch[12];
>> + uint32_t data;
>> + } *data;
>> +
>> + uint64_t bb_offset, src_offset, dst_offset;
>> + uint64_t alignment;
>> + uint8_t src_mocs = intel_get_uc_mocs(fd);
>> + uint64_t bb_size = xe_get_default_alignment(fd);
>> + uint8_t dst_mocs = src_mocs;
>> + uint64_t ahnd;
>> + int i;
>> +
>> + alignment = xe_get_default_alignment(fd);
>> +
>> + bb_handle = xe_bo_create_flags(fd, 0, bb_size,
>visible_vram_if_possible(fd, 0));
>> + data = xe_bo_map(fd, bb_handle, bb_size);
>> +
>> + ahnd = intel_allocator_open_full(fd, vm, 0, 0,
>INTEL_ALLOCATOR_SIMPLE,
>> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>
>Slightly misaligned, from what I can see. You can check these with
>scripts/checkpatch.pl from the kernel repo.
>
>> + src_offset = get_offset(ahnd, src, size, alignment);
>> + dst_offset = get_offset(ahnd, dst, size, alignment);
>> + bb_offset = get_offset(ahnd, bb_handle, bb_size, alignment);
>> +
>> + i = 0;
>> + data->batch[i++] = MEM_COPY_CMD;
>> + data->batch[i++] = size - 1;
>> + data->batch[i++] = col_size - 1;
>> + data->batch[i++] = src_pitch;
>> + data->batch[i++] = dst_pitch;
>> + data->batch[i++] = src_offset;
>> + data->batch[i++] = src_offset << 32;
>> + data->batch[i++] = dst_offset;
>> + data->batch[i++] = dst_offset << 32;
>> + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
>> + data->batch[i++] = MI_BATCH_BUFFER_END;
>> + data->batch[i++] = MI_NOOP;
>
>I see that in both batches we use MI_NOOP -- is there a reason for doing that?
To make sure bb is aligned, and pad out to qword boundary.
>
>> +
>> + syncobj = syncobj_create(fd, 0);
>> + sync.handle = syncobj;
>> +
>> + xe_vm_bind_sync(fd, vm, bb_handle, 0, bb_offset, bb_size);
>> +
>> + exec.exec_queue_id = engine;
>> + exec.address = bb_offset;
>> + sync.handle = syncobj;
>> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
>> +
>> + gem_close(fd, bb_handle);
>> + put_ahnd(ahnd);
>> + munmap(data, bb_size);
>> +
>^--- extra empty line, it would be good to delete it
>
>Also, that's the comment that applies both to mem_copy and mem_set --
>shouldn't we call syncobj_destroy() at the end of the test?
Missed it will fix this.
>
>> +}
>> +
>> +/**
>> + * SUBTEST: mem-set
>> + * Description: Test validates MEM_SET command.
>> + * RUN type: FULL
>> + */
>> +
>> +static void igt_mem_set(int fd, uint32_t dst, size_t size, uint32_t height,
>> + uint32_t fill_data, uint32_t vm, uint32_t engine) {
>> + struct drm_xe_sync sync = {
>> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
>> + };
>> + struct drm_xe_exec exec = {
>> + .num_batch_buffer = 1,
>> + .num_syncs = 1,
>> + .syncs = to_user_pointer(&sync),
>> + };
>> + struct {
>> + uint32_t batch[12];
>> + uint32_t data;
>> + } *data;
>> +
>> + uint32_t syncobj;
>> + uint64_t dst_offset, ahnd;
>> + uint8_t dst_mocs = intel_get_uc_mocs(fd);
>> + int b;
>> +
>> + data = xe_bo_map(fd, dst, size);
>> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
>
>Before we had a simple allocator, why do we pick a different one in this one?
Intension was to create separately in mem_copy and mem_set, However makes sense to me
Will create ahnd for src and dst in copy_test, use them accordingly.
>
>> + dst_offset = intel_allocator_alloc_with_strategy(ahnd, dst, size, 0,
>> +
> ALLOC_STRATEGY_LOW_TO_HIGH);
>
>Alignment is slightly off here
>
>> +
>> + b = 0;
>> + data->batch[b++] = MEM_SET_CMD;
>> + data->batch[b++] = size - 1;
>> + data->batch[b++] = height;
>> + data->batch[b++] = 2 * size - 1;
>
> From what I understand, this filed is ignored for linear fill and we have no
>matrix case. Do you have a plans of adding one? If not, I think it should be
>fine to set it to 0, but you'd need to test my assumption.
>
>> + data->batch[b++] = dst_offset;
>> + data->batch[b++] = dst_offset << 32;
>> + data->batch[b++] = (fill_data << 24) | dst_mocs;
>> + data->batch[b++] = MI_BATCH_BUFFER_END;
>> + data->batch[b++] = MI_NOOP;
>> + igt_assert(b <= ARRAY_SIZE(data->batch));
>> +
>> + syncobj = syncobj_create(fd, 0);
>> + sync.handle = syncobj;
>> +
>> + xe_vm_bind_sync(fd, vm, dst, 0, dst_offset, size);
>> +
>> + exec.exec_queue_id = engine;
>> + exec.address = dst_offset;
>> + sync.handle = syncobj;
>> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
>> +
>> + munmap(data, size);
>> + put_ahnd(ahnd);
>
>Is gem_close() call missing from here?
Nope it's closed in copy_test.
>
>> +}
>> +
>> +static void copy_test(int fd, enum command cmd,
>> + struct drm_xe_engine_class_instance *hwe) {
>> + uint32_t src_size, dst_size;
>> + uint32_t src, dst, vm, engine;
>> + char c = 'a';
>> + size_t bo_size = xe_get_default_alignment(fd);
>> + uint32_t temp_buffer[bo_size];
>> +
>> + src = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe-
>>gt_id));
>> + dst = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd,
>> +hwe->gt_id));
>
>This test only tests lmem<->lmem scenario, what about smem<->smem and
>lmem<->smem?
>
>> + vm = xe_vm_create(fd, 0, 0);
>> + engine = xe_exec_queue_create(fd, vm, hwe, 0);
>
>Given the recent rename from xe_engine to xe_exec_queue, would it be
>possible to rename this variable and param names to match it? Leaving
>engine here is slightly confusing.
I feel this should be easy to understand, instead of name them to queues,
However I can change them if we are following the same for rest of the tests in IGT.
>
>> +
>> + /* Fill a pattern in the buffer */
>> + for (int i = 0; i < bo_size; i++) {
>> + temp_buffer[i] = c++ % 16;
>> + temp_buffer[i] |= (c++ % 16) << 8;
>> + temp_buffer[i] |= (c++ % 16) << 16;
>> + temp_buffer[i] |= (c++ % 16) << 24;
>
>For each byte, we're using a different value. It's more of a nit, but I wonder if
>we could just increment c for each 4 byte chunk, not every byte.
Sure Will have a look.
>
>> + }
>> +
>> + src_size = bo_size;
>> + dst_size = bo_size;
>> +
>> + switch (cmd) {
>> + case MEM_COPY: /* MEM_COPY_CMD */
>> + igt_mem_copy(fd,
>> + src,
>> + dst,
>> + bo_size,
>> + 1,
>> + 0,
>> + 0,
>> + vm,
>> + engine);
>> + break;
>> +
>> + case MEM_SET:
>> + igt_mem_set(fd,
>> + dst,
>> + bo_size,
>> + 1,
>> + temp_buffer[0] & 0xff,
>> + vm,
>> + engine);
>> + src_size = 1;
>> + break;
>> + }
>
>It's more of a suggestion -- could we add comments to each argument what it
>stands for? That would ease the reading process, it took some time for me to
>map each value with the specific parameter.
Sure will do that.
>
>> +
>> + igt_assert_eq(objcmp(fd, src, src_size, dst, dst_size), 0);
>> + gem_close(fd, src);
>> + gem_close(fd, dst);
>> +
>> + xe_exec_queue_destroy(fd, engine);
>> + xe_vm_destroy(fd, vm);
>> +}
>> +
>> +igt_main
>> +{
>> + struct drm_xe_engine_class_instance *hwe;
>> + int fd;
>> +
>> + igt_fixture {
>> + fd = drm_open_driver(DRIVER_XE);
>> + xe_device_get(fd);
>
>How is this test going to be run? As a part of CI or manually? If the former, I
>think we should add a check to see if a specific platform supports MEM_COPY
>or MEM_SET and skip if it doesn't. We could do it by adding information on
>supported commands to intel_cmd_info.c and implementing a helper to
>check for it, something similar to
>blt_fast_copy_supports_tiling() function.
As per my understanding these command should work on all platforms.
>
>All the best,
>Karolina
>
>> + }
>> +
>> + igt_subtest("mem-set")
>> + xe_for_each_hw_engine(fd, hwe)
>> + copy_test(fd, MEM_SET, hwe);
>> +
>> + igt_subtest("mem-copy")
>> + xe_for_each_hw_engine(fd, hwe)
>> + copy_test(fd, MEM_COPY, hwe);
>> +
>> + igt_fixture {
>> + drm_close_driver(fd);
>> + }
>> +}
>> +
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands
2023-08-21 13:29 ` Ch, Sai Gowtham
@ 2023-08-22 8:14 ` Karolina Stolarek
0 siblings, 0 replies; 14+ messages in thread
From: Karolina Stolarek @ 2023-08-22 8:14 UTC (permalink / raw)
To: Ch, Sai Gowtham; +Cc: igt-dev@lists.freedesktop.org
Hi Sai,
On 21.08.2023 15:29, Ch, Sai Gowtham wrote:
>
>
>> -----Original Message-----
>> From: Stolarek, Karolina <karolina.stolarek@intel.com>
>> Sent: Friday, August 18, 2023 7:10 PM
>> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>> Cc: igt-dev@lists.freedesktop.org
>> Subject: Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic
>> test to exercise blt commands
>>
>> Hi Sai,
>>
>> On 18.08.2023 07:19, sai.gowtham.ch@intel.com wrote:
>>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>>
>>> Add copy basic test to exercise copy commands like mem-copy and mem-
>> set.
>>>
>>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>> ---
>>> tests/meson.build | 1 +
>>> tests/xe/xe_copy_basic.c | 262
>> +++++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 263 insertions(+)
>>> create mode 100644 tests/xe/xe_copy_basic.c
>>>
>>> diff --git a/tests/meson.build b/tests/meson.build index
>>> 58061dbc2..323c2108a 100644
>>> --- a/tests/meson.build
>>> +++ b/tests/meson.build
>>> @@ -266,6 +266,7 @@ xe_progs = [
>>> 'xe_ccs',
>>> 'xe_create',
>>> 'xe_compute',
>>> + 'xe_copy_basic',
>>> 'xe_dma_buf_sync',
>>> 'xe_debugfs',
>>> 'xe_evict',
>>> diff --git a/tests/xe/xe_copy_basic.c b/tests/xe/xe_copy_basic.c new
>>> file mode 100644 index 000000000..ce1223eb1
>>> --- /dev/null
>>> +++ b/tests/xe/xe_copy_basic.c
>>> @@ -0,0 +1,262 @@
>>> +/* SPDX-License-Identifier: MIT */
>>
>> Nit: this line uses formatting dedicated for header files, use // instead
>>
>>> +/* > +* Copyright © 2023 Intel Corporation
>>
>> Nit: Add spaces to align *s to /*
>>
>>> +*
>>> +* Authors:
>>> +* Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>> +*/
>>> +
>>> +#include "igt.h"
>>> +#include "xe_drm.h"
>>> +#include "xe/xe_ioctl.h"
>>> +#include "xe/xe_query.h"
>>> +#include "lib/intel_mocs.h"
>>> +#include "lib/intel_reg.h"
>>> +#include "lib/igt_syncobj.h"
>>> +#include "lib/xe/xe_util.h"
>>> +
>>> +/**
>>> + * TEST: Test to valiudate copy commands on xe
>>
>> From what I understand, the TEST field is just the name of the specific test,
>> the rest should go to Description. Also, s/valiudate/validate/
> I think we are following the same for tests we have.
> My bad Will change the Validate spell in next version.
Right, I'm also not too passionate about it, so you can leave the doc as
it is
>>
>>> + * Category: Software building block
>>> + * Sub-category: Copy
>>> + * Functionality: blitter
>>> + * Test category: functionality test
>>> + */
>>> +
>>> +enum command {
>>> + MEM_COPY,
>>> + MEM_SET,
>>> +};
>>> +
>>> +static int objcmp(int fd, uint32_t src, uint32_t dst,
>>> + uint32_t src_size, uint32_t dst_size)
>>
>> ^-- misaligned line
>>
>>> +{
>>> + void *buf_src, *buf_dst;
>>> + int ret = 0;
>>> +
>>> + buf_src = xe_bo_map(fd, src, src_size);
>>> + buf_dst = xe_bo_map(fd, dst, dst_size);
>>> +
>>> + ret = memcmp(buf_src, buf_dst , src_size);
>>
>> Whoops, an extra space before ","
>>
>>> +
>>> + munmap(buf_src, src_size);
>>> + munmap(buf_dst, dst_size);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +/**
>>> + * SUBTEST: mem-copy
>>> + * Description: Test validates MEM_COPY command, it takes various
>>> + * parameters needed for the filling batch buffer for MEM_COPY
>> command.
>>> + * Run type: FULL
>>> + */
>>> +
>>
>> I _think_ that an empty line before this and the other doc is not needed, but
>> I'd need to double-check in other tests.
>>
>>> +static void
>>> +igt_mem_copy(int fd, uint32_t src, uint32_t dst,
>>> + uint32_t size, uint32_t col_size, uint32_t src_pitch,
>>
>> Nit: misaligned line that uses spaces instead of tabs, could you correct it in
>> the next version?
>>
>> Also, I have a question about src_pitch and dst_pitch arguments -- is there a
>> test case where they are different from 0? If not, could we drop them from
>> the arguments list?
> We can change it to 0, however intention of having this is to understand bb better.
> Will add comments and make them 0.
Right. And thanks, comments will help here, I think
>>
>>> + uint32_t dst_pitch, uint32_t vm, uint32_t engine) {
>>> + struct drm_xe_sync sync = {
>>> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
>>> + };
>>> + struct drm_xe_exec exec = {
>>> + .num_batch_buffer = 1,
>>> + .num_syncs = 1,
>>> + .syncs = to_user_pointer(&sync),
>>> + };
>>> +
>>> + uint32_t bb_handle, syncobj;
>>> + struct {
>>> + uint32_t batch[12];
>>> + uint32_t data;
>>> + } *data;
>>> +
>>> + uint64_t bb_offset, src_offset, dst_offset;
>>> + uint64_t alignment;
>>> + uint8_t src_mocs = intel_get_uc_mocs(fd);
>>> + uint64_t bb_size = xe_get_default_alignment(fd);
>>> + uint8_t dst_mocs = src_mocs;
>>> + uint64_t ahnd;
>>> + int i;
>>> +
>>> + alignment = xe_get_default_alignment(fd);
>>> +
>>> + bb_handle = xe_bo_create_flags(fd, 0, bb_size,
>> visible_vram_if_possible(fd, 0));
>>> + data = xe_bo_map(fd, bb_handle, bb_size);
>>> +
>>> + ahnd = intel_allocator_open_full(fd, vm, 0, 0,
>> INTEL_ALLOCATOR_SIMPLE,
>>> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>>
>> Slightly misaligned, from what I can see. You can check these with
>> scripts/checkpatch.pl from the kernel repo.
>>
>>> + src_offset = get_offset(ahnd, src, size, alignment);
>>> + dst_offset = get_offset(ahnd, dst, size, alignment);
>>> + bb_offset = get_offset(ahnd, bb_handle, bb_size, alignment);
>>> +
>>> + i = 0;
>>> + data->batch[i++] = MEM_COPY_CMD;
>>> + data->batch[i++] = size - 1;
>>> + data->batch[i++] = col_size - 1;
>>> + data->batch[i++] = src_pitch;
>>> + data->batch[i++] = dst_pitch;
>>> + data->batch[i++] = src_offset;
>>> + data->batch[i++] = src_offset << 32;
>>> + data->batch[i++] = dst_offset;
>>> + data->batch[i++] = dst_offset << 32;
>>> + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
>>> + data->batch[i++] = MI_BATCH_BUFFER_END;
>>> + data->batch[i++] = MI_NOOP;
>>
>> I see that in both batches we use MI_NOOP -- is there a reason for doing that?
> To make sure bb is aligned, and pad out to qword boundary.
>>
>>> +
>>> + syncobj = syncobj_create(fd, 0);
>>> + sync.handle = syncobj;
>>> +
>>> + xe_vm_bind_sync(fd, vm, bb_handle, 0, bb_offset, bb_size);
>>> +
>>> + exec.exec_queue_id = engine;
>>> + exec.address = bb_offset;
>>> + sync.handle = syncobj;
>>> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
>>> +
>>> + gem_close(fd, bb_handle);
>>> + put_ahnd(ahnd);
>>> + munmap(data, bb_size);
>>> +
>> ^--- extra empty line, it would be good to delete it
>>
>> Also, that's the comment that applies both to mem_copy and mem_set --
>> shouldn't we call syncobj_destroy() at the end of the test?
> Missed it will fix this.
>>
>>> +}
>>> +
>>> +/**
>>> + * SUBTEST: mem-set
>>> + * Description: Test validates MEM_SET command.
>>> + * RUN type: FULL
>>> + */
>>> +
>>> +static void igt_mem_set(int fd, uint32_t dst, size_t size, uint32_t height,
>>> + uint32_t fill_data, uint32_t vm, uint32_t engine) {
>>> + struct drm_xe_sync sync = {
>>> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
>>> + };
>>> + struct drm_xe_exec exec = {
>>> + .num_batch_buffer = 1,
>>> + .num_syncs = 1,
>>> + .syncs = to_user_pointer(&sync),
>>> + };
>>> + struct {
>>> + uint32_t batch[12];
>>> + uint32_t data;
>>> + } *data;
>>> +
>>> + uint32_t syncobj;
>>> + uint64_t dst_offset, ahnd;
>>> + uint8_t dst_mocs = intel_get_uc_mocs(fd);
>>> + int b;
>>> +
>>> + data = xe_bo_map(fd, dst, size);
>>> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
>>
>> Before we had a simple allocator, why do we pick a different one in this one?
> Intension was to create separately in mem_copy and mem_set, However makes sense to me
> Will create ahnd for src and dst in copy_test, use them accordingly.
>>
>>> + dst_offset = intel_allocator_alloc_with_strategy(ahnd, dst, size, 0,
>>> +
>> ALLOC_STRATEGY_LOW_TO_HIGH);
>>
>> Alignment is slightly off here
>>
>>> +
>>> + b = 0;
>>> + data->batch[b++] = MEM_SET_CMD;
>>> + data->batch[b++] = size - 1;
>>> + data->batch[b++] = height;
>>> + data->batch[b++] = 2 * size - 1;
>>
>> From what I understand, this filed is ignored for linear fill and we have no
>> matrix case. Do you have a plans of adding one? If not, I think it should be
>> fine to set it to 0, but you'd need to test my assumption.
>>
>>> + data->batch[b++] = dst_offset;
>>> + data->batch[b++] = dst_offset << 32;
>>> + data->batch[b++] = (fill_data << 24) | dst_mocs;
>>> + data->batch[b++] = MI_BATCH_BUFFER_END;
>>> + data->batch[b++] = MI_NOOP;
>>> + igt_assert(b <= ARRAY_SIZE(data->batch));
>>> +
>>> + syncobj = syncobj_create(fd, 0);
>>> + sync.handle = syncobj;
>>> +
>>> + xe_vm_bind_sync(fd, vm, dst, 0, dst_offset, size);
>>> +
>>> + exec.exec_queue_id = engine;
>>> + exec.address = dst_offset;
>>> + sync.handle = syncobj;
>>> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
>>> +
>>> + munmap(data, size);
>>> + put_ahnd(ahnd);
>>
>> Is gem_close() call missing from here?
> Nope it's closed in copy_test.
Ah, my bad!
>>
>>> +}
>>> +
>>> +static void copy_test(int fd, enum command cmd,
>>> + struct drm_xe_engine_class_instance *hwe) {
>>> + uint32_t src_size, dst_size;
>>> + uint32_t src, dst, vm, engine;
>>> + char c = 'a';
>>> + size_t bo_size = xe_get_default_alignment(fd);
>>> + uint32_t temp_buffer[bo_size];
>>> +
>>> + src = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd, hwe-
>>> gt_id));
>>> + dst = xe_bo_create_flags(fd, 0, bo_size, visible_vram_memory(fd,
>>> +hwe->gt_id));
>>
>> This test only tests lmem<->lmem scenario, what about smem<->smem and
>> lmem<->smem?
>>
>>> + vm = xe_vm_create(fd, 0, 0);
>>> + engine = xe_exec_queue_create(fd, vm, hwe, 0);
>>
>> Given the recent rename from xe_engine to xe_exec_queue, would it be
>> possible to rename this variable and param names to match it? Leaving
>> engine here is slightly confusing.
> I feel this should be easy to understand, instead of name them to queues,
> However I can change them if we are following the same for rest of the tests in IGT.
I also reviewed a patch that does a similar rename, so I thought that it
would make sense to keep it consistent accross the codebase.
>>
>>> +
>>> + /* Fill a pattern in the buffer */
>>> + for (int i = 0; i < bo_size; i++) {
>>> + temp_buffer[i] = c++ % 16;
>>> + temp_buffer[i] |= (c++ % 16) << 8;
>>> + temp_buffer[i] |= (c++ % 16) << 16;
>>> + temp_buffer[i] |= (c++ % 16) << 24;
>>
>> For each byte, we're using a different value. It's more of a nit, but I wonder if
>> we could just increment c for each 4 byte chunk, not every byte.
> Sure Will have a look.
>>
>>> + }
>>> +
>>> + src_size = bo_size;
>>> + dst_size = bo_size;
>>> +
>>> + switch (cmd) {
>>> + case MEM_COPY: /* MEM_COPY_CMD */
>>> + igt_mem_copy(fd,
>>> + src,
>>> + dst,
>>> + bo_size,
>>> + 1,
>>> + 0,
>>> + 0,
>>> + vm,
>>> + engine);
>>> + break;
>>> +
>>> + case MEM_SET:
>>> + igt_mem_set(fd,
>>> + dst,
>>> + bo_size,
>>> + 1,
>>> + temp_buffer[0] & 0xff,
>>> + vm,
>>> + engine);
>>> + src_size = 1;
>>> + break;
>>> + }
>>
>> It's more of a suggestion -- could we add comments to each argument what it
>> stands for? That would ease the reading process, it took some time for me to
>> map each value with the specific parameter.
> Sure will do that.
>>
>>> +
>>> + igt_assert_eq(objcmp(fd, src, src_size, dst, dst_size), 0);
>>> + gem_close(fd, src);
>>> + gem_close(fd, dst);
>>> +
>>> + xe_exec_queue_destroy(fd, engine);
>>> + xe_vm_destroy(fd, vm);
>>> +}
>>> +
>>> +igt_main
>>> +{
>>> + struct drm_xe_engine_class_instance *hwe;
>>> + int fd;
>>> +
>>> + igt_fixture {
>>> + fd = drm_open_driver(DRIVER_XE);
>>> + xe_device_get(fd);
>>
>> How is this test going to be run? As a part of CI or manually? If the former, I
>> think we should add a check to see if a specific platform supports MEM_COPY
>> or MEM_SET and skip if it doesn't. We could do it by adding information on
>> supported commands to intel_cmd_info.c and implementing a helper to
>> check for it, something similar to
>> blt_fast_copy_supports_tiling() function.
> As per my understanding these command should work on all platforms.
Hmm, I just checked the documentation and it looks like only selected
platforms can handle these commands, so we'd need to skip the test for
these that don't via igt_require (similarly to what is done in
(xe|gem)_exercise_blt). But, like I said, that would add a couple of
patches if you want to use intel_cmds_info lib.
Many thanks,
Karolina
>>
>> All the best,
>> Karolina
>>
>>> + }
>>> +
>>> + igt_subtest("mem-set")
>>> + xe_for_each_hw_engine(fd, hwe)
>>> + copy_test(fd, MEM_SET, hwe);
>>> +
>>> + igt_subtest("mem-copy")
>>> + xe_for_each_hw_engine(fd, hwe)
>>> + copy_test(fd, MEM_COPY, hwe);
>>> +
>>> + igt_fixture {
>>> + drm_close_driver(fd);
>>> + }
>>> +}
>>> +
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands
@ 2023-10-03 7:33 sai.gowtham.ch
0 siblings, 0 replies; 14+ messages in thread
From: sai.gowtham.ch @ 2023-10-03 7:33 UTC (permalink / raw)
To: igt-dev, karolina.stolarek, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:
1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
intel/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_blt.c | 195 +++++++++++++++++++++++++++++++++
lib/intel_blt.h | 39 +++++++
lib/intel_reg.h | 4 +
tests/intel/xe_copy_basic.c | 208 ++++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
5 files changed, 447 insertions(+)
create mode 100644 tests/intel/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands
@ 2023-10-13 10:37 sai.gowtham.ch
0 siblings, 0 replies; 14+ messages in thread
From: sai.gowtham.ch @ 2023-10-13 10:37 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, karolina.stolarek, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:
1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
intel/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_blt.c | 199 ++++++++++++++++++++++++++++++++++++
lib/intel_blt.h | 39 +++++++
lib/intel_reg.h | 4 +
tests/intel/xe_copy_basic.c | 195 +++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
5 files changed, 438 insertions(+)
create mode 100644 tests/intel/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-10-13 10:39 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2023-08-18 5:19 [igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands sai.gowtham.ch
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_reg: Add copy commands in the lib sai.gowtham.ch
2023-08-18 13:40 ` Karolina Stolarek
2023-08-18 5:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch
2023-08-18 13:40 ` Karolina Stolarek
2023-08-21 9:51 ` Kamil Konieczny
2023-08-21 13:29 ` Ch, Sai Gowtham
2023-08-22 8:14 ` Karolina Stolarek
2023-08-18 6:24 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
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2023-08-19 8:56 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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