[PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Bommu Krishnaiah]

Introduce helper functions for object creation, binding, submission,
and destruction, applicable for SVM and other tests

xe-basic test is validating the helper function introduced in 'lib/xe/xe_util: helper function'

svm test cases:
svm-basic-malloc
svm-basic-mmap
svm-random-access
svm-huge-page
svm-atomic-access
svm-atomic-access
svm_invalid_va
svm-mprotect
svm-benchmark
svm-sparse-access

svm kernel implimentation:
https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
branch: origin/drm-xe-next-svm-unify-userptr

v2 igt patch: https://patchwork.freedesktop.org/series/133096/

Note: xe-basic test is validated without SVM. Remaining tests are not validated because the SVM driver code is still under development

Bommu Krishnaiah (10):
  lib/xe/xe_util: Introduce helper functions for buffer creation and
    command submission etc
  tests/intel/xe_svm: basic xe-basic test
  tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
  tests/intel/xe_svm: add random access test for SVM
  tests/intel/xe_svm: add huge page access test for SVM
  tests/intel/xe_svm: Add support for GPU atomic access test for svm
  tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
    functionality with invalid address access
  tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance
    with a simple benchmark
  tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality
    with read-only memory access
  tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
    accessing two memory locations with SVM

 include/drm-uapi/xe_drm.h |   1 +
 lib/xe/xe_util.c          | 214 +++++++++++++++++
 lib/xe/xe_util.h          |  40 ++++
 tests/intel/xe_svm.c      | 476 ++++++++++++++++++++++++++++++++++++++
 tests/meson.build         |   1 +
 5 files changed, 732 insertions(+)
 create mode 100644 tests/intel/xe_svm.c

-- 
2.25.1

[PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for buffer creation and command submission etc

[Bommu Krishnaiah]

Introduce helper functions for buffer creation, binding, command submission, and
destruction, applicable for SVM and other tests.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 lib/xe/xe_util.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_util.h |  33 +++++++++++
 2 files changed, 184 insertions(+)

diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 050162b5e..de848b8bc 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -10,6 +10,157 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
+#include "lib/svga/vm_basic_types.h"
+
+/**
+ * Submits a command buffer to the GPU, waits for its completion, and verifies
+ * the user fence value
+ */
+int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf)
+{
+	int64_t timeout = ONE_SEC;
+
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+			.timeline_value = USER_FENCE_VALUE,
+			.addr = xe_cmdbuf_exec_ufence_gpuva(cmdbuf),},
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+		.exec_queue_id = cmdbuf->exec_queue,
+		.address = (uint64_t)cmdbuf->gpu_addr,
+	};
+
+	xe_exec(cmdbuf->fd, &exec);
+	return __xe_wait_ufence(cmdbuf->fd, xe_cmdbuf_exec_ufence_cpuva(cmdbuf),USER_FENCE_VALUE, cmdbuf->exec_queue, &timeout);
+}
+
+/**
+ * Wrapper function to submit a command buffer and assert its successful
+ * execution.
+ */
+void xe_submit_cmd(struct xe_buffer *cmdbuf)
+{
+	int64_t ret;
+
+	ret = __xe_submit_cmd(cmdbuf);
+	igt_assert_eq(ret, 0);
+}
+
+/**
+ * Creates a buffer, maps it to both CPU and GPU address spaces, and binds it
+ * to a virtual memory (VM) space.
+ */
+void xe_create_buffer(struct xe_buffer *buffer)
+{
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+			.timeline_value = USER_FENCE_VALUE },
+	};
+
+	buffer->bind_queue = xe_bind_exec_queue_create(buffer->fd, buffer->vm, 0);
+	buffer->bind_ufence = aligned_alloc(xe_get_default_alignment(buffer->fd), PAGE_ALIGN_UFENCE);
+	sync->addr = (uint64_t)buffer->bind_ufence;
+
+	if (!buffer->is_userptr) {
+		buffer->bo = xe_bo_create(buffer->fd, 0, buffer->size, buffer->placement, buffer->flag);
+		buffer->cpu_addr = xe_bo_map(buffer->fd, buffer->bo, buffer->size);
+		xe_vm_bind_async(buffer->fd, buffer->vm, buffer->bind_queue, buffer->bo, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+	} else {
+		buffer->cpu_addr = aligned_alloc(xe_get_default_alignment(buffer->fd), buffer->size);
+		xe_vm_bind_userptr_async(buffer->fd, buffer->vm, buffer->bind_queue, to_user_pointer(buffer->cpu_addr), (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+	}
+
+	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
+}
+
+/**
+ * Destroys a buffer created by xe_create_buffer and releases associated
+ * resources.
+ */
+void xe_destroy_buffer(struct xe_buffer *buffer)
+{
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+			.timeline_value = USER_FENCE_VALUE },
+	};
+	sync->addr = (uint64_t)buffer->bind_ufence;
+
+	xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
+
+	munmap(buffer->cpu_addr, buffer->size);
+	if (!buffer->is_userptr)
+		gem_close(buffer->fd, buffer->bo);
+	else
+		free(buffer->cpu_addr);
+
+	free(buffer->bind_ufence);
+	xe_exec_queue_destroy(buffer->fd, buffer->bind_queue);
+}
+
+/**
+ * Inserts a MI_STORE_DWORD_IMM_GEN4 command into a batch buffer, which stores
+ * an immediate value to a given destination virtual address.
+ * */
+void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val)
+{
+	int i = 0;
+
+	batch[i] = MI_STORE_DWORD_IMM_GEN4;
+	batch[++i] = dst_va;
+	batch[++i] = dst_va >> 32;
+	batch[++i] = val;
+	batch[++i] = MI_BATCH_BUFFER_END;
+}
+
+/**
+ * Creates a command buffer, fills it with commands using the provided fill
+ * function, and sets up the execution queue for submission.
+ */
+void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func, uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci)
+{
+	//make some room for a exec_ufence, which will be used to sync the
+	//submission of this command....
+
+	cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size + PAGE_ALIGN_UFENCE);
+	xe_create_buffer(cmd_buf);
+	cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd, cmd_buf->vm, eci, 0);
+	fill_func(cmd_buf->cpu_addr, dst_va, val);
+}
+
+/**
+ * Destroys a command buffer created by xe_create_cmdbuf and releases
+ * associated resources.
+ */
+void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf)
+{
+	xe_exec_queue_destroy(cmd_buf->fd, cmd_buf->exec_queue);
+	xe_destroy_buffer(cmd_buf);
+}
+
+/**
+ * Returns the GPU virtual address of the execution user fence located at the
+ * end of the command buffer.
+ */
+uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf)
+{
+	/* the last 8 bytes of the cmd buffer is used as ufence */
+	return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
+}
+
+/**
+ * Returns the CPU virtual address of the execution user fence located at the
+ * end of the command buffer.
+ */
+uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf)
+{
+	/* the last 8 bytes of the cmd buffer is used as ufence */
+	return cmd_buf->cpu_addr + cmd_buf->size - 8;
+}
 
 static bool __region_belongs_to_regions_type(struct drm_xe_mem_region *region,
 					     uint32_t *mem_regions_type,
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 6480ea01a..c38f79e60 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -12,6 +12,39 @@
 #include <stdint.h>
 #include <xe_drm.h>
 
+#define USER_FENCE_VALUE        0xdeadbeefdeadbeefull
+#define ONE_SEC MS_TO_NS(1000)
+#define PAGE_ALIGN_UFENCE 4096
+
+struct xe_buffer {
+	void *cpu_addr;
+	void *gpu_addr;
+	/*the user fence used to vm bind this buffer*/
+	uint32_t *bind_ufence;
+	uint64_t size;
+	uint32_t flag;
+	uint32_t vm;
+	uint32_t bo;
+	uint32_t placement;
+	uint32_t bind_queue;
+	/*only a cmd buffer has a exec queue*/
+	uint32_t exec_queue;
+	int fd;
+	bool is_userptr;
+};
+
+typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va, uint32_t val);
+void xe_create_buffer(struct xe_buffer *buffer);
+void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
+		uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci);
+uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
+uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
+void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
+void xe_submit_cmd(struct xe_buffer *cmdbuf);
+int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
+void xe_destroy_buffer(struct xe_buffer *buffer);
+void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf);
+
 #define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
 	(xe_region_class(fd, region) == DRM_XE_MEM_REGION_CLASS_SYSMEM)
 #define XE_IS_VRAM_MEMORY_REGION(fd, region) \
-- 
2.25.1

RE: [PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for buffer creation and command submission etc

[Zeng, Oak]

See one nit-pick inline

Patch is:

Reviewed-by: Oak Zeng <oak.zeng@intel.com>

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for
> buffer creation and command submission etc
> 
> Introduce helper functions for buffer creation, binding, command submission,
> and
> destruction, applicable for SVM and other tests.
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  lib/xe/xe_util.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_util.h |  33 +++++++++++
>  2 files changed, 184 insertions(+)
> 
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index 050162b5e..de848b8bc 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -10,6 +10,157 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
> +#include "lib/svga/vm_basic_types.h"
> +
> +/**
> + * Submits a command buffer to the GPU, waits for its completion, and verifies
> + * the user fence value
> + */
> +int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf)
> +{
> +	int64_t timeout = ONE_SEC;
> +
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE,
> +			.addr = xe_cmdbuf_exec_ufence_gpuva(cmdbuf),},
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +		.exec_queue_id = cmdbuf->exec_queue,
> +		.address = (uint64_t)cmdbuf->gpu_addr,
> +	};
> +
> +	xe_exec(cmdbuf->fd, &exec);
> +	return __xe_wait_ufence(cmdbuf->fd,
> xe_cmdbuf_exec_ufence_cpuva(cmdbuf),USER_FENCE_VALUE, cmdbuf-
> >exec_queue, &timeout);
> +}
> +
> +/**
> + * Wrapper function to submit a command buffer and assert its successful
> + * execution.
> + */
> +void xe_submit_cmd(struct xe_buffer *cmdbuf)
> +{
> +	int64_t ret;
> +
> +	ret = __xe_submit_cmd(cmdbuf);
> +	igt_assert_eq(ret, 0);
> +}
> +
> +/**
> + * Creates a buffer, maps it to both CPU and GPU address spaces, and binds it
> + * to a virtual memory (VM) space.
> + */
> +void xe_create_buffer(struct xe_buffer *buffer)
> +{
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags =
> DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE },
> +	};
> +
> +	buffer->bind_queue = xe_bind_exec_queue_create(buffer->fd, buffer-
> >vm, 0);
> +	buffer->bind_ufence = aligned_alloc(xe_get_default_alignment(buffer-
> >fd), PAGE_ALIGN_UFENCE);
> +	sync->addr = (uint64_t)buffer->bind_ufence;
> +
> +	if (!buffer->is_userptr) {
> +		buffer->bo = xe_bo_create(buffer->fd, 0, buffer->size, buffer-
> >placement, buffer->flag);
> +		buffer->cpu_addr = xe_bo_map(buffer->fd, buffer->bo, buffer-
> >size);
> +		xe_vm_bind_async(buffer->fd, buffer->vm, buffer->bind_queue,
> buffer->bo, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
> +	} else {
> +		buffer->cpu_addr =
> aligned_alloc(xe_get_default_alignment(buffer->fd), buffer->size);
> +		xe_vm_bind_userptr_async(buffer->fd, buffer->vm, buffer-
> >bind_queue, to_user_pointer(buffer->cpu_addr), (uint64_t)buffer->gpu_addr,
> buffer->size, sync, 1);
> +	}
> +
> +	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence,
> USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
> +}
> +
> +/**
> + * Destroys a buffer created by xe_create_buffer and releases associated
> + * resources.
> + */
> +void xe_destroy_buffer(struct xe_buffer *buffer)
> +{
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags =
> DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE },
> +	};
> +	sync->addr = (uint64_t)buffer->bind_ufence;
> +
> +	xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0,
> (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
> +	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence,
> USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
> +
> +	munmap(buffer->cpu_addr, buffer->size);
> +	if (!buffer->is_userptr)
> +		gem_close(buffer->fd, buffer->bo);
> +	else
> +		free(buffer->cpu_addr);
> +
> +	free(buffer->bind_ufence);
> +	xe_exec_queue_destroy(buffer->fd, buffer->bind_queue);
> +}
> +
> +/**
> + * Inserts a MI_STORE_DWORD_IMM_GEN4 command into a batch buffer,
> which stores
> + * an immediate value to a given destination virtual address.
> + * */
> +void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val)
> +{
> +	int i = 0;
> +
> +	batch[i] = MI_STORE_DWORD_IMM_GEN4;
> +	batch[++i] = dst_va;
> +	batch[++i] = dst_va >> 32;
> +	batch[++i] = val;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +}
> +
> +/**
> + * Creates a command buffer, fills it with commands using the provided fill
> + * function, and sets up the execution queue for submission.
> + */
> +void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t
> fill_func, uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance
> *eci)
> +{
> +	//make some room for a exec_ufence, which will be used to sync the
> +	//submission of this command....
> +

Remove the extra blank line

Also better to use /***/ for comment

> +	cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size +
> PAGE_ALIGN_UFENCE);
> +	xe_create_buffer(cmd_buf);
> +	cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd,
> cmd_buf->vm, eci, 0);
> +	fill_func(cmd_buf->cpu_addr, dst_va, val);
> +}
> +
> +/**
> + * Destroys a command buffer created by xe_create_cmdbuf and releases
> + * associated resources.
> + */
> +void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf)
> +{
> +	xe_exec_queue_destroy(cmd_buf->fd, cmd_buf->exec_queue);
> +	xe_destroy_buffer(cmd_buf);
> +}
> +
> +/**
> + * Returns the GPU virtual address of the execution user fence located at the
> + * end of the command buffer.
> + */
> +uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf)
> +{
> +	/* the last 8 bytes of the cmd buffer is used as ufence */
> +	return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
> +}
> +
> +/**
> + * Returns the CPU virtual address of the execution user fence located at the
> + * end of the command buffer.
> + */
> +uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf)
> +{
> +	/* the last 8 bytes of the cmd buffer is used as ufence */
> +	return cmd_buf->cpu_addr + cmd_buf->size - 8;
> +}
> 
>  static bool __region_belongs_to_regions_type(struct drm_xe_mem_region
> *region,
>  					     uint32_t *mem_regions_type,
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index 6480ea01a..c38f79e60 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -12,6 +12,39 @@
>  #include <stdint.h>
>  #include <xe_drm.h>
> 
> +#define USER_FENCE_VALUE        0xdeadbeefdeadbeefull
> +#define ONE_SEC MS_TO_NS(1000)
> +#define PAGE_ALIGN_UFENCE 4096
> +
> +struct xe_buffer {
> +	void *cpu_addr;
> +	void *gpu_addr;
> +	/*the user fence used to vm bind this buffer*/
> +	uint32_t *bind_ufence;
> +	uint64_t size;
> +	uint32_t flag;
> +	uint32_t vm;
> +	uint32_t bo;
> +	uint32_t placement;
> +	uint32_t bind_queue;
> +	/*only a cmd buffer has a exec queue*/
> +	uint32_t exec_queue;
> +	int fd;
> +	bool is_userptr;
> +};
> +
> +typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va,
> uint32_t val);
> +void xe_create_buffer(struct xe_buffer *buffer);
> +void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t
> fill_func,
> +		uint64_t dst_va, uint32_t val, struct
> drm_xe_engine_class_instance *eci);
> +uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
> +uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
> +void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
> +void xe_submit_cmd(struct xe_buffer *cmdbuf);
> +int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
> +void xe_destroy_buffer(struct xe_buffer *buffer);
> +void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf);
> +
>  #define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
>  	(xe_region_class(fd, region) ==
> DRM_XE_MEM_REGION_CLASS_SYSMEM)
>  #define XE_IS_VRAM_MEMORY_REGION(fd, region) \
> --
> 2.25.1

Re: [PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for buffer creation and command submission etc

[Kamil Konieczny]

Hi Bommu,
On 2024-05-17 at 17:16:49 +0530, Bommu Krishnaiah wrote:
> Introduce helper functions for buffer creation, binding, command submission, and
> destruction, applicable for SVM and other tests.
> 

Please include here link to lore.kernel.org with reply to
your older version of this patch which explains limitations
of your approach.

> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  lib/xe/xe_util.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_util.h |  33 +++++++++++
>  2 files changed, 184 insertions(+)
> 
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index 050162b5e..de848b8bc 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -10,6 +10,157 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
> +#include "lib/svga/vm_basic_types.h"
-----------------^^^^
Why svga here? Do I miss something?

> +
> +/**
> + * Submits a command buffer to the GPU, waits for its completion, and verifies
> + * the user fence value

Description should have function name, parameters and
return value(s), see some other lib how to do it, for example
lib/igt_device.c

The same goes for all other new lib functions below.

Regards,
Kamil

> + */
> +int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf)
> +{
> +	int64_t timeout = ONE_SEC;
> +
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE,
> +			.addr = xe_cmdbuf_exec_ufence_gpuva(cmdbuf),},
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +		.exec_queue_id = cmdbuf->exec_queue,
> +		.address = (uint64_t)cmdbuf->gpu_addr,
> +	};
> +
> +	xe_exec(cmdbuf->fd, &exec);
> +	return __xe_wait_ufence(cmdbuf->fd, xe_cmdbuf_exec_ufence_cpuva(cmdbuf),USER_FENCE_VALUE, cmdbuf->exec_queue, &timeout);
> +}
> +
> +/**
> + * Wrapper function to submit a command buffer and assert its successful
> + * execution.
> + */
> +void xe_submit_cmd(struct xe_buffer *cmdbuf)
> +{
> +	int64_t ret;
> +
> +	ret = __xe_submit_cmd(cmdbuf);
> +	igt_assert_eq(ret, 0);
> +}
> +
> +/**
> + * Creates a buffer, maps it to both CPU and GPU address spaces, and binds it
> + * to a virtual memory (VM) space.
> + */
> +void xe_create_buffer(struct xe_buffer *buffer)
> +{
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE },
> +	};
> +
> +	buffer->bind_queue = xe_bind_exec_queue_create(buffer->fd, buffer->vm, 0);
> +	buffer->bind_ufence = aligned_alloc(xe_get_default_alignment(buffer->fd), PAGE_ALIGN_UFENCE);
> +	sync->addr = (uint64_t)buffer->bind_ufence;
> +
> +	if (!buffer->is_userptr) {
> +		buffer->bo = xe_bo_create(buffer->fd, 0, buffer->size, buffer->placement, buffer->flag);
> +		buffer->cpu_addr = xe_bo_map(buffer->fd, buffer->bo, buffer->size);
> +		xe_vm_bind_async(buffer->fd, buffer->vm, buffer->bind_queue, buffer->bo, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
> +	} else {
> +		buffer->cpu_addr = aligned_alloc(xe_get_default_alignment(buffer->fd), buffer->size);
> +		xe_vm_bind_userptr_async(buffer->fd, buffer->vm, buffer->bind_queue, to_user_pointer(buffer->cpu_addr), (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
> +	}
> +
> +	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
> +}
> +
> +/**
> + * Destroys a buffer created by xe_create_buffer and releases associated
> + * resources.
> + */
> +void xe_destroy_buffer(struct xe_buffer *buffer)
> +{
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.timeline_value = USER_FENCE_VALUE },
> +	};
> +	sync->addr = (uint64_t)buffer->bind_ufence;
> +
> +	xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
> +	xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
> +
> +	munmap(buffer->cpu_addr, buffer->size);
> +	if (!buffer->is_userptr)
> +		gem_close(buffer->fd, buffer->bo);
> +	else
> +		free(buffer->cpu_addr);
> +
> +	free(buffer->bind_ufence);
> +	xe_exec_queue_destroy(buffer->fd, buffer->bind_queue);
> +}
> +
> +/**
> + * Inserts a MI_STORE_DWORD_IMM_GEN4 command into a batch buffer, which stores
> + * an immediate value to a given destination virtual address.
> + * */
> +void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val)
> +{
> +	int i = 0;
> +
> +	batch[i] = MI_STORE_DWORD_IMM_GEN4;
> +	batch[++i] = dst_va;
> +	batch[++i] = dst_va >> 32;
> +	batch[++i] = val;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +}
> +
> +/**
> + * Creates a command buffer, fills it with commands using the provided fill
> + * function, and sets up the execution queue for submission.
> + */
> +void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func, uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci)
> +{
> +	//make some room for a exec_ufence, which will be used to sync the
> +	//submission of this command....
> +
> +	cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size + PAGE_ALIGN_UFENCE);
> +	xe_create_buffer(cmd_buf);
> +	cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd, cmd_buf->vm, eci, 0);
> +	fill_func(cmd_buf->cpu_addr, dst_va, val);
> +}
> +
> +/**
> + * Destroys a command buffer created by xe_create_cmdbuf and releases
> + * associated resources.
> + */
> +void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf)
> +{
> +	xe_exec_queue_destroy(cmd_buf->fd, cmd_buf->exec_queue);
> +	xe_destroy_buffer(cmd_buf);
> +}
> +
> +/**
> + * Returns the GPU virtual address of the execution user fence located at the
> + * end of the command buffer.
> + */
> +uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf)
> +{
> +	/* the last 8 bytes of the cmd buffer is used as ufence */
> +	return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
> +}
> +
> +/**
> + * Returns the CPU virtual address of the execution user fence located at the
> + * end of the command buffer.
> + */
> +uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf)
> +{
> +	/* the last 8 bytes of the cmd buffer is used as ufence */
> +	return cmd_buf->cpu_addr + cmd_buf->size - 8;
> +}
>  
>  static bool __region_belongs_to_regions_type(struct drm_xe_mem_region *region,
>  					     uint32_t *mem_regions_type,
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index 6480ea01a..c38f79e60 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -12,6 +12,39 @@
>  #include <stdint.h>
>  #include <xe_drm.h>
>  
> +#define USER_FENCE_VALUE        0xdeadbeefdeadbeefull
> +#define ONE_SEC MS_TO_NS(1000)
> +#define PAGE_ALIGN_UFENCE 4096
> +
> +struct xe_buffer {
> +	void *cpu_addr;
> +	void *gpu_addr;
> +	/*the user fence used to vm bind this buffer*/
> +	uint32_t *bind_ufence;
> +	uint64_t size;
> +	uint32_t flag;
> +	uint32_t vm;
> +	uint32_t bo;
> +	uint32_t placement;
> +	uint32_t bind_queue;
> +	/*only a cmd buffer has a exec queue*/
> +	uint32_t exec_queue;
> +	int fd;
> +	bool is_userptr;
> +};
> +
> +typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va, uint32_t val);
> +void xe_create_buffer(struct xe_buffer *buffer);
> +void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
> +		uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci);
> +uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
> +uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
> +void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
> +void xe_submit_cmd(struct xe_buffer *cmdbuf);
> +int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
> +void xe_destroy_buffer(struct xe_buffer *buffer);
> +void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf);
> +
>  #define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
>  	(xe_region_class(fd, region) == DRM_XE_MEM_REGION_CLASS_SYSMEM)
>  #define XE_IS_VRAM_MEMORY_REGION(fd, region) \
> -- 
> 2.25.1
> 

[PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test

[Bommu Krishnaiah]

Add basic test to validate helper functions introduced in
'lib/xe/xe_util: helper function'. This test writes values
to the destination buffer using GPU (MI_STORE_DWORD_IMM_GEN4).

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 tests/intel/xe_svm.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build    |  1 +
 2 files changed, 100 insertions(+)
 create mode 100644 tests/intel/xe_svm.c

diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
new file mode 100644
index 000000000..6302af95b
--- /dev/null
+++ b/tests/intel/xe_svm.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: MIT
+ /*
+  * Copyright © 2024 Intel Corporation
+  */
+
+/** @file xe_svm.c
+ *
+ * Test shared virtual memory.
+ *
+ * Shared virtual memory (SVM) is a xe driver feature
+ * which provide shared virtual address space b/t CPU and GPU
+ * program. This means application writer can just malloc or mmap,
+ * and use the returned ptr for both CPU and GPU program.
+ */
+
+/**
+ * TEST: xe-svm
+ * Description: Test shared virtual memory
+ * Sub-category: Memory management
+ * Functionality: svm
+ *
+ * SUBTEST: xe-basic
+ * Description: Basic test to verify store dword functionality using helper functions
+ */
+
+#include <fcntl.h>
+#include <string.h>
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+#include "lib/xe/xe_util.h"
+#include "xe_drm.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+/**
+ *  @brief Verifies basic workload execution on the GPU.
+ *
+ * This function tests writing a value to a GPU buffer using the helper functions
+ * for command submission and buffer management.
+ */
+static void xe_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	uint32_t val = 0xc0ffee;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+
+	struct xe_buffer dst_buf = {
+		.fd = fd,
+		.gpu_addr = (void *)(uintptr_t)gpu_va,
+		.vm = vm,
+		.size = bo_size,
+		.placement = vram_if_possible(fd, eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	struct xe_buffer cmd_buf = {
+		.fd = fd,
+		.gpu_addr = (void *)(uintptr_t)gpu_va + bo_size,
+		.vm = vm,
+		.size = bo_size,
+		.placement = vram_if_possible(fd, eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	xe_create_buffer(&dst_buf);
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst_buf.gpu_addr, val, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*(uint32_t *)dst_buf.cpu_addr, val);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	xe_destroy_buffer(&dst_buf);
+}
+
+igt_main
+{
+	int fd;
+	uint32_t vm;
+	struct drm_xe_engine_class_instance *hwe;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		igt_require(xe_supports_faults(fd));
+		vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
+	}
+
+	igt_subtest_f("xe-basic")
+		xe_for_each_engine(fd, hwe)
+			xe_basic(fd, vm, hwe);
+
+	igt_fixture {
+		xe_vm_destroy(fd, vm);
+		drm_close_driver(fd);
+	}
+}
+
diff --git a/tests/meson.build b/tests/meson.build
index 758ae090c..be792a4fd 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -314,6 +314,7 @@ intel_xe_progs = [
 	'xe_vm',
 	'xe_waitfence',
 	'xe_spin_batch',
+	'xe_svm',
 	'xe_sysfs_defaults',
 	'xe_sysfs_scheduler',
 ]
-- 
2.25.1

RE: [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test

[Zeng, Oak]

Reviewed-by: Oak Zeng <oak.zeng@intel.com>

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test
> 
> Add basic test to validate helper functions introduced in
> 'lib/xe/xe_util: helper function'. This test writes values
> to the destination buffer using GPU (MI_STORE_DWORD_IMM_GEN4).
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  tests/intel/xe_svm.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build    |  1 +
>  2 files changed, 100 insertions(+)
>  create mode 100644 tests/intel/xe_svm.c
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> new file mode 100644
> index 000000000..6302af95b
> --- /dev/null
> +++ b/tests/intel/xe_svm.c
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: MIT
> + /*
> +  * Copyright © 2024 Intel Corporation
> +  */
> +
> +/** @file xe_svm.c
> + *
> + * Test shared virtual memory.
> + *
> + * Shared virtual memory (SVM) is a xe driver feature
> + * which provide shared virtual address space b/t CPU and GPU
> + * program. This means application writer can just malloc or mmap,
> + * and use the returned ptr for both CPU and GPU program.
> + */
> +
> +/**
> + * TEST: xe-svm
> + * Description: Test shared virtual memory
> + * Sub-category: Memory management
> + * Functionality: svm
> + *
> + * SUBTEST: xe-basic
> + * Description: Basic test to verify store dword functionality using helper
> functions
> + */
> +
> +#include <fcntl.h>
> +#include <string.h>
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "lib/xe/xe_util.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +/**
> + *  @brief Verifies basic workload execution on the GPU.
> + *
> + * This function tests writing a value to a GPU buffer using the helper functions
> + * for command submission and buffer management.
> + */
> +static void xe_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance
> *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	uint32_t val = 0xc0ffee;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +
> +	struct xe_buffer dst_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	struct xe_buffer cmd_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va + bo_size,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	xe_create_buffer(&dst_buf);
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst_buf.gpu_addr,
> val, eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*(uint32_t *)dst_buf.cpu_addr, val);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	xe_destroy_buffer(&dst_buf);
> +}
> +
> +igt_main
> +{
> +	int fd;
> +	uint32_t vm;
> +	struct drm_xe_engine_class_instance *hwe;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		igt_require(xe_supports_faults(fd));
> +		vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE
> | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
> +	}
> +
> +	igt_subtest_f("xe-basic")
> +		xe_for_each_engine(fd, hwe)
> +			xe_basic(fd, vm, hwe);
> +
> +	igt_fixture {
> +		xe_vm_destroy(fd, vm);
> +		drm_close_driver(fd);
> +	}
> +}
> +
> diff --git a/tests/meson.build b/tests/meson.build
> index 758ae090c..be792a4fd 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -314,6 +314,7 @@ intel_xe_progs = [
>  	'xe_vm',
>  	'xe_waitfence',
>  	'xe_spin_batch',
> +	'xe_svm',
>  	'xe_sysfs_defaults',
>  	'xe_sysfs_scheduler',
>  ]
> --
> 2.25.1

RE: [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test

[Piecielska, Katarzyna]

Hello,
I see r-b for this test and that is ok. Before merging this series please make sure that you have Mega feature in test documentation (it was added to IGT upstream last week).
So it should be something like this:
> + * TEST: xe-svm
> + * Description: Test shared virtual memory
Mega feature: General Core features
Sub-category: Memory management tests
> + * Functionality: svm

Thanks,
Kasia
-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Zeng, Oak
Sent: Friday, May 17, 2024 4:24 PM
To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; igt-dev@lists.freedesktop.org
Cc: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>
Subject: RE: [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test

Reviewed-by: Oak Zeng <oak.zeng@intel.com>

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak 
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad 
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic 
> test
> 
> Add basic test to validate helper functions introduced in
> 'lib/xe/xe_util: helper function'. This test writes values to the 
> destination buffer using GPU (MI_STORE_DWORD_IMM_GEN4).
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  tests/intel/xe_svm.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build    |  1 +
>  2 files changed, 100 insertions(+)
>  create mode 100644 tests/intel/xe_svm.c
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c new file mode 
> 100644 index 000000000..6302af95b
> --- /dev/null
> +++ b/tests/intel/xe_svm.c
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: MIT
> + /*
> +  * Copyright © 2024 Intel Corporation
> +  */
> +
> +/** @file xe_svm.c
> + *
> + * Test shared virtual memory.
> + *
> + * Shared virtual memory (SVM) is a xe driver feature
> + * which provide shared virtual address space b/t CPU and GPU
> + * program. This means application writer can just malloc or mmap,
> + * and use the returned ptr for both CPU and GPU program.
> + */
> +
> +/**
> + * TEST: xe-svm
> + * Description: Test shared virtual memory
> + * Sub-category: Memory management
> + * Functionality: svm
> + *
> + * SUBTEST: xe-basic
> + * Description: Basic test to verify store dword functionality using 
> +helper
> functions
> + */
> +
> +#include <fcntl.h>
> +#include <string.h>
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "lib/xe/xe_util.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +/**
> + *  @brief Verifies basic workload execution on the GPU.
> + *
> + * This function tests writing a value to a GPU buffer using the 
> +helper functions
> + * for command submission and buffer management.
> + */
> +static void xe_basic(int fd, uint32_t vm, struct 
> +drm_xe_engine_class_instance
> *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	uint32_t val = 0xc0ffee;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +
> +	struct xe_buffer dst_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	struct xe_buffer cmd_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va + bo_size,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	xe_create_buffer(&dst_buf);
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst_buf.gpu_addr,
> val, eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*(uint32_t *)dst_buf.cpu_addr, val);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	xe_destroy_buffer(&dst_buf);
> +}
> +
> +igt_main
> +{
> +	int fd;
> +	uint32_t vm;
> +	struct drm_xe_engine_class_instance *hwe;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		igt_require(xe_supports_faults(fd));
> +		vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE
> | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
> +	}
> +
> +	igt_subtest_f("xe-basic")
> +		xe_for_each_engine(fd, hwe)
> +			xe_basic(fd, vm, hwe);
> +
> +	igt_fixture {
> +		xe_vm_destroy(fd, vm);
> +		drm_close_driver(fd);
> +	}
> +}
> +
> diff --git a/tests/meson.build b/tests/meson.build index 
> 758ae090c..be792a4fd 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -314,6 +314,7 @@ intel_xe_progs = [
>  	'xe_vm',
>  	'xe_waitfence',
>  	'xe_spin_batch',
> +	'xe_svm',
>  	'xe_sysfs_defaults',
>  	'xe_sysfs_scheduler',
>  ]
> --
> 2.25.1

[PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests using malloc and mmap

[Bommu Krishnaiah]

Adds subtests to verify the basic functionality of Shared Virtual Memory (SVM)
in the xe driver. The tests ensure that memory allocated with malloc or mmap can be correctly
used for GPU command submission and data verification.

Subtests:
- svm-basic-malloc: Verifies SVM functionality using memory allocated with malloc.
- svm-basic-mmap: Verifies SVM functionality using memory allocated with mmap.

The verification is done by writing a specific value to the allocated memory via GPU and
checking if the value is correctly stored.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 include/drm-uapi/xe_drm.h |  1 +
 tests/intel/xe_svm.c      | 52 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 0b709b374..69c8792bb 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -973,6 +973,7 @@ struct drm_xe_vm_bind_op {
 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE	(1 << 1)
 #define DRM_XE_VM_BIND_FLAG_NULL	(1 << 2)
 #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
+#define DRM_XE_VM_BIND_FLAG_SYSTEM_ALLOCATOR	(1 << 4)
 	/** @flags: Bind flags */
 	__u32 flags;
 
diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 6302af95b..741961529 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -21,6 +21,12 @@
  *
  * SUBTEST: xe-basic
  * Description: Basic test to verify store dword functionality using helper functions
+ *
+ * SUBTEST: svm-basic-malloc
+ * Description: Verify SVM basic functionality using malloc.
+ *
+ * SUBTEST: svm-basic-mmap
+ * Description: Verify SVM basic functionality using mmap.
  */
 
 #include <fcntl.h>
@@ -75,6 +81,44 @@ static void xe_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance *e
 	xe_destroy_buffer(&dst_buf);
 }
 
+/**
+ * @brief Tests SVM functionality using malloc or mmap.
+ *
+ * This function tests the ability to use malloc or mmap allocated memory
+ * for direct GPU command submission and data verification.
+ */
+static void svm_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci, bool test_mmap)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t *dst;
+
+	struct xe_buffer cmd_buf = {
+		.fd = fd,
+		.gpu_addr = (void *)(uintptr_t)gpu_va,
+		.vm = vm,
+		.size = bo_size,
+		.placement = vram_if_possible(fd, eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	if (test_mmap)
+		dst = mmap(NULL, 4, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
+	else
+		dst = aligned_alloc(xe_get_default_alignment(fd), 4);
+
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst, 0xc0ffee);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	if (test_mmap)
+		munmap(dst, 4);
+	else
+		free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -91,6 +135,14 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			xe_basic(fd, vm, hwe);
 
+	igt_subtest_f("svm-basic-malloc")
+		xe_for_each_engine(fd, hwe)
+			svm_basic(fd, vm, hwe, false);
+
+	igt_subtest_f("svm-basic-mmap")
+		xe_for_each_engine(fd, hwe)
+			svm_basic(fd, vm, hwe, true);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests using malloc and mmap

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests using
> malloc and mmap
> 
> Adds subtests to verify the basic functionality of Shared Virtual Memory (SVM)
> in the xe driver. The tests ensure that memory allocated with malloc or mmap
> can be correctly
> used for GPU command submission and data verification.
> 
> Subtests:
> - svm-basic-malloc: Verifies SVM functionality using memory allocated with
> malloc.
> - svm-basic-mmap: Verifies SVM functionality using memory allocated with
> mmap.
> 
> The verification is done by writing a specific value to the allocated memory via
> GPU and
> checking if the value is correctly stored.
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  include/drm-uapi/xe_drm.h |  1 +
>  tests/intel/xe_svm.c      | 52 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
> 
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 0b709b374..69c8792bb 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -973,6 +973,7 @@ struct drm_xe_vm_bind_op {
>  #define DRM_XE_VM_BIND_FLAG_IMMEDIATE	(1 << 1)
>  #define DRM_XE_VM_BIND_FLAG_NULL	(1 << 2)
>  #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
> +#define DRM_XE_VM_BIND_FLAG_SYSTEM_ALLOCATOR	(1 << 4)

You introduced this flag but didn't use it.

Use it to perform the whole address space vm bind in th igt fixture.


>  	/** @flags: Bind flags */
>  	__u32 flags;
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index 6302af95b..741961529 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -21,6 +21,12 @@
>   *
>   * SUBTEST: xe-basic
>   * Description: Basic test to verify store dword functionality using helper
> functions
> + *
> + * SUBTEST: svm-basic-malloc
> + * Description: Verify SVM basic functionality using malloc.
> + *
> + * SUBTEST: svm-basic-mmap
> + * Description: Verify SVM basic functionality using mmap.
>   */
> 
>  #include <fcntl.h>
> @@ -75,6 +81,44 @@ static void xe_basic(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *e
>  	xe_destroy_buffer(&dst_buf);
>  }
> 
> +/**
> + * @brief Tests SVM functionality using malloc or mmap.
> + *
> + * This function tests the ability to use malloc or mmap allocated memory
> + * for direct GPU command submission and data verification.
> + */
> +static void svm_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance
> *eci, bool test_mmap)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +	uint32_t *dst;
> +
> +	struct xe_buffer cmd_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	if (test_mmap)
> +		dst = mmap(NULL, 4, PROT_READ|PROT_WRITE,
> MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
> +	else
> +		dst = aligned_alloc(xe_get_default_alignment(fd), 4);


Hmm, I currently assume system allocator should be able handle a allocation of 4 bytes, even without an alignment. If not, it is a driver bug. Let's remove the alignment for now.
> +
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);

Maybe change the dst_va parameter of xe_create_cmdbuf to void *, and do a cast inside xe_create_cmd_buf to cast the dst_va to uinit64_t. this way we don't need to cast every time we call xe_create_cmdbuf.

Oak

> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*dst, 0xc0ffee);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	if (test_mmap)
> +		munmap(dst, 4);
> +	else
> +		free(dst);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -91,6 +135,14 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			xe_basic(fd, vm, hwe);
> 
> +	igt_subtest_f("svm-basic-malloc")
> +		xe_for_each_engine(fd, hwe)
> +			svm_basic(fd, vm, hwe, false);
> +
> +	igt_subtest_f("svm-basic-mmap")
> +		xe_for_each_engine(fd, hwe)
> +			svm_basic(fd, vm, hwe, true);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

RE: [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests using malloc and mmap

[Bommu, Krishnaiah]

> -----Original Message-----
> From: Zeng, Oak <oak.zeng@intel.com>
> Sent: Friday, May 17, 2024 8:10 PM
> To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; igt-
> dev@lists.freedesktop.org
> Cc: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>
> Subject: RE: [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests
> using malloc and mmap
> 
> 
> 
> > -----Original Message-----
> > From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> > Sent: Friday, May 17, 2024 7:47 AM
> > To: igt-dev@lists.freedesktop.org
> > Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> > <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> > <himal.prasad.ghimiray@intel.com>
> > Subject: [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic
> > tests using malloc and mmap
> >
> > Adds subtests to verify the basic functionality of Shared Virtual
> > Memory (SVM) in the xe driver. The tests ensure that memory allocated
> > with malloc or mmap can be correctly used for GPU command submission
> > and data verification.
> >
> > Subtests:
> > - svm-basic-malloc: Verifies SVM functionality using memory allocated
> > with malloc.
> > - svm-basic-mmap: Verifies SVM functionality using memory allocated
> > with mmap.
> >
> > The verification is done by writing a specific value to the allocated
> > memory via GPU and checking if the value is correctly stored.
> >
> > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Oak Zeng <oak.zeng@intel.com>
> > Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > ---
> >  include/drm-uapi/xe_drm.h |  1 +
> >  tests/intel/xe_svm.c      | 52 +++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 53 insertions(+)
> >
> > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> > index 0b709b374..69c8792bb 100644
> > --- a/include/drm-uapi/xe_drm.h
> > +++ b/include/drm-uapi/xe_drm.h
> > @@ -973,6 +973,7 @@ struct drm_xe_vm_bind_op {
> >  #define DRM_XE_VM_BIND_FLAG_IMMEDIATE	(1 << 1)
> >  #define DRM_XE_VM_BIND_FLAG_NULL	(1 << 2)
> >  #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
> > +#define DRM_XE_VM_BIND_FLAG_SYSTEM_ALLOCATOR	(1 << 4)
> 
> You introduced this flag but didn't use it.
> 
> Use it to perform the whole address space vm bind in th igt fixture.
> 
__xe_vm_bind_assert(fd, vm, 0, 0, 0, 0, 0x1ull << 47, DRM_XE_VM_BIND_OP_MAP,
                                DRM_XE_VM_BIND_FLAG_SYSTEM_ALLOCATOR, 0, 0, 0, 0);
I added this in previous patch, I forget to add this in this patch, I will add in igt fixture

Regards,
Krishna.
> 
> >  	/** @flags: Bind flags */
> >  	__u32 flags;
> >
> > diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c index
> > 6302af95b..741961529 100644
> > --- a/tests/intel/xe_svm.c
> > +++ b/tests/intel/xe_svm.c
> > @@ -21,6 +21,12 @@
> >   *
> >   * SUBTEST: xe-basic
> >   * Description: Basic test to verify store dword functionality using
> > helper functions
> > + *
> > + * SUBTEST: svm-basic-malloc
> > + * Description: Verify SVM basic functionality using malloc.
> > + *
> > + * SUBTEST: svm-basic-mmap
> > + * Description: Verify SVM basic functionality using mmap.
> >   */
> >
> >  #include <fcntl.h>
> > @@ -75,6 +81,44 @@ static void xe_basic(int fd, uint32_t vm, struct
> > drm_xe_engine_class_instance *e
> >  	xe_destroy_buffer(&dst_buf);
> >  }
> >
> > +/**
> > + * @brief Tests SVM functionality using malloc or mmap.
> > + *
> > + * This function tests the ability to use malloc or mmap allocated
> > +memory
> > + * for direct GPU command submission and data verification.
> > + */
> > +static void svm_basic(int fd, uint32_t vm, struct
> > +drm_xe_engine_class_instance
> > *eci, bool test_mmap)
> > +{
> > +	uint64_t gpu_va = 0x1a0000;
> > +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> > +	uint32_t *dst;
> > +
> > +	struct xe_buffer cmd_buf = {
> > +		.fd = fd,
> > +		.gpu_addr = (void *)(uintptr_t)gpu_va,
> > +		.vm = vm,
> > +		.size = bo_size,
> > +		.placement = vram_if_possible(fd, eci->gt_id),
> > +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> > +	};
> > +
> > +	if (test_mmap)
> > +		dst = mmap(NULL, 4, PROT_READ|PROT_WRITE,
> > MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
> > +	else
> > +		dst = aligned_alloc(xe_get_default_alignment(fd), 4);
> 
> 
> Hmm, I currently assume system allocator should be able handle a allocation of
> 4 bytes, even without an alignment. If not, it is a driver bug. Let's remove the
> alignment for now.
> > +
> > +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee,
> > +eci);
> 
> Maybe change the dst_va parameter of xe_create_cmdbuf to void *, and do a
> cast inside xe_create_cmd_buf to cast the dst_va to uinit64_t. this way we don't
> need to cast every time we call xe_create_cmdbuf.
> 
> Oak
> 
> > +	xe_submit_cmd(&cmd_buf);
> > +
> > +	igt_assert_eq(*dst, 0xc0ffee);
> > +
> > +	xe_destroy_cmdbuf(&cmd_buf);
> > +	if (test_mmap)
> > +		munmap(dst, 4);
> > +	else
> > +		free(dst);
> > +}
> > +
> >  igt_main
> >  {
> >  	int fd;
> > @@ -91,6 +135,14 @@ igt_main
> >  		xe_for_each_engine(fd, hwe)
> >  			xe_basic(fd, vm, hwe);
> >
> > +	igt_subtest_f("svm-basic-malloc")
> > +		xe_for_each_engine(fd, hwe)
> > +			svm_basic(fd, vm, hwe, false);
> > +
> > +	igt_subtest_f("svm-basic-mmap")
> > +		xe_for_each_engine(fd, hwe)
> > +			svm_basic(fd, vm, hwe, true);
> > +
> >  	igt_fixture {
> >  		xe_vm_destroy(fd, vm);
> >  		drm_close_driver(fd);
> > --
> > 2.25.1

[PATCH i-g-t v3 04/10] tests/intel/xe_svm: add random access test for SVM

[Bommu Krishnaiah]

Verifies the Shared Virtual Memory (SVM) functionality by randomly
accessing any location in malloc'ed memory. The test ensures that
the GPU can correctly handle random memory access patterns.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 tests/intel/xe_svm.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 741961529..73a232c47 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -27,6 +27,9 @@
  *
  * SUBTEST: svm-basic-mmap
  * Description: Verify SVM basic functionality using mmap.
+ *
+ * SUBTEST: svm-random-access
+ * Description: Verifies that the GPU can randomly access and correctly store values in malloc'ed memory.
  */
 
 #include <fcntl.h>
@@ -119,6 +122,40 @@ static void svm_basic(int fd, uint32_t vm, struct drm_xe_engine_class_instance *
 		free(dst);
 }
 
+/**
+ *  @brief Verifies GPU can randomly access any location in malloc'ed memory.
+ *
+ *This function tests the ability of the GPU to randomly access and correctly store
+ * values in malloc'ed memory.
+ */
+static void svm_random_access(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t *dst, *dst_to_access;
+	uint32_t size = 1024*1024, sz_dw = size/4;
+
+	struct xe_buffer cmd_buf = {
+		.fd = fd,
+		.gpu_addr = (void *)(uintptr_t)gpu_va,
+		.vm = vm,
+		.size = bo_size,
+		.placement = vram_if_possible(fd, eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	dst = malloc(size);
+	dst_to_access = dst + random()%sz_dw;
+
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst_to_access, 0xc0ffee, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst, 0xc0ffee);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -143,6 +180,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_basic(fd, vm, hwe, true);
 
+	igt_subtest_f("svm-random-access")
+		xe_for_each_engine(fd, hwe)
+			svm_random_access(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 04/10] tests/intel/xe_svm: add random access test for SVM

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 04/10] tests/intel/xe_svm: add random access test for
> SVM
> 
> Verifies the Shared Virtual Memory (SVM) functionality by randomly
> accessing any location in malloc'ed memory. The test ensures that
> the GPU can correctly handle random memory access patterns.
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  tests/intel/xe_svm.c | 41 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index 741961529..73a232c47 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -27,6 +27,9 @@
>   *
>   * SUBTEST: svm-basic-mmap
>   * Description: Verify SVM basic functionality using mmap.
> + *
> + * SUBTEST: svm-random-access
> + * Description: Verifies that the GPU can randomly access and correctly store
> values in malloc'ed memory.
>   */
> 
>  #include <fcntl.h>
> @@ -119,6 +122,40 @@ static void svm_basic(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *
>  		free(dst);
>  }
> 
> +/**
> + *  @brief Verifies GPU can randomly access any location in malloc'ed memory.
> + *
> + *This function tests the ability of the GPU to randomly access and correctly
> store
> + * values in malloc'ed memory.
> + */
> +static void svm_random_access(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +	uint32_t *dst, *dst_to_access;
> +	uint32_t size = 1024*1024, sz_dw = size/4;
> +
> +	struct xe_buffer cmd_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va,

Why you need uintptr_t? same to last patch

Oak
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	dst = malloc(size);
> +	dst_to_access = dst + random()%sz_dw;
> +
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst_to_access,
> 0xc0ffee, eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*dst, 0xc0ffee);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	free(dst);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -143,6 +180,10 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			svm_basic(fd, vm, hwe, true);
> 
> +	igt_subtest_f("svm-random-access")
> +		xe_for_each_engine(fd, hwe)
> +			svm_random_access(fd, vm, hwe);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

[PATCH i-g-t v3 05/10] tests/intel/xe_svm: add huge page access test for SVM

[Bommu Krishnaiah]

svm-huge-page verifies the Shared Virtual Memory (SVM) functionality
by using huge page access. The test allocates 2MB of aligned memory
to utilize huge pages and verifies GPU access to this memory.

Subtest:
- svm-huge-page: Verifies that the GPU can correctly access memory allocated
  as huge pages (2MB aligned).

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 tests/intel/xe_svm.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 73a232c47..d9629246c 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -30,6 +30,9 @@
  *
  * SUBTEST: svm-random-access
  * Description: Verifies that the GPU can randomly access and correctly store values in malloc'ed memory.
+ *
+ * SUBTEST: svm-huge-page
+ * Description: verify SVM basic functionality by using huge page access
  */
 
 #include <fcntl.h>
@@ -156,6 +159,49 @@ static void svm_random_access(int fd, uint32_t vm, struct drm_xe_engine_class_in
 	free(dst);
 }
 
+/**
+ * Test the behavior of transparent huge page.
+ * Allocate 2MB of aligned memory so huge page
+ * is used. What happens if driver only migrate
+ * 1 4k page of that buffer to GPU?
+ *
+ * Test result shows that the huge page is splitted
+ * into small pages and only one 4k page is
+ * migrated.
+ */
+static void svm_thp(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t size = 1<<21; //2MB
+	uint32_t *dst;
+	int ret;
+
+	struct xe_buffer cmd_buf = {
+		.fd = fd,
+		.gpu_addr = (void *)(uintptr_t)gpu_va,
+		.vm = vm,
+		.size = bo_size,
+		.placement = vram_if_possible(fd, eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	ret = posix_memalign((void **)&dst, size, size);
+	igt_assert_eq(ret, 0);
+	/** TODO huge page advice cause the system hang
+	* when process exit...Very possible a hmm bug
+	**/
+	memset(dst, 0xbe, size);
+
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst, 0xc0ffee);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -184,6 +230,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_random_access(fd, vm, hwe);
 
+	igt_subtest_f("svm-huge-page")
+		xe_for_each_engine(fd, hwe)
+			svm_thp(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 05/10] tests/intel/xe_svm: add huge page access test for SVM

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 05/10] tests/intel/xe_svm: add huge page access test
> for SVM
> 
> svm-huge-page verifies the Shared Virtual Memory (SVM) functionality
> by using huge page access. The test allocates 2MB of aligned memory
> to utilize huge pages and verifies GPU access to this memory.
> 
> Subtest:
> - svm-huge-page: Verifies that the GPU can correctly access memory allocated
>   as huge pages (2MB aligned).
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  tests/intel/xe_svm.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index 73a232c47..d9629246c 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -30,6 +30,9 @@
>   *
>   * SUBTEST: svm-random-access
>   * Description: Verifies that the GPU can randomly access and correctly store
> values in malloc'ed memory.
> + *
> + * SUBTEST: svm-huge-page
> + * Description: verify SVM basic functionality by using huge page access
>   */
> 
>  #include <fcntl.h>
> @@ -156,6 +159,49 @@ static void svm_random_access(int fd, uint32_t vm,
> struct drm_xe_engine_class_in
>  	free(dst);
>  }
> 
> +/**
> + * Test the behavior of transparent huge page.
> + * Allocate 2MB of aligned memory so huge page
> + * is used. What happens if driver only migrate
> + * 1 4k page of that buffer to GPU?

On i915, we only migrate 1 4k page on gpu page fault. On xekmd, we changed this behavior. We migrate whole cpu vma for now. With the migration granularity work Himal is doing, we will migrate with migration granularity. The default granularity is 2MiB.

> + *
> + * Test result shows that the huge page is splitted
> + * into small pages and only one 4k page is
> + * migrated.
> + */
> +static void svm_thp(int fd, uint32_t vm, struct drm_xe_engine_class_instance
> *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +	uint32_t size = 1<<21; //2MB
> +	uint32_t *dst;
> +	int ret;
> +
> +	struct xe_buffer cmd_buf = {
> +		.fd = fd,
> +		.gpu_addr = (void *)(uintptr_t)gpu_va,
> +		.vm = vm,
> +		.size = bo_size,
> +		.placement = vram_if_possible(fd, eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	ret = posix_memalign((void **)&dst, size, size);
> +	igt_assert_eq(ret, 0);
> +	/** TODO huge page advice cause the system hang
> +	* when process exit...Very possible a hmm bug
> +	**/

Not sure whether we still this issue or not. We will have to test to see.

Oak
> +	memset(dst, 0xbe, size);
> +
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*dst, 0xc0ffee);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	free(dst);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -184,6 +230,10 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			svm_random_access(fd, vm, hwe);
> 
> +	igt_subtest_f("svm-huge-page")
> +		xe_for_each_engine(fd, hwe)
> +			svm_thp(fd, vm, hwe);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

[PATCH i-g-t v3 06/10] tests/intel/xe_svm: Add support for GPU atomic access test for svm

[Bommu Krishnaiah]

Verify GPU atomic access using multiple threads by performing operations on
randomly allocated locations within malloc'ed memory in shared virtual memory.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 lib/xe/xe_util.c     | 11 +++++++
 lib/xe/xe_util.h     |  1 +
 tests/intel/xe_svm.c | 71 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 83 insertions(+)

diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index de848b8bc..672e9dcef 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -117,6 +117,17 @@ void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val)
 	batch[++i] = MI_BATCH_BUFFER_END;
 }
 
+// Function to insert atomic increment command
+void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val)
+{
+	int i = 0;
+
+	batch[i] = MI_ATOMIC | MI_ATOMIC_INC;
+	batch[++i] = dst_va;
+	batch[++i] = dst_va >> 32;
+	batch[++i] = MI_BATCH_BUFFER_END;
+}
+
 /**
  * Creates a command buffer, fills it with commands using the provided fill
  * function, and sets up the execution queue for submission.
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index c38f79e60..46e1ccc9a 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -40,6 +40,7 @@ void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
 uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
 uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
 void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
+void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void xe_submit_cmd(struct xe_buffer *cmdbuf);
 int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
 void xe_destroy_buffer(struct xe_buffer *buffer);
diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index d9629246c..f9e8eb2d9 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -33,6 +33,9 @@
  *
  * SUBTEST: svm-huge-page
  * Description: verify SVM basic functionality by using huge page access
+ *
+ * SUBTEST: svm-atomic-access
+ * Description: verify SVM basic functionality by using GPU atomic access any location in malloc'ed memory
  */
 
 #include <fcntl.h>
@@ -47,6 +50,18 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
+#define NUM_THREADS 10
+
+// Thread argument structure
+typedef struct {
+	int fd;
+	uint32_t vm;
+	void *gpu_va;
+	uint64_t dst_va;
+	uint32_t val;
+	struct drm_xe_engine_class_instance *eci;
+} thread_args_t;
+
 /**
  *  @brief Verifies basic workload execution on the GPU.
  *
@@ -202,6 +217,58 @@ static void svm_thp(int fd, uint32_t vm, struct drm_xe_engine_class_instance *ec
 	free(dst);
 }
 
+
+// Thread function for submitting atomic increment commands
+static void* thread_func(void* args)
+{
+	thread_args_t *thread_args = (thread_args_t *)args;
+	struct xe_buffer cmd_buf = {
+		.fd = thread_args->fd,
+		.gpu_addr = (void *)(uintptr_t)thread_args->gpu_va,
+		.vm = thread_args->vm,
+		.size = xe_bb_size(thread_args->fd, PAGE_ALIGN_UFENCE),
+		.placement = vram_if_possible(thread_args->fd, thread_args->eci->gt_id),
+		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	xe_create_cmdbuf(&cmd_buf, insert_atomic_inc, thread_args->dst_va, thread_args->val, thread_args->eci);
+	xe_submit_cmd(&cmd_buf);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+
+	return NULL;
+}
+
+// Test GPU atomic access with multiple threads
+static void svm_atomic_access(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	int val = 0xc0ffee;
+	uint32_t *dst, *dst_to_access;
+	uint32_t size = 1024 * 1024, sz_dw = size / 4;
+	pthread_t threads[NUM_THREADS];
+
+	dst = aligned_alloc(xe_get_default_alignment(fd), size);
+	dst_to_access = dst + (rand() % sz_dw);
+	*dst_to_access = val;
+
+	thread_args_t thread_args = { fd, vm, (void *)(uintptr_t)gpu_va, (uint64_t)dst_to_access, val, eci };
+
+	// Create and launch threads
+	for (int i = 0; i < NUM_THREADS; i++) {
+		pthread_create(&threads[i], NULL, thread_func, &thread_args);
+	}
+
+	// Wait for all threads to finish
+	for (int i = 0; i < NUM_THREADS; i++) {
+		pthread_join(threads[i], NULL);
+	}
+
+	igt_assert_eq(*dst_to_access, val + NUM_THREADS);
+
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -234,6 +301,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_thp(fd, vm, hwe);
 
+	igt_subtest_f("svm-atomic-access")
+		xe_for_each_engine(fd, hwe)
+			svm_atomic_access(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 06/10] tests/intel/xe_svm: Add support for GPU atomic access test for svm

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 06/10] tests/intel/xe_svm: Add support for GPU atomic
> access test for svm
> 
> Verify GPU atomic access using multiple threads by performing operations on
> randomly allocated locations within malloc'ed memory in shared virtual memory.
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  lib/xe/xe_util.c     | 11 +++++++
>  lib/xe/xe_util.h     |  1 +
>  tests/intel/xe_svm.c | 71 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 83 insertions(+)
> 
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index de848b8bc..672e9dcef 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -117,6 +117,17 @@ void insert_store(uint32_t *batch, uint64_t dst_va,
> uint32_t val)
>  	batch[++i] = MI_BATCH_BUFFER_END;
>  }
> 
> +// Function to insert atomic increment command
> +void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val)
> +{
> +	int i = 0;

You can write:

(void)val;

To annotate the parameter val is not used.

> +
> +	batch[i] = MI_ATOMIC | MI_ATOMIC_INC;
> +	batch[++i] = dst_va;
> +	batch[++i] = dst_va >> 32;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +}
> +
>  /**
>   * Creates a command buffer, fills it with commands using the provided fill
>   * function, and sets up the execution queue for submission.
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index c38f79e60..46e1ccc9a 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -40,6 +40,7 @@ void xe_create_cmdbuf(struct xe_buffer *cmd_buf,
> cmdbuf_fill_func_t fill_func,
>  uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
>  uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
>  void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
> +void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
>  void xe_submit_cmd(struct xe_buffer *cmdbuf);
>  int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
>  void xe_destroy_buffer(struct xe_buffer *buffer);
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index d9629246c..f9e8eb2d9 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -33,6 +33,9 @@
>   *
>   * SUBTEST: svm-huge-page
>   * Description: verify SVM basic functionality by using huge page access
> + *
> + * SUBTEST: svm-atomic-access
> + * Description: verify SVM basic functionality by using GPU atomic access any
> location in malloc'ed memory
>   */
> 
>  #include <fcntl.h>
> @@ -47,6 +50,18 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> 
> +#define NUM_THREADS 10
> +
> +// Thread argument structure
> +typedef struct {
> +	int fd;
> +	uint32_t vm;
> +	void *gpu_va;
> +	uint64_t dst_va;
> +	uint32_t val;
> +	struct drm_xe_engine_class_instance *eci;
> +} thread_args_t;
> +
>  /**
>   *  @brief Verifies basic workload execution on the GPU.
>   *
> @@ -202,6 +217,58 @@ static void svm_thp(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *ec
>  	free(dst);
>  }
> 
> +
> +// Thread function for submitting atomic increment commands
> +static void* thread_func(void* args)
> +{
> +	thread_args_t *thread_args = (thread_args_t *)args;
> +	struct xe_buffer cmd_buf = {
> +		.fd = thread_args->fd,
> +		.gpu_addr = (void *)(uintptr_t)thread_args->gpu_va,

So you are creating many cmd buffers, one per thread. But all those command buffers are bind to the same gpu_va. This won't work.

You need to use different gpu va for each command buffer

> +		.vm = thread_args->vm,
> +		.size = xe_bb_size(thread_args->fd, PAGE_ALIGN_UFENCE),
> +		.placement = vram_if_possible(thread_args->fd, thread_args-
> >eci->gt_id),
> +		.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	xe_create_cmdbuf(&cmd_buf, insert_atomic_inc, thread_args->dst_va,
> thread_args->val, thread_args->eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +
> +	return NULL;
> +}
> +
> +// Test GPU atomic access with multiple threads
> +static void svm_atomic_access(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	int val = 0xc0ffee;
> +	uint32_t *dst, *dst_to_access;
> +	uint32_t size = 1024 * 1024, sz_dw = size / 4;
> +	pthread_t threads[NUM_THREADS];
> +
> +	dst = aligned_alloc(xe_get_default_alignment(fd), size);
> +	dst_to_access = dst + (rand() % sz_dw);
> +	*dst_to_access = val;
> +
> +	thread_args_t thread_args = { fd, vm, (void *)(uintptr_t)gpu_va,
> (uint64_t)dst_to_access, val, eci };

Same question as before, why uintptr_t?

Oak
> +
> +	// Create and launch threads
> +	for (int i = 0; i < NUM_THREADS; i++) {
> +		pthread_create(&threads[i], NULL, thread_func, &thread_args);
> +	}
> +
> +	// Wait for all threads to finish
> +	for (int i = 0; i < NUM_THREADS; i++) {
> +		pthread_join(threads[i], NULL);
> +	}
> +
> +	igt_assert_eq(*dst_to_access, val + NUM_THREADS);
> +
> +	free(dst);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -234,6 +301,10 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			svm_thp(fd, vm, hwe);
> 
> +	igt_subtest_f("svm-atomic-access")
> +		xe_for_each_engine(fd, hwe)
> +			svm_atomic_access(fd, vm, hwe);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

[PATCH i-g-t v3 07/10] tests/intel/xe_svm: Add svm-invalid-va test to verify SVM functionality with invalid address access

[Bommu Krishnaiah]

svm-invalid-va test ensures that the driver correctly handles catastrophic
errors when the GPU attempts to access an invalid address in SVM.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 tests/intel/xe_svm.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index f9e8eb2d9..895cf26ac 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -36,6 +36,9 @@
  *
  * SUBTEST: svm-atomic-access
  * Description: verify SVM basic functionality by using GPU atomic access any location in malloc'ed memory
+ *
+ * SUBTEST: svm-invalid-va
+ * Description: Verify SVM functionality while accessing an invalid address.
  */
 
 #include <fcntl.h>
@@ -269,6 +272,35 @@ static void svm_atomic_access(int fd, uint32_t vm, struct drm_xe_engine_class_in
 	free(dst);
 }
 
+/**
+ * Submit a GPU command to access an invalid address.
+ * Driver should detect a catastrophic error.
+ */
+static void svm_invalid_va(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t *dst;
+
+	struct xe_buffer cmd_buf = {
+			.fd = fd,
+			.gpu_addr = (void *)(uintptr_t)gpu_va,
+			.vm = vm,
+			.size = bo_size,
+			.placement = vram_if_possible(fd, eci->gt_id),
+			.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM
+	};
+
+	dst = (uint32_t *)0x1fffffffffff000;
+
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
+
+	igt_assert_eq(__xe_submit_cmd(&cmd_buf), -EIO); // for invalid address __xe_wait_ufence will return -EIO
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -305,6 +337,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_atomic_access(fd, vm, hwe);
 
+	igt_subtest_f("svm-invalid-va")
+		xe_for_each_engine(fd, hwe)
+			svm_invalid_va(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 07/10] tests/intel/xe_svm: Add svm-invalid-va test to verify SVM functionality with invalid address access

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 07/10] tests/intel/xe_svm: Add svm-invalid-va test to
> verify SVM functionality with invalid address access
> 
> svm-invalid-va test ensures that the driver correctly handles catastrophic
> errors when the GPU attempts to access an invalid address in SVM.
> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  tests/intel/xe_svm.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index f9e8eb2d9..895cf26ac 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -36,6 +36,9 @@
>   *
>   * SUBTEST: svm-atomic-access
>   * Description: verify SVM basic functionality by using GPU atomic access any
> location in malloc'ed memory
> + *
> + * SUBTEST: svm-invalid-va
> + * Description: Verify SVM functionality while accessing an invalid address.
>   */
> 
>  #include <fcntl.h>
> @@ -269,6 +272,35 @@ static void svm_atomic_access(int fd, uint32_t vm,
> struct drm_xe_engine_class_in
>  	free(dst);
>  }
> 
> +/**
> + * Submit a GPU command to access an invalid address.
> + * Driver should detect a catastrophic error.
> + */
> +static void svm_invalid_va(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +	uint32_t *dst;
> +
> +	struct xe_buffer cmd_buf = {
> +			.fd = fd,
> +			.gpu_addr = (void *)(uintptr_t)gpu_va,
> +			.vm = vm,
> +			.size = bo_size,
> +			.placement = vram_if_possible(fd, eci->gt_id),
> +			.flag =
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM
> +	};
> +
> +	dst = (uint32_t *)0x1fffffffffff000;
> +
> +	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
> +
> +	igt_assert_eq(__xe_submit_cmd(&cmd_buf), -EIO); // for invalid
> address __xe_wait_ufence will return -EIO

Move the comment above igt_assert_eq. with that, patch is:

Reviewed-by: Oak Zeng <oak.zeng@intel.com>
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	free(dst);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -305,6 +337,10 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			svm_atomic_access(fd, vm, hwe);
> 
> +	igt_subtest_f("svm-invalid-va")
> +		xe_for_each_engine(fd, hwe)
> +			svm_invalid_va(fd, vm, hwe);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

[PATCH i-g-t v3 08/10] tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance with a simple benchmark

[Bommu Krishnaiah]

svm-benchmark test provides a basic benchmark to compare the performance of
system allocators against runtime allocators in SVM scenarios.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 lib/xe/xe_util.c     | 34 +++++++++++++++++++++++++++++++
 lib/xe/xe_util.h     |  5 +++++
 tests/intel/xe_svm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+)

diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 672e9dcef..c19cdae0c 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -128,6 +128,24 @@ void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val)
 	batch[++i] = MI_BATCH_BUFFER_END;
 }
 
+/** Insert commands to batch buffer to memset dst_va buffer with val
+ */
+void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val)
+{
+#define PVC_MEM_SET_CMD		(2 << 29 | 0x5b << 22)
+#define MS_MATRIX		(1 << 17)
+	const int page_shift = 12;
+
+	*batch++ = PVC_MEM_SET_CMD | MS_MATRIX | (7 - 2);
+	*batch++ = BIT(page_shift) - 1;
+	*batch++ = (size >> page_shift) - 1;
+	*batch++ = BIT(page_shift) - 1;
+	*batch++ = lower_32_bits(dst_va);
+	*batch++ = upper_32_bits(dst_va);
+	*batch++ = (uint32_t)val << 24;
+	*batch++ = MI_BATCH_BUFFER_END;
+}
+
 /**
  * Creates a command buffer, fills it with commands using the provided fill
  * function, and sets up the execution queue for submission.
@@ -143,6 +161,22 @@ void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func, u
 	fill_func(cmd_buf->cpu_addr, dst_va, val);
 }
 
+/**
+ * Create a command buffer and fill it with a two-DW command function.
+ */
+void xe_create_cmdbuf_fill_two_dw(struct xe_buffer *cmd_buf, cmdbuf_fill_two_dw_func_t fill_func,
+		uint64_t dst_va, uint64_t dst_va1, uint32_t val, struct drm_xe_engine_class_instance *eci)
+{
+	//make some room for a exec_ufence, which will be used to sync the
+	//submission of this command....
+
+	cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size + PAGE_ALIGN_UFENCE);
+	xe_create_buffer(cmd_buf);
+	cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd, cmd_buf->vm, eci, 0);
+	fill_func(cmd_buf->cpu_addr, dst_va, dst_va1, val);
+}
+
+
 /**
  * Destroys a command buffer created by xe_create_cmdbuf and releases
  * associated resources.
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 46e1ccc9a..50f2a4bc4 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -34,13 +34,18 @@ struct xe_buffer {
 };
 
 typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va, uint32_t val);
+typedef void (*cmdbuf_fill_two_dw_func_t) (uint32_t *batch, uint64_t dst_gpu_va,
+		uint64_t dst_gpu_va1, uint32_t val);
 void xe_create_buffer(struct xe_buffer *buffer);
 void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
 		uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci);
+void xe_create_cmdbuf_fill_two_dw(struct xe_buffer *cmd_buf, cmdbuf_fill_two_dw_func_t fill_func,
+		uint64_t dst_va, uint64_t dst_va1, uint32_t val, struct drm_xe_engine_class_instance *eci);
 uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
 uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
 void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
+void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val);
 void xe_submit_cmd(struct xe_buffer *cmdbuf);
 int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
 void xe_destroy_buffer(struct xe_buffer *buffer);
diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 895cf26ac..072a602b1 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -39,6 +39,9 @@
  *
  * SUBTEST: svm-invalid-va
  * Description: Verify SVM functionality while accessing an invalid address.
+ *
+ * SUBTEST: svm-benchmark
+ * Description: Verify SVM performance with a simple benchmark test.
  */
 
 #include <fcntl.h>
@@ -301,6 +304,47 @@ static void svm_invalid_va(int fd, uint32_t vm, struct drm_xe_engine_class_insta
 	free(dst);
 }
 
+/**
+ * A simple benchmark test.
+ * Uses the GPU to memset a buffer with a specific value and measures the end-to-end bandwidth.
+ * This provides a basic comparison of the performance between the system allocator and the runtime allocator.
+ *
+ * By comparing the output of those two tests, we can have
+ * a very basic concept of the performance of sytem allocator
+ * compared to runtime allocator.
+ */
+static void svm_benchmark(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t *dst, size = 1 << 26;
+	struct timespec start_time;
+	double bandwidth;
+
+	struct xe_buffer cmd_buf = {
+			.fd = fd,
+			.gpu_addr = (void *)(uintptr_t)gpu_va,
+			.vm = vm,
+			.size = bo_size,
+			.placement = vram_if_possible(fd, eci->gt_id),
+			.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	igt_gettime(&start_time);
+	dst = aligned_alloc(xe_get_default_alignment(fd), size);
+
+	xe_create_cmdbuf_fill_two_dw(&cmd_buf, insert_memset, (uint64_t)dst, (uint64_t)size, 0x12, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst, 0x12121212);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+
+	bandwidth = (double)(size>>20)*NSEC_PER_SEC/igt_nsec_elapsed(&start_time);
+	igt_info("engine class %d, engine id %d memset E2E bandwidth(include sync overhead) %.3f MiB/s\n", eci->engine_class, eci->engine_instance, bandwidth);
+}
+
 igt_main
 {
 	int fd;
@@ -341,6 +385,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_invalid_va(fd, vm, hwe);
 
+	igt_subtest_f("svm-benchmark")
+		xe_for_each_engine(fd, hwe)
+			svm_benchmark(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

RE: [PATCH i-g-t v3 08/10] tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance with a simple benchmark

[Zeng, Oak]

> -----Original Message-----
> From: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Sent: Friday, May 17, 2024 7:47 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH i-g-t v3 08/10] tests/intel/xe_svm: Add svm-benchmark test to
> measure SVM performance with a simple benchmark
> 
> svm-benchmark test provides a basic benchmark to compare the performance
> of
> system allocators against runtime allocators in SVM scenarios.

In the i915 igt, we have a similar benchmark test for runtime allocator, thus above description.

In xekmd igt, right now we don't have a corresponding runtime allocator benchmark test. So we need to modify above description. 

> 
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  lib/xe/xe_util.c     | 34 +++++++++++++++++++++++++++++++
>  lib/xe/xe_util.h     |  5 +++++
>  tests/intel/xe_svm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 87 insertions(+)
> 
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index 672e9dcef..c19cdae0c 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -128,6 +128,24 @@ void insert_atomic_inc(uint32_t *batch, uint64_t
> dst_va, uint32_t val)
>  	batch[++i] = MI_BATCH_BUFFER_END;
>  }
> 
> +/** Insert commands to batch buffer to memset dst_va buffer with val
> + */
> +void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t
> val)
> +{
> +#define PVC_MEM_SET_CMD		(2 << 29 | 0x5b << 22)
> +#define MS_MATRIX		(1 << 17)
> +	const int page_shift = 12;
> +
> +	*batch++ = PVC_MEM_SET_CMD | MS_MATRIX | (7 - 2);
> +	*batch++ = BIT(page_shift) - 1;
> +	*batch++ = (size >> page_shift) - 1;
> +	*batch++ = BIT(page_shift) - 1;
> +	*batch++ = lower_32_bits(dst_va);
> +	*batch++ = upper_32_bits(dst_va);
> +	*batch++ = (uint32_t)val << 24;
> +	*batch++ = MI_BATCH_BUFFER_END;
> +}
> +
>  /**
>   * Creates a command buffer, fills it with commands using the provided fill
>   * function, and sets up the execution queue for submission.
> @@ -143,6 +161,22 @@ void xe_create_cmdbuf(struct xe_buffer *cmd_buf,
> cmdbuf_fill_func_t fill_func, u
>  	fill_func(cmd_buf->cpu_addr, dst_va, val);
>  }
> 
> +/**
> + * Create a command buffer and fill it with a two-DW command function.
> + */
> +void xe_create_cmdbuf_fill_two_dw(struct xe_buffer *cmd_buf,
> cmdbuf_fill_two_dw_func_t fill_func,
> +		uint64_t dst_va, uint64_t dst_va1, uint32_t val, struct
> drm_xe_engine_class_instance *eci)
> +{
> +	//make some room for a exec_ufence, which will be used to sync the
> +	//submission of this command....
> +
> +	cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size +
> PAGE_ALIGN_UFENCE);
> +	xe_create_buffer(cmd_buf);
> +	cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd,
> cmd_buf->vm, eci, 0);
> +	fill_func(cmd_buf->cpu_addr, dst_va, dst_va1, val);
> +}
> +
> +
>  /**
>   * Destroys a command buffer created by xe_create_cmdbuf and releases
>   * associated resources.
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index 46e1ccc9a..50f2a4bc4 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -34,13 +34,18 @@ struct xe_buffer {
>  };
> 
>  typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va,
> uint32_t val);
> +typedef void (*cmdbuf_fill_two_dw_func_t) (uint32_t *batch, uint64_t
> dst_gpu_va,
> +		uint64_t dst_gpu_va1, uint32_t val);
>  void xe_create_buffer(struct xe_buffer *buffer);
>  void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
>  		uint64_t dst_va, uint32_t val, struct
> drm_xe_engine_class_instance *eci);
> +void xe_create_cmdbuf_fill_two_dw(struct xe_buffer *cmd_buf,
> cmdbuf_fill_two_dw_func_t fill_func,
> +		uint64_t dst_va, uint64_t dst_va1, uint32_t val, struct
> drm_xe_engine_class_instance *eci);
>  uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
>  uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
>  void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
>  void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
> +void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t
> val);
>  void xe_submit_cmd(struct xe_buffer *cmdbuf);
>  int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
>  void xe_destroy_buffer(struct xe_buffer *buffer);
> diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
> index 895cf26ac..072a602b1 100644
> --- a/tests/intel/xe_svm.c
> +++ b/tests/intel/xe_svm.c
> @@ -39,6 +39,9 @@
>   *
>   * SUBTEST: svm-invalid-va
>   * Description: Verify SVM functionality while accessing an invalid address.
> + *
> + * SUBTEST: svm-benchmark
> + * Description: Verify SVM performance with a simple benchmark test.
>   */
> 
>  #include <fcntl.h>
> @@ -301,6 +304,47 @@ static void svm_invalid_va(int fd, uint32_t vm, struct
> drm_xe_engine_class_insta
>  	free(dst);
>  }
> 
> +/**
> + * A simple benchmark test.
> + * Uses the GPU to memset a buffer with a specific value and measures the
> end-to-end bandwidth.
> + * This provides a basic comparison of the performance between the system
> allocator and the runtime allocator.

Change the description as well, remove runtme allocator

Oak
> + *
> + * By comparing the output of those two tests, we can have
> + * a very basic concept of the performance of sytem allocator
> + * compared to runtime allocator.
> + */
> +static void svm_benchmark(int fd, uint32_t vm, struct
> drm_xe_engine_class_instance *eci)
> +{
> +	uint64_t gpu_va = 0x1a0000;
> +	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
> +	uint32_t *dst, size = 1 << 26;
> +	struct timespec start_time;
> +	double bandwidth;
> +
> +	struct xe_buffer cmd_buf = {
> +			.fd = fd,
> +			.gpu_addr = (void *)(uintptr_t)gpu_va,
> +			.vm = vm,
> +			.size = bo_size,
> +			.placement = vram_if_possible(fd, eci->gt_id),
> +			.flag =
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
> +	};
> +
> +	igt_gettime(&start_time);
> +	dst = aligned_alloc(xe_get_default_alignment(fd), size);
> +
> +	xe_create_cmdbuf_fill_two_dw(&cmd_buf, insert_memset,
> (uint64_t)dst, (uint64_t)size, 0x12, eci);
> +	xe_submit_cmd(&cmd_buf);
> +
> +	igt_assert_eq(*dst, 0x12121212);
> +
> +	xe_destroy_cmdbuf(&cmd_buf);
> +	free(dst);
> +
> +	bandwidth =
> (double)(size>>20)*NSEC_PER_SEC/igt_nsec_elapsed(&start_time);
> +	igt_info("engine class %d, engine id %d memset E2E bandwidth(include
> sync overhead) %.3f MiB/s\n", eci->engine_class, eci->engine_instance,
> bandwidth);
> +}
> +
>  igt_main
>  {
>  	int fd;
> @@ -341,6 +385,10 @@ igt_main
>  		xe_for_each_engine(fd, hwe)
>  			svm_invalid_va(fd, vm, hwe);
> 
> +	igt_subtest_f("svm-benchmark")
> +		xe_for_each_engine(fd, hwe)
> +			svm_benchmark(fd, vm, hwe);
> +
>  	igt_fixture {
>  		xe_vm_destroy(fd, vm);
>  		drm_close_driver(fd);
> --
> 2.25.1

[PATCH i-g-t v3 09/10] tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality with read-only memory access

[Bommu Krishnaiah]

svm-mprotect test ensures that the driver correctly handles invalid
GPU write attempts to read-only memory regions in the context of SVM scenarios.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 tests/intel/xe_svm.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 072a602b1..86c9e86b8 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -42,6 +42,9 @@
  *
  * SUBTEST: svm-benchmark
  * Description: Verify SVM performance with a simple benchmark test.
+ *
+ * SUBTEST: svm-mprotect
+ * Description: verify SVM functionality while accessing read only memory
  */
 
 #include <fcntl.h>
@@ -345,6 +348,38 @@ static void svm_benchmark(int fd, uint32_t vm, struct drm_xe_engine_class_instan
 	igt_info("engine class %d, engine id %d memset E2E bandwidth(include sync overhead) %.3f MiB/s\n", eci->engine_class, eci->engine_instance, bandwidth);
 }
 
+/**
+ * Use mprotect to mark a chunk of memory to be read only and submit
+ * GPU command to write to this read only memory. GPU write should
+ * fail and driver should detect an invalid access error.
+ */
+static void svm_mprotect(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t *dst;
+	uint32_t size = 65536;
+
+	struct xe_buffer cmd_buf = {
+			.fd = fd,
+			.gpu_addr = (void *)(uintptr_t)gpu_va,
+			.vm = vm,
+			.size = bo_size,
+			.placement = vram_if_possible(fd, eci->gt_id),
+			.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	dst = aligned_alloc(size, size);
+	mprotect(dst, size, PROT_READ);
+
+	xe_create_cmdbuf(&cmd_buf, insert_store, (uint64_t)dst, 0xc0ffee, eci);
+
+	igt_assert_eq(__xe_submit_cmd(&cmd_buf), -EIO);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -389,6 +424,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_benchmark(fd, vm, hwe);
 
+	igt_subtest_f("svm-mprotect")
+		xe_for_each_engine(fd, hwe)
+			svm_mprotect(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

[PATCH i-g-t v3 10/10] tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely accessing two memory locations with SVM

[Bommu Krishnaiah]

svm-sparse-access verifies the functionality of sparsely accessing two memory locations using SVM

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 lib/xe/xe_util.c     | 18 ++++++++++++++++++
 lib/xe/xe_util.h     |  1 +
 tests/intel/xe_svm.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)

diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index c19cdae0c..217d3fa1b 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -146,6 +146,24 @@ void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val
 	*batch++ = MI_BATCH_BUFFER_END;
 }
 
+/**
+ * Insert commands to batch buffer to store values in two memory locations.
+ */
+void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val)
+{
+	int i = 0;
+
+	batch[i] = MI_STORE_DWORD_IMM;
+	batch[++i] = dst_va;
+	batch[++i] = dst_va >> 32;
+	batch[++i] = val;
+	batch[++i] = MI_STORE_DWORD_IMM;
+	batch[++i] = dst_va1;
+	batch[++i] = dst_va1 >> 32;
+	batch[++i] = val;
+	batch[++i] = MI_BATCH_BUFFER_END;
+}
+
 /**
  * Creates a command buffer, fills it with commands using the provided fill
  * function, and sets up the execution queue for submission.
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 50f2a4bc4..f463cca3b 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -46,6 +46,7 @@ uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
 void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val);
+void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val);
 void xe_submit_cmd(struct xe_buffer *cmdbuf);
 int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
 void xe_destroy_buffer(struct xe_buffer *buffer);
diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 86c9e86b8..0bdc1cc1e 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -45,6 +45,9 @@
  *
  * SUBTEST: svm-mprotect
  * Description: verify SVM functionality while accessing read only memory
+ *
+ * SUBTEST: svm-sparse-access
+ * Description: verify Sparsely access two memory locations with svm
  */
 
 #include <fcntl.h>
@@ -380,6 +383,39 @@ static void svm_mprotect(int fd, uint32_t vm, struct drm_xe_engine_class_instanc
 	free(dst);
 }
 
+/**
+ *  Sparsely access two memory locations
+ */
+static void svm_sparse_access(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t size = 1024*1024, sz_dw = size/4;
+	uint32_t *dst, *dst_to_access, *dst_to_access1;
+
+	struct xe_buffer cmd_buf = {
+			.fd = fd,
+			.gpu_addr = (void *)(uintptr_t)gpu_va,
+			.vm = vm,
+			.size = bo_size,
+			.placement = vram_if_possible(fd, eci->gt_id),
+			.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	dst = malloc(size);
+	dst_to_access = dst + (sz_dw>>1);
+	dst_to_access1 = dst + (sz_dw>>2);
+
+	xe_create_cmdbuf_fill_two_dw(&cmd_buf, insert_two_stores, (uint64_t)dst_to_access, (uint64_t)dst_to_access1, 0xc0ffee, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst_to_access, 0xc0ffee);
+	igt_assert_eq(*dst_to_access1, 0xc0ffee);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -428,6 +464,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_mprotect(fd, vm, hwe);
 
+	igt_subtest_f("svm-sparse-access")
+		xe_for_each_engine(fd, hwe)
+			svm_sparse_access(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1

✗ GitLab.Pipeline: warning for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Patchwork]

== Series Details ==

Series: tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)
URL   : https://patchwork.freedesktop.org/series/133746/
State : warning

== Summary ==

Pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1179970 for the overview.

build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/58868527):
                                                                                                             ^
  ../lib/xe/xe_util.c: In function ‘xe_destroy_buffer’:
  ../lib/xe/xe_util.c:90:15: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    sync->addr = (uint64_t)buffer->bind_ufence;
                 ^
  ../lib/xe/xe_util.c:92:68: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
                                                                      ^
  ../lib/xe/xe_util.c: In function ‘xe_cmdbuf_exec_ufence_gpuva’:
  ../lib/xe/xe_util.c:215:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
           ^
  cc1: some warnings being treated as errors
  ninja: build stopped: subcommand failed.
  section_end:1715949053:step_script
  section_start:1715949053:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1715949054:cleanup_file_variables
  ERROR: Job failed: exit code 1
  

build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/58868529):
                                                                                                             ^
  ../lib/xe/xe_util.c: In function ‘xe_destroy_buffer’:
  ../lib/xe/xe_util.c:90:15: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    sync->addr = (uint64_t)buffer->bind_ufence;
                 ^
  ../lib/xe/xe_util.c:92:68: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
                                                                      ^
  ../lib/xe/xe_util.c: In function ‘xe_cmdbuf_exec_ufence_gpuva’:
  ../lib/xe/xe_util.c:215:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
           ^
  cc1: some warnings being treated as errors
  ninja: build stopped: subcommand failed.
  section_end:1715949058:step_script
  section_start:1715949058:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1715949059:cleanup_file_variables
  ERROR: Job failed: exit code 1

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1179970

✓ CI.xeBAT: success for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1929 bytes --]

== Series Details ==

Series: tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)
URL   : https://patchwork.freedesktop.org/series/133746/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7860_BAT -> XEIGTPW_11155_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (5 -> 5)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_11155_BAT that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-7:         [FAIL][1] ([Intel XE#1861]) -> [DMESG-FAIL][2] ([Intel XE#324])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
  [Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324


Build changes
-------------

  * IGT: IGT_7860 -> IGTPW_11155
  * Linux: xe-1302-f5b1f5e83aca888ada6cf909735023349a73d3df -> xe-1305-8ef53c10d150679e3ff5db00d128417dfffb7798

  IGTPW_11155: 11155
  IGT_7860: 05b3f5540c6dcaacdf2169dc730c126df9ffd7e2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1302-f5b1f5e83aca888ada6cf909735023349a73d3df: f5b1f5e83aca888ada6cf909735023349a73d3df
  xe-1305-8ef53c10d150679e3ff5db00d128417dfffb7798: 8ef53c10d150679e3ff5db00d128417dfffb7798

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/index.html

[-- Attachment #2: Type: text/html, Size: 2433 bytes --]

✓ Fi.CI.BAT: success for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5688 bytes --]

== Series Details ==

Series: tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)
URL   : https://patchwork.freedesktop.org/series/133746/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14780 -> IGTPW_11155
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/index.html

Participating hosts (44 -> 43)
------------------------------

  Additional (1): fi-cfl-8109u 
  Missing    (2): fi-snb-2520m fi-elk-e7500 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11155:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_busy@basic@modeset:
    - {bat-mtlp-9}:       [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/bat-mtlp-9/igt@kms_busy@basic@modeset.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/bat-mtlp-9/igt@kms_busy@basic@modeset.html

  
Known issues
------------

  Here are the changes found in IGTPW_11155 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_module_load@load:
    - bat-arls-3:         [PASS][5] -> [ABORT][6] ([i915#11041])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/bat-arls-3/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/bat-arls-3/igt@i915_module_load@load.html

  * igt@kms_dsc@dsc-basic:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][7] +11 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/fi-cfl-8109u/igt@kms_dsc@dsc-basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@dmabuf:
    - {bat-mtlp-9}:       [DMESG-FAIL][8] ([i915#11035]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/bat-mtlp-9/igt@i915_selftest@live@dmabuf.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/bat-mtlp-9/igt@i915_selftest@live@dmabuf.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [ABORT][10] ([i915#10594]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_flip@basic-flip-vs-modeset@b-dp7:
    - {bat-mtlp-9}:       [DMESG-WARN][12] ([i915#10435]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@b-dp7.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@b-dp7.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1:
    - {bat-rpls-4}:       [DMESG-WARN][14] ([i915#9970]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/bat-rpls-4/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/bat-rpls-4/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html

  
#### Warnings ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-kbl-7567u:       [DMESG-WARN][16] ([i915#180] / [i915#8585] / [i915#9925]) -> [DMESG-WARN][17] ([i915#180] / [i915#1982] / [i915#8585] / [i915#9925])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/fi-kbl-7567u/igt@core_hotunplug@unbind-rebind.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/fi-kbl-7567u/igt@core_hotunplug@unbind-rebind.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
  [i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
  [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
  [i915#11035]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11035
  [i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#8585]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8585
  [i915#9925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9925
  [i915#9970]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9970


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7860 -> IGTPW_11155

  CI-20190529: 20190529
  CI_DRM_14780: 8ef53c10d150679e3ff5db00d128417dfffb7798 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11155: 11155
  IGT_7860: 05b3f5540c6dcaacdf2169dc730c126df9ffd7e2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/index.html

[-- Attachment #2: Type: text/html, Size: 6602 bytes --]

✗ CI.xeFULL: failure for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 75073 bytes --]

== Series Details ==

Series: tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)
URL   : https://patchwork.freedesktop.org/series/133746/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_7860_full -> XEIGTPW_11155_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11155_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11155_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 2)
------------------------------

  Missing    (1): shard-adlp 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11155_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-suspend-interruptible@d-dp4:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible@d-dp4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible@d-dp4.html

  * {igt@xe_svm@svm-benchmark} (NEW):
    - shard-dg2-set2:     NOTRUN -> [FAIL][3] +8 other tests fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@xe_svm@svm-benchmark.html

  * {igt@xe_svm@svm-mprotect} (NEW):
    - {shard-lnl}:        NOTRUN -> [SKIP][4] +6 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-8/igt@xe_svm@svm-mprotect.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [DMESG-WARN][5] ([Intel XE#1162] / [Intel XE#1214]) -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_addfb_basic@unused-pitches:
    - {shard-lnl}:        NOTRUN -> [SKIP][7]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-8/igt@kms_addfb_basic@unused-pitches.html

  
New tests
---------

  New tests have been introduced between XEIGT_7860_full and XEIGTPW_11155_full:

### New IGT tests (10) ###

  * igt@xe_svm@svm-atomic-access:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-basic-malloc:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-basic-mmap:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-benchmark:
    - Statuses : 1 fail(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-huge-page:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-invalid-va:
    - Statuses : 1 fail(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-mprotect:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-random-access:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@svm-sparse-access:
    - Statuses : 1 fail(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_svm@xe-basic:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11155_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotrebind:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][8] ([Intel XE#1548])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@core_hotunplug@hotrebind.html

  * igt@core_setmaster@master-drop-set-root:
    - shard-dg2-set2:     [PASS][9] -> [DMESG-WARN][10] ([Intel XE#1162] / [Intel XE#1214]) +1 other test dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@core_setmaster@master-drop-set-root.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@core_setmaster@master-drop-set-root.html

  * igt@kms_addfb_basic@unused-pitches:
    - shard-dg2-set2:     [PASS][11] -> [SKIP][12] ([Intel XE#1201] / [i915#6077])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_addfb_basic@unused-pitches.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_addfb_basic@unused-pitches.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#316])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#1201] / [Intel XE#829]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#787]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#787]) +6 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-dp-4.html

  * igt@kms_cdclk@mode-transition@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#314]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_cdclk@mode-transition@pipe-c-dp-4.html

  * igt@kms_cdclk@plane-scaling:
    - shard-dg2-set2:     [PASS][22] -> [SKIP][23] ([Intel XE#1201] / [Intel XE#1234]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_cdclk@plane-scaling.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_cdclk@plane-scaling.html

  * igt@kms_color@ctm-0-75:
    - shard-dg2-set2:     [PASS][24] -> [SKIP][25] ([Intel XE#1201]) +15 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_color@ctm-0-75.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_color@ctm-0-75.html

  * igt@kms_cursor_crc@cursor-dpms:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][26] ([Intel XE#1214] / [Intel XE#282]) +2 other tests dmesg-warn
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_cursor_crc@cursor-dpms.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-dg2-set2:     [PASS][27] -> [SKIP][28] ([Intel XE#1201] / [Intel XE#1235])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-dg2-set2:     [PASS][29] -> [DMESG-WARN][30] ([Intel XE#1214] / [Intel XE#282]) +2 other tests dmesg-warn
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([i915#3804])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#1137] / [Intel XE#1201])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-dg2-set2:     [PASS][33] -> [INCOMPLETE][34] ([Intel XE#1195]) +2 other tests incomplete
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#651]) +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#651])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#1201]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#653]) +4 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-dg2-set2:     [PASS][39] -> [SKIP][40] ([Intel XE#1201] / [Intel XE#417])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_hdmi_inject@inject-audio.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats:
    - shard-dg2-set2:     NOTRUN -> [TIMEOUT][41] ([Intel XE#295] / [Intel XE#380] / [Intel XE#909])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [TIMEOUT][42] ([Intel XE#904] / [Intel XE#909])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-hdmi-a-6.html

  * igt@kms_prop_blob@invalid-set-prop:
    - shard-dg2-set2:     [PASS][43] -> [SKIP][44] ([Intel XE#1201] / [Intel XE#780])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_prop_blob@invalid-set-prop.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_prop_blob@invalid-set-prop.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#1201] / [Intel XE#929]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#929])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_psr@fbc-psr-primary-render.html

  * igt@kms_rotation_crc@sprite-rotation-180:
    - shard-dg2-set2:     [PASS][47] -> [SKIP][48] ([Intel XE#1201] / [Intel XE#829]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_rotation_crc@sprite-rotation-180.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_rotation_crc@sprite-rotation-180.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#1091] / [Intel XE#1201])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@sriov_basic@bind-unbind-vf.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [PASS][50] -> [FAIL][51] ([Intel XE#1600])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#1201] / [Intel XE#288]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch.html

  * igt@xe_exec_threads@threads-hang-shared-vm-userptr:
    - shard-dg2-set2:     [PASS][53] -> [DMESG-WARN][54] ([Intel XE#1214] / [Intel XE#358])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@xe_exec_threads@threads-hang-shared-vm-userptr.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@xe_exec_threads@threads-hang-shared-vm-userptr.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-basic:
    - shard-dg2-set2:     [PASS][55] -> [INCOMPLETE][56] ([Intel XE#1169] / [Intel XE#1195] / [Intel XE#1356])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html

  * igt@xe_media_fill@media-fill:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#1201] / [Intel XE#560])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@xe_media_fill@media-fill.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#1201] / [Intel XE#979])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#1201] / [Intel XE#366])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@xe_pm@d3cold-multiple-execs.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - {shard-lnl}:        [SKIP][60] ([Intel XE#1134]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color@deep-color:
    - shard-dg2-set2:     [INCOMPLETE][62] ([Intel XE#1150] / [Intel XE#1195]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_color@deep-color.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_color@deep-color.html

  * igt@kms_color@deep-color@pipe-b-hdmi-a-6-ctm:
    - shard-dg2-set2:     [INCOMPLETE][64] ([Intel XE#1195]) -> [PASS][65] +2 other tests pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_color@deep-color@pipe-b-hdmi-a-6-ctm.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_color@deep-color@pipe-b-hdmi-a-6-ctm.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-dg2-set2:     [DMESG-WARN][66] ([Intel XE#1214] / [Intel XE#282] / [Intel XE#910]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-dg2-set2:     [DMESG-WARN][68] ([Intel XE#1214] / [Intel XE#282]) -> [PASS][69] +2 other tests pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_cursor_legacy@forked-bo@all-pipes:
    - shard-dg2-set2:     [DMESG-WARN][70] ([Intel XE#282]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_cursor_legacy@forked-bo@all-pipes.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_cursor_legacy@forked-bo@all-pipes.html

  * igt@kms_flip@absolute-wf_vblank-interruptible:
    - shard-dg2-set2:     [SKIP][72] ([Intel XE#1201]) -> [PASS][73] +1 other test pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_flip@absolute-wf_vblank-interruptible.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_flip@absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - {shard-lnl}:        [DMESG-WARN][74] ([Intel XE#1830]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-3/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-4/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][76] ([Intel XE#1201] / [Intel XE#1234]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_plane@plane-position-hole-dpms:
    - {shard-lnl}:        [INCOMPLETE][78] ([Intel XE#1330] / [Intel XE#1602] / [Intel XE#1760]) -> [PASS][79] +1 other test pass
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@kms_plane@plane-position-hole-dpms.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-1/igt@kms_plane@plane-position-hole-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - {shard-lnl}:        [FAIL][80] ([Intel XE#718]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-6/igt@kms_pm_dc@dc5-psr.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - {shard-lnl}:        [SKIP][82] -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@kms_pm_rpm@basic-pci-d3-state.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-4/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_prop_blob@basic:
    - {shard-lnl}:        [SKIP][84] ([Intel XE#1733]) -> [PASS][85] +2 other tests pass
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@kms_prop_blob@basic.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-4/igt@kms_prop_blob@basic.html

  * igt@xe_evict@evict-beng-cm-threads-large:
    - shard-dg2-set2:     [TIMEOUT][86] ([Intel XE#1473] / [Intel XE#392]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@xe_evict@evict-beng-cm-threads-large.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@xe_evict@evict-beng-cm-threads-large.html

  * igt@xe_evict@evict-beng-mixed-threads-large:
    - shard-dg2-set2:     [TIMEOUT][88] ([Intel XE#1473]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@xe_evict@evict-beng-mixed-threads-large.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_evict@evict-beng-mixed-threads-large.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-dg2-set2:     [INCOMPLETE][90] ([Intel XE#1195] / [Intel XE#1473]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@xe_evict@evict-mixed-many-threads-small.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - {shard-lnl}:        [SKIP][92] ([Intel XE#1699]) -> [PASS][93] +7 other tests pass
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-1/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_gt_freq@freq_low_max:
    - shard-dg2-set2:     [FAIL][94] ([Intel XE#1045] / [Intel XE#1204]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@xe_gt_freq@freq_low_max.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@xe_gt_freq@freq_low_max.html

  * igt@xe_live_ktest@xe_migrate:
    - shard-dg2-set2:     [SKIP][96] ([Intel XE#1192] / [Intel XE#1201]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@xe_live_ktest@xe_migrate.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@xe_live_ktest@xe_migrate.html

  * igt@xe_module_load@many-reload:
    - shard-dg2-set2:     [DMESG-WARN][98] ([Intel XE#1214]) -> [PASS][99] +1 other test pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@xe_module_load@many-reload.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@xe_module_load@many-reload.html

  * igt@xe_module_load@reload-no-display:
    - {shard-lnl}:        [ABORT][100] ([Intel XE#1602] / [Intel XE#1689] / [Intel XE#1760]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@xe_module_load@reload-no-display.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-8/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@s3-basic-exec:
    - shard-dg2-set2:     [DMESG-WARN][102] ([Intel XE#1162] / [Intel XE#1214]) -> [PASS][103] +3 other tests pass
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@xe_pm@s3-basic-exec.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@xe_pm@s3-basic-exec.html

  * igt@xe_vm@shared-pde3-page:
    - {shard-lnl}:        [SKIP][104] ([Intel XE#1130] / [Intel XE#1699]) -> [PASS][105] +2 other tests pass
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-lnl-2/igt@xe_vm@shared-pde3-page.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-lnl-8/igt@xe_vm@shared-pde3-page.html

  
#### Warnings ####

  * igt@core_hotunplug@hotreplug-lateclose:
    - shard-dg2-set2:     [DMESG-FAIL][106] ([Intel XE#1162] / [Intel XE#1548]) -> [DMESG-FAIL][107] ([Intel XE#1548]) +1 other test dmesg-fail
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@core_hotunplug@hotreplug-lateclose.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@core_hotunplug@hotreplug-lateclose.html

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-dg2-set2:     [DMESG-FAIL][108] ([Intel XE#1162] / [Intel XE#1345] / [Intel XE#1548]) -> [DMESG-FAIL][109] ([Intel XE#1345] / [Intel XE#1548])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@core_hotunplug@hotunplug-rescan.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@core_hotunplug@hotunplug-rescan.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2-set2:     [SKIP][110] ([Intel XE#1201] / [Intel XE#623]) -> [SKIP][111] ([Intel XE#623])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2-set2:     [SKIP][112] ([Intel XE#873]) -> [SKIP][113] ([Intel XE#1201] / [Intel XE#873])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_async_flips@invalid-async-flip.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][114] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][115] ([Intel XE#1201] / [Intel XE#829]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][116] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][117] ([Intel XE#316]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][118] ([Intel XE#316]) -> [SKIP][119] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][120] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][121] ([Intel XE#1201] / [Intel XE#829]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-dg2-set2:     [SKIP][122] ([Intel XE#610]) -> [SKIP][123] ([Intel XE#1201] / [Intel XE#610])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     [SKIP][124] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][125] ([Intel XE#1124]) +6 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg2-set2:     [SKIP][126] ([Intel XE#1124]) -> [SKIP][127] ([Intel XE#1124] / [Intel XE#1201]) +5 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][128] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][129] ([Intel XE#367]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][130] ([Intel XE#367]) -> [SKIP][131] ([Intel XE#1201] / [Intel XE#367]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][132] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][133] ([Intel XE#1201] / [Intel XE#829]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][134] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][135] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [SKIP][136] ([Intel XE#787]) -> [SKIP][137] ([Intel XE#1201] / [Intel XE#787]) +27 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][138] ([Intel XE#1195]) -> [TIMEOUT][139] ([Intel XE#1850])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][140] ([Intel XE#1195]) -> [TIMEOUT][141] ([Intel XE#1713])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][142] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][143] ([Intel XE#787]) +48 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][144] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][145] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-dg2-set2:     [SKIP][146] ([Intel XE#306]) -> [SKIP][147] ([Intel XE#1201] / [Intel XE#306]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_chamelium_color@ctm-0-25.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@gamma:
    - shard-dg2-set2:     [SKIP][148] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][149] ([Intel XE#306]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_chamelium_color@gamma.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2-set2:     [SKIP][150] ([Intel XE#373]) -> [SKIP][151] ([Intel XE#1201] / [Intel XE#373]) +6 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-dg2-set2:     [SKIP][152] ([Intel XE#373]) -> [SKIP][153] ([Intel XE#1201])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-dg2-set2:     [SKIP][154] ([Intel XE#1201]) -> [SKIP][155] ([Intel XE#1201] / [Intel XE#373])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2-set2:     [SKIP][156] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][157] ([Intel XE#373]) +4 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2-set2:     [SKIP][158] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][159] ([Intel XE#307])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_content_protection@dp-mst-type-1.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     [SKIP][160] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][161] ([Intel XE#308]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-256x256:
    - shard-dg2-set2:     [DMESG-WARN][162] ([Intel XE#1214] / [Intel XE#282]) -> [SKIP][163] ([Intel XE#1201])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_cursor_crc@cursor-random-256x256.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_cursor_crc@cursor-random-256x256.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-set2:     [SKIP][164] ([Intel XE#308]) -> [SKIP][165] ([Intel XE#1201] / [Intel XE#308])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_cursor_crc@cursor-random-512x512.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-dg2-set2:     [SKIP][166] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][167] ([Intel XE#455]) +6 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_cursor_crc@cursor-random-max-size.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-dg2-set2:     [DMESG-FAIL][168] -> [DMESG-FAIL][169] ([Intel XE#1162])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_cursor_crc@cursor-suspend.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-FAIL][170] -> [FAIL][171] ([Intel XE#616])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-6.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][172] ([Intel XE#616]) -> [DMESG-FAIL][173] ([Intel XE#1162])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6.html

  * igt@kms_cursor_edge_walk@256x256-top-bottom:
    - shard-dg2-set2:     [DMESG-WARN][174] ([Intel XE#1214] / [Intel XE#282]) -> [FAIL][175] ([Intel XE#581])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_cursor_edge_walk@256x256-top-bottom.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_cursor_edge_walk@256x256-top-bottom.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [DMESG-WARN][176] ([Intel XE#1214] / [Intel XE#282]) -> [DMESG-WARN][177] ([Intel XE#282]) +6 other tests dmesg-warn
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@forked-bo@pipe-b:
    - shard-dg2-set2:     [DMESG-WARN][178] ([Intel XE#282]) -> [DMESG-WARN][179] ([Intel XE#1214] / [Intel XE#282]) +2 other tests dmesg-warn
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_cursor_legacy@forked-bo@pipe-b.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_cursor_legacy@forked-bo@pipe-b.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-set2:     [SKIP][180] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][181] ([Intel XE#323]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4:
    - shard-dg2-set2:     [SKIP][182] ([Intel XE#455] / [Intel XE#929]) -> [SKIP][183] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#929])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][184] -> [SKIP][185] ([Intel XE#1201])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a6-dp4:
    - shard-dg2-set2:     [DMESG-WARN][186] ([Intel XE#1162]) -> [DMESG-WARN][187] ([Intel XE#1162] / [Intel XE#1214]) +1 other test dmesg-warn
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a6-dp4.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a6-dp4.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [DMESG-WARN][188] ([Intel XE#1162] / [Intel XE#1214]) -> [INCOMPLETE][189] ([Intel XE#1195])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_flip@flip-vs-suspend.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6:
    - shard-dg2-set2:     [DMESG-WARN][190] ([Intel XE#1162] / [Intel XE#1214]) -> [DMESG-WARN][191] ([Intel XE#1162])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-dg2-set2:     [SKIP][192] ([Intel XE#455]) -> [SKIP][193] ([Intel XE#1201])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][194] ([Intel XE#455]) -> [SKIP][195] ([Intel XE#1201] / [Intel XE#455]) +15 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     [SKIP][196] ([Intel XE#651]) -> [SKIP][197] ([Intel XE#1201] / [Intel XE#651]) +17 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#658]) -> [SKIP][199] ([Intel XE#1201] / [Intel XE#658])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][201] ([Intel XE#1201] / [Intel XE#1234])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][203] ([Intel XE#1201]) +4 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][205] ([Intel XE#651]) +16 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#653]) -> [SKIP][207] ([Intel XE#1201]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#1201]) -> [SKIP][209] ([Intel XE#1201] / [Intel XE#653])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][211] ([Intel XE#1201]) +4 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2-set2:     [SKIP][212] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][213] ([Intel XE#653]) +17 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][214] ([Intel XE#1201] / [Intel XE#1234]) -> [SKIP][215] ([Intel XE#1201] / [Intel XE#653])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#653]) -> [SKIP][217] ([Intel XE#1201] / [Intel XE#653]) +16 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][219] ([Intel XE#1201])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_hdr@invalid-hdr.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_hdr@invalid-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     [SKIP][220] ([Intel XE#356]) -> [SKIP][221] ([Intel XE#1201] / [Intel XE#356])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#455] / [Intel XE#498]) -> [SKIP][223] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) +1 other test skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][224] ([Intel XE#498]) -> [SKIP][225] ([Intel XE#1201] / [Intel XE#498]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-6.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-6.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format:
    - shard-dg2-set2:     [TIMEOUT][226] ([Intel XE#380] / [Intel XE#904] / [Intel XE#909]) -> [INCOMPLETE][227] ([Intel XE#1195] / [Intel XE#904] / [Intel XE#909])
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [TIMEOUT][228] ([Intel XE#904] / [Intel XE#909]) -> [INCOMPLETE][229] ([Intel XE#1195] / [Intel XE#904] / [Intel XE#909])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a-hdmi-a-6.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#1201] / [Intel XE#305]) -> [SKIP][231] ([Intel XE#305]) +2 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455]) -> [SKIP][233] ([Intel XE#305] / [Intel XE#455]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-dg2-set2:     [SKIP][234] ([Intel XE#305] / [Intel XE#455]) -> [SKIP][235] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455]) +1 other test skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][236] ([Intel XE#305]) -> [SKIP][237] ([Intel XE#1201] / [Intel XE#305]) +5 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     [SKIP][238] ([Intel XE#1201] / [Intel XE#870]) -> [SKIP][239] ([Intel XE#870])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_pm_backlight@bad-brightness.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-dg2-set2:     [SKIP][240] ([Intel XE#870]) -> [SKIP][241] ([Intel XE#1201] / [Intel XE#870])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_pm_backlight@fade-with-suspend.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-set2:     [SKIP][242] ([Intel XE#1122]) -> [SKIP][243] ([Intel XE#1122] / [Intel XE#1201])
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][245] ([Intel XE#929]) +11 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-434/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2-set2:     [SKIP][246] ([Intel XE#1122] / [Intel XE#1201]) -> [SKIP][247] ([Intel XE#1122])
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_psr2_su@page_flip-nv12.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#929]) -> [SKIP][249] ([Intel XE#1201] / [Intel XE#929]) +12 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr2-primary-blt:
    - shard-dg2-set2:     [SKIP][250] ([Intel XE#1201]) -> [SKIP][251] ([Intel XE#1201] / [Intel XE#929])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_psr@psr2-primary-blt.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_psr@psr2-primary-blt.html

  * igt@kms_psr@psr2-primary-render:
    - shard-dg2-set2:     [SKIP][252] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][253] ([Intel XE#1201]) +2 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-464/igt@kms_psr@psr2-primary-render.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_psr@psr2-primary-render.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2-set2:     [SKIP][254] ([Intel XE#1149] / [Intel XE#1201]) -> [SKIP][255] ([Intel XE#1149])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2-set2:     [SKIP][256] ([Intel XE#327]) -> [SKIP][257] ([Intel XE#1201] / [Intel XE#327]) +2 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@kms_rotation_crc@primary-rotation-270.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-433/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2-set2:     [SKIP][258] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][259] ([Intel XE#327])
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@kms_rotation_crc@sprite-rotation-90.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2-set2:     [SKIP][260] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][261] ([Intel XE#1201] / [Intel XE#829])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#1201] / [Intel XE#330]) -> [SKIP][263] ([Intel XE#330])
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@kms_tv_load_detect@load-detect.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flipline:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#1201]) -> [SKIP][265] ([Intel XE#1201] / [Intel XE#455])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@kms_vrr@flipline.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@kms_vrr@flipline.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][267] ([Intel XE#1091])
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@sriov_basic@enable-vfs-bind-unbind-each.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@xe_copy_basic@mem-copy-linear-0x369:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][269] ([Intel XE#1123])
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0x369.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0x369.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][270] ([Intel XE#1126] / [Intel XE#1201]) -> [SKIP][271] ([Intel XE#1126]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfffe.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-dg2-set2:     [TIMEOUT][272] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) -> [INCOMPLETE][273] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392])
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-large.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-434/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_evict@evict-beng-threads-large:
    - shard-dg2-set2:     [INCOMPLETE][274] ([Intel XE#1195] / [Intel XE#1473]) -> [TIMEOUT][275] ([Intel XE#1473])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-433/igt@xe_evict@evict-beng-threads-large.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@xe_evict@evict-beng-threads-large.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#288]) -> [SKIP][277] ([Intel XE#1201] / [Intel XE#288]) +15 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-463/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][279] ([Intel XE#288]) +15 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-463/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm.html

  * igt@xe_module_load@force-load:
    - shard-dg2-set2:     [SKIP][280] ([Intel XE#378]) -> [SKIP][281] ([Intel XE#1201] / [Intel XE#378])
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@xe_module_load@force-load.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-435/igt@xe_module_load@force-load.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][282] ([Intel XE#1201] / [Intel XE#1337]) -> [SKIP][283] ([Intel XE#1337])
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-436/igt@xe_pat@display-vs-wb-transient.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-dg2-set2:     [DMESG-WARN][284] ([Intel XE#1162] / [Intel XE#1214]) -> [INCOMPLETE][285] ([Intel XE#1195] / [Intel XE#569])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-435/igt@xe_pm@s3-vm-bind-userptr.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-436/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_query@multigpu-query-config:
    - shard-dg2-set2:     [SKIP][286] ([Intel XE#944]) -> [SKIP][287] ([Intel XE#1201] / [Intel XE#944]) +3 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-432/igt@xe_query@multigpu-query-config.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-464/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-dg2-set2:     [SKIP][288] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][289] ([Intel XE#944])
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7860/shard-dg2-466/igt@xe_query@multigpu-query-invalid-size.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/shard-dg2-432/igt@xe_query@multigpu-query-invalid-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041
  [Intel XE#1045]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1045
  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1134
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149
  [Intel XE#1150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1150
  [Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162
  [Intel XE#1169]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1169
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
  [Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214
  [Intel XE#1234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1234
  [Intel XE#1235]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1235
  [Intel XE#1330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1330
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1345
  [Intel XE#1356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1356
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
  [Intel XE#1446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1446
  [Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1483
  [Intel XE#1494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1494
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1548
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1602]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1602
  [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620
  [Intel XE#1641]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1641
  [Intel XE#1650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1650
  [Intel XE#1663]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1663
  [Intel XE#1689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1689
  [Intel XE#1699]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1699
  [Intel XE#1713]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1713
  [Intel XE#1717]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1717
  [Intel XE#1725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1725
  [Intel XE#1731]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1731
  [Intel XE#1733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1733
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
  [Intel XE#1761]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1761
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1830
  [Intel XE#1850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1850
  [Intel XE#282]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/282
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#295]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/295
  [Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/358
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/380
  [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392
  [Intel XE#417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/417
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#581]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/581
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/780
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#829]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/829
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/904
  [Intel XE#909]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/909
  [Intel XE#910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/910
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077


Build changes
-------------

  * IGT: IGT_7860 -> IGTPW_11155
  * Linux: xe-1302-f5b1f5e83aca888ada6cf909735023349a73d3df -> xe-1305-8ef53c10d150679e3ff5db00d128417dfffb7798

  IGTPW_11155: 11155
  IGT_7860: 05b3f5540c6dcaacdf2169dc730c126df9ffd7e2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1302-f5b1f5e83aca888ada6cf909735023349a73d3df: f5b1f5e83aca888ada6cf909735023349a73d3df
  xe-1305-8ef53c10d150679e3ff5db00d128417dfffb7798: 8ef53c10d150679e3ff5db00d128417dfffb7798

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11155/index.html

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✗ Fi.CI.IGT: failure for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Patchwork]

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== Series Details ==

Series: tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)
URL   : https://patchwork.freedesktop.org/series/133746/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14780_full -> IGTPW_11155_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11155_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11155_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/index.html

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11155_full:

### IGT changes ###

#### Possible regressions ####

  * igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_clear:
    - shard-dg1:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_clear.html

  * igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_range_bias:
    - shard-dg1:          NOTRUN -> [DMESG-FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_range_bias.html

  * igt@sysfs_preempt_timeout@timeout@rcs0:
    - shard-dg2:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-6/igt@sysfs_preempt_timeout@timeout@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@sysfs_preempt_timeout@timeout@rcs0.html

  
Known issues
------------

  Here are the changes found in IGTPW_11155_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#8411])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][7] ([i915#10380])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@api_intel_bb@render-ccs.html

  * igt@debugfs_test@basic-hwmon:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#9318])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-1/igt@debugfs_test@basic-hwmon.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#11078])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu:         NOTRUN -> [SKIP][10] ([i915#11078])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@device_reset@unbind-cold-reset-rebind.html
    - shard-dg2:          NOTRUN -> [SKIP][11] ([i915#11078])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][12] ([i915#7742]) +1 other test fail
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-6/igt@drm_fdinfo@idle@rcs0.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#8414]) +6 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@gem_basic@multigpu-create-close:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#7697])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@gem_basic@multigpu-create-close.html
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#7697])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@gem_basic@multigpu-create-close.html

  * igt@gem_caching@read-writes:
    - shard-mtlp:         NOTRUN -> [SKIP][16] ([i915#4873])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@gem_caching@read-writes.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#9323])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@gem_ccs@block-multicopy-compressed.html
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#9323])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-dg1:          NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9323])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg1:          NOTRUN -> [SKIP][20] ([i915#7697])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#6335])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@gem_create@create-ext-cpu-access-big.html
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#6335])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-1/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg1:          NOTRUN -> [SKIP][23] ([i915#8555]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_ctx_persistence@heartbeat-stop.html
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#8555])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#280])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#280])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@gem_ctx_sseu@invalid-sseu.html
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#280])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_ctx_sseu@invalid-sseu.html
    - shard-mtlp:         NOTRUN -> [SKIP][28] ([i915#280]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         [PASS][29] -> [ABORT][30] ([i915#10030] / [i915#7975] / [i915#8213])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-4/igt@gem_eio@hibernate.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-10/igt@gem_eio@hibernate.html

  * igt@gem_eio@kms:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][31] ([i915#10513] / [i915#1982])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#4771])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@hog:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#4812])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@gem_exec_balancer@hog.html

  * igt@gem_exec_capture@many-4k-incremental:
    - shard-dg2:          NOTRUN -> [FAIL][34] ([i915#9606]) +1 other test fail
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@gem_exec_capture@many-4k-incremental.html
    - shard-rkl:          NOTRUN -> [FAIL][35] ([i915#9606]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_exec_capture@many-4k-incremental.html

  * igt@gem_exec_capture@many-4k-zero:
    - shard-dg1:          NOTRUN -> [FAIL][36] ([i915#9606]) +1 other test fail
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_exec_capture@many-4k-zero.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4473] / [i915#4771])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][38] ([i915#2842])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-rkl:          [PASS][39] -> [FAIL][40] ([i915#2842]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [PASS][41] -> [FAIL][42] ([i915#2842])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-sync:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#3539])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@gem_exec_fair@basic-sync.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][44] ([i915#2842])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html
    - shard-tglu:         NOTRUN -> [FAIL][45] ([i915#2842])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_fence@submit:
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#4812])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-8/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
    - shard-dg1:          NOTRUN -> [SKIP][47] ([i915#3539] / [i915#4852]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_exec_flush@basic-batch-kernel-default-wb.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#3539] / [i915#4852]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_reloc@basic-cpu-read:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#3281]) +18 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@gem_exec_reloc@basic-cpu-read.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#3281]) +15 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
    - shard-dg1:          NOTRUN -> [SKIP][51] ([i915#3281]) +15 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_exec_reloc@basic-scanout:
    - shard-mtlp:         NOTRUN -> [SKIP][52] ([i915#3281]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@gem_exec_reloc@basic-scanout.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-dg1:          NOTRUN -> [SKIP][53] ([i915#4812]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_schedule@reorder-wide:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#4537] / [i915#4812]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@gem_exec_schedule@reorder-wide.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#7276])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_exec_suspend@basic-s4-devices@smem:
    - shard-rkl:          NOTRUN -> [ABORT][56] ([i915#7975] / [i915#8213])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@gem_exec_suspend@basic-s4-devices@smem.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#4860])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@gem_fenced_exec_thrash@2-spare-fences.html
    - shard-dg1:          NOTRUN -> [SKIP][58] ([i915#4860])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_fenced_exec_thrash@2-spare-fences.html

  * igt@gem_fenced_exec_thrash@too-many-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#4860]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@gem_fenced_exec_thrash@too-many-fences.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#4613]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random@lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][61] ([i915#10378])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_lmem_swapping@heavy-random@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          [PASS][62] -> [FAIL][63] ([i915#10378])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-glk:          NOTRUN -> [SKIP][64] ([i915#4613]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk6/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@random:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([i915#4613])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][66] -> [TIMEOUT][67] ([i915#5493])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-ccs@lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][68] ([i915#10378])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@gem_lmem_swapping@verify-ccs@lmem0.html

  * igt@gem_media_vme:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#284])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@gem_media_vme.html
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#284])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@gem_media_vme.html

  * igt@gem_mmap@bad-offset:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#4083]) +5 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@gem_mmap@bad-offset.html

  * igt@gem_mmap_gtt@coherency:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#4077]) +8 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_mmap_gtt@coherency.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#4077]) +6 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@copy:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#4083]) +5 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@set-cache-level:
    - shard-mtlp:         NOTRUN -> [SKIP][75] ([i915#4083]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gem_mmap_wc@set-cache-level.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#3282]) +5 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#3282]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@write-display:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#3282]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@gem_partial_pwrite_pread@write-display.html

  * igt@gem_pread@bench:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#3282]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@gem_pread@bench.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][80] ([i915#2658]) +1 other test warn
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk8/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#4270]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#4270])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@gem_pxp@reject-modify-context-protection-off-2.html
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#4270]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@gem_pxp@reject-modify-context-protection-off-2.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#4270]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#4270])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-7/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#8428]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#5190] / [i915#8428]) +8 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#4079]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_set_tiling_vs_gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][89] ([i915#4079])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gem_set_tiling_vs_gtt.html

  * igt@gem_softpin@evict-snoop:
    - shard-mtlp:         NOTRUN -> [SKIP][90] ([i915#4885])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@gem_softpin@evict-snoop.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#4885])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_partial_pwrite_pread@writes:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#4077]) +8 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@gem_tiled_partial_pwrite_pread@writes.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#4879])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#3297] / [i915#4880])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-dg1:          NOTRUN -> [SKIP][95] ([i915#3297]) +4 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#2527] / [i915#2856])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-9/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#2856]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-10/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#2527]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-mtlp:         NOTRUN -> [SKIP][99] ([i915#2856]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@gen9_exec_parse@unaligned-jump.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#2527]) +2 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_module_load@load:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#6227])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@i915_module_load@load.html
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#6227])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][103] -> [ABORT][104] ([i915#9820])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-2/igt@i915_module_load@reload-with-fault-injection.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg1:          NOTRUN -> [INCOMPLETE][105] ([i915#1982] / [i915#9820] / [i915#9849])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#8399])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-3/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#6590])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][108] -> [INCOMPLETE][109] ([i915#7790])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-snb2/igt@i915_pm_rps@reset.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-snb5/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][110] ([i915#8925])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-15/igt@i915_pm_rps@thresholds-park@gt0.html
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#8925])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_power@sanity:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([i915#7984])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@i915_power@sanity.html

  * igt@i915_query@engine-info-invalid:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][113] ([i915#4423])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@i915_query@engine-info-invalid.html

  * igt@i915_selftest@mock@memory_region:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][114] ([i915#9311])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-15/igt@i915_selftest@mock@memory_region.html
    - shard-glk:          NOTRUN -> [DMESG-WARN][115] ([i915#9311])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk1/igt@i915_selftest@mock@memory_region.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#4212])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][117] ([i915#4212])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@clobberred-modifier:
    - shard-dg1:          NOTRUN -> [SKIP][118] ([i915#4212])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_addfb_basic@clobberred-modifier.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][119] ([i915#8709]) +7 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#8709]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][121] ([i915#6228])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#9531])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#1769] / [i915#3555])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][124] ([i915#5286]) +5 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#5286]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][126] ([i915#4538] / [i915#5286]) +7 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-mtlp:         [PASS][127] -> [FAIL][128] ([i915#5138])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#3638]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#4538] / [i915#5190]) +13 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][131] ([i915#3638]) +4 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][132] ([i915#4538]) +4 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#6187])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-mtlp:         NOTRUN -> [SKIP][134] +10 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_joiner@basic:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#10656])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][136] ([i915#6095]) +23 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][137] ([i915#10307] / [i915#6095]) +173 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][138] ([i915#6095]) +31 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][140] ([i915#6095]) +87 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#6095]) +75 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#3742])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-tglu:         NOTRUN -> [SKIP][143] ([i915#7828]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-snb:          NOTRUN -> [SKIP][144] +66 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-snb5/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][145] ([i915#7828]) +7 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#7828]) +12 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#7828]) +9 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-15/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#7828]) +8 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_color@deep-color:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#3555] / [i915#9979])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#7118] / [i915#9424])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@content-type-change:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#9424])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg1:          NOTRUN -> [SKIP][152] ([i915#3299])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][153] ([i915#7173])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#9424])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_content_protection@mei-interface.html
    - shard-tglu:         NOTRUN -> [SKIP][155] ([i915#6944] / [i915#9424])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-5/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-dg1:          NOTRUN -> [SKIP][156] ([i915#7116] / [i915#9424]) +2 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][157] ([i915#3555] / [i915#8814]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#3359])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#3359])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-dg1:          NOTRUN -> [SKIP][160] ([i915#3555]) +4 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#3359])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][162] ([i915#8814]) +2 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-1/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][163] ([i915#3359]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][164] ([i915#9809]) +5 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg1:          NOTRUN -> [SKIP][165] ([i915#4103] / [i915#4213])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][166] +36 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#5354]) +36 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-5/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][168] -> [FAIL][169] ([i915#2346])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#9067])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#4103] / [i915#4213])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#4103])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@single-move@pipe-a:
    - shard-mtlp:         [PASS][173] -> [DMESG-WARN][174] ([i915#10166])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-mtlp-1/igt@kms_cursor_legacy@single-move@pipe-a.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_cursor_legacy@single-move@pipe-a.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][175] ([i915#9723])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#9227])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#8588])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#3555]) +4 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#8812])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][180] ([i915#8812])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-tglu:         NOTRUN -> [SKIP][181] ([i915#3840])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][182] ([i915#3555] / [i915#3840]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#3555] / [i915#3840]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#3555] / [i915#3840]) +2 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#3840] / [i915#9053])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#3840] / [i915#9053])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#4854])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@kms_feature_discovery@chamelium.html
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#4854])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_feature_discovery@chamelium.html
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#4854])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-15/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#9934]) +8 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][191] ([i915#3637]) +4 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg1:          NOTRUN -> [SKIP][192] ([i915#8381])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglu:         NOTRUN -> [SKIP][193] ([i915#3637]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1:
    - shard-rkl:          [PASS][194] -> [FAIL][195] ([i915#2122]) +1 other test fail
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a4:
    - shard-dg1:          [PASS][196] -> [FAIL][197] ([i915#2122])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-18/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a4.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a4.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][198] ([i915#8381])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][199] ([i915#8381])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#2672]) +1 other test skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][201] ([i915#2672]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][202] ([i915#3555] / [i915#8810]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][203] ([i915#2587] / [i915#2672]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][204] ([i915#8810])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][205] ([i915#2587] / [i915#2672]) +1 other test skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][206] ([i915#2672] / [i915#3555])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#2672]) +4 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [FAIL][208] ([i915#6880])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#8708]) +17 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][210] ([i915#8708]) +3 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-snb:          [PASS][211] -> [SKIP][212] +2 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][213] ([i915#1825]) +26 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][214] ([i915#8708]) +21 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#10055])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][216] +37 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][217] +52 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][218] ([i915#3023]) +23 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-dg1:          NOTRUN -> [SKIP][219] ([i915#5439])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-mtlp:         NOTRUN -> [DMESG-WARN][220] ([i915#1982])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-1p-rte:
    - shard-dg2:          NOTRUN -> [SKIP][221] ([i915#3458]) +14 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][222] ([i915#1825]) +40 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][223] ([i915#3458]) +17 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#3555] / [i915#8228]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-10/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#3555] / [i915#8228]) +1 other test skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][226] ([i915#4816])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#6301])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][228] ([i915#7862]) +1 other test fail
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk5/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][229] ([i915#10647]) +1 other test fail
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk8/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#3555]) +2 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-5/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#3555] / [i915#8821])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#3555]) +2 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-5/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-mtlp:         NOTRUN -> [SKIP][233] ([i915#3555] / [i915#8806])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][234] ([i915#9423]) +7 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][235] ([i915#9423]) +7 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#9423]) +7 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][237] ([i915#5176]) +3 other tests skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-edp-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][238] ([i915#5176] / [i915#9423]) +3 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][239] ([i915#5176] / [i915#9423]) +1 other test skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][240] ([i915#5235]) +7 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][241] ([i915#5235]) +5 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][242] ([i915#5235] / [i915#9423]) +15 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][243] ([i915#5235]) +2 other tests skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][244] ([i915#3555] / [i915#5235])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1.html

  * igt@kms_pm_backlight@fade:
    - shard-rkl:          NOTRUN -> [SKIP][245] ([i915#5354])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_pm_backlight@fade.html
    - shard-dg1:          NOTRUN -> [SKIP][246] ([i915#5354])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [PASS][247] -> [SKIP][248] ([i915#4281])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-2/igt@kms_pm_dc@dc9-dpms.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][249] ([i915#9301])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-10/igt@kms_pm_lpsp@kms-lpsp@pipe-a-hdmi-a-1.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-mtlp:         NOTRUN -> [SKIP][250] ([i915#8430])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#9519])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [PASS][252] -> [SKIP][253] ([i915#9519]) +1 other test skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu:         NOTRUN -> [SKIP][254] ([i915#9519])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-mtlp:         NOTRUN -> [SKIP][255] ([i915#6524])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-1/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2:          NOTRUN -> [SKIP][256] ([i915#6524] / [i915#6805])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][257] +17 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf@psr2-pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][258] ([i915#9808]) +3 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf@psr2-pipe-a-edp-1.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][259] ([i915#4348])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2:          NOTRUN -> [SKIP][260] ([i915#9683])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@kms_psr2_su@page_flip-nv12.html
    - shard-rkl:          NOTRUN -> [SKIP][261] ([i915#9683])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_psr2_su@page_flip-nv12.html
    - shard-dg1:          NOTRUN -> [SKIP][262] ([i915#9683])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-dg1:          NOTRUN -> [SKIP][263] ([i915#1072] / [i915#9732]) +18 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-13/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html

  * igt@kms_psr@fbc-psr-primary-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +15 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@kms_psr@fbc-psr-primary-mmap-cpu.html

  * igt@kms_psr@fbc-psr2-primary-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][266] ([i915#9732]) +10 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@kms_psr@fbc-psr2-primary-mmap-gtt.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][267] ([i915#1072] / [i915#9732]) +22 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-primary-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][268] ([i915#9688]) +7 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_psr@pr-primary-mmap-cpu.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][269] ([i915#4077] / [i915#9688])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@kms_psr@psr-primary-mmap-gtt@edp-1.html

  * igt@kms_psr@psr2-cursor-plane-onoff@edp-1:
    - shard-mtlp:         [PASS][270] -> [FAIL][271] ([i915#10105])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-mtlp-4/igt@kms_psr@psr2-cursor-plane-onoff@edp-1.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@kms_psr@psr2-cursor-plane-onoff@edp-1.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-glk:          NOTRUN -> [SKIP][272] +284 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk5/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu:         NOTRUN -> [SKIP][273] ([i915#9685])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
    - shard-dg2:          NOTRUN -> [SKIP][274] ([i915#9685])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][275] ([i915#4235]) +2 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][276] ([i915#5289])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][277] ([i915#4235] / [i915#5190])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][278] ([i915#5190])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-mtlp:         NOTRUN -> [SKIP][279] ([i915#4235]) +1 other test skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-mtlp:         NOTRUN -> [SKIP][280] ([i915#3555] / [i915#8809])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-mtlp:         NOTRUN -> [SKIP][281] ([i915#8623])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@kms_tiled_display@basic-test-pattern.html
    - shard-rkl:          NOTRUN -> [SKIP][282] ([i915#8623])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][283] -> [FAIL][284] ([i915#9196])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-dg2:          NOTRUN -> [SKIP][285] ([i915#9906])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-mtlp:         NOTRUN -> [SKIP][286] ([i915#2437] / [i915#9412])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-2/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#2437])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-glk:          NOTRUN -> [SKIP][288] ([i915#2437]) +1 other test skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk3/igt@kms_writeback@writeback-pixel-formats.html
    - shard-dg1:          NOTRUN -> [SKIP][289] ([i915#2437] / [i915#9412])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@global-sseu-config-invalid:
    - shard-dg2:          NOTRUN -> [SKIP][290] ([i915#7387])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@perf@global-sseu-config-invalid.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-dg2:          NOTRUN -> [SKIP][291] ([i915#8516])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-7/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg2:          NOTRUN -> [SKIP][292] ([i915#3708])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          NOTRUN -> [SKIP][293] ([i915#3291] / [i915#3708])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][294] ([i915#3708] / [i915#4077])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@prime_vgem@coherency-gtt.html
    - shard-dg1:          NOTRUN -> [SKIP][295] ([i915#3708] / [i915#4077])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@prime_vgem@coherency-gtt.html
    - shard-mtlp:         NOTRUN -> [SKIP][296] ([i915#3708] / [i915#4077])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-7/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-rkl:          NOTRUN -> [SKIP][297] ([i915#3708])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg1:          NOTRUN -> [SKIP][298] ([i915#3708])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-tglu:         NOTRUN -> [SKIP][299] ([i915#9917])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-7/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - shard-dg2:          NOTRUN -> [SKIP][300] ([i915#9917])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-mtlp:         NOTRUN -> [FAIL][301] ([i915#9779])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-8/igt@syncobj_wait@invalid-wait-zero-handles.html
    - shard-dg2:          NOTRUN -> [FAIL][302] ([i915#9779])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@syncobj_wait@invalid-wait-zero-handles.html
    - shard-rkl:          NOTRUN -> [FAIL][303] ([i915#9779])
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@syncobj_wait@invalid-wait-zero-handles.html
    - shard-dg1:          NOTRUN -> [FAIL][304] ([i915#9779])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-17/igt@syncobj_wait@invalid-wait-zero-handles.html

  * igt@v3d/v3d_perfmon@create-two-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][305] ([i915#2575]) +12 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@v3d/v3d_perfmon@create-two-perfmon.html

  * igt@v3d/v3d_submit_cl@bad-multisync-pad:
    - shard-mtlp:         NOTRUN -> [SKIP][306] ([i915#2575]) +7 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@v3d/v3d_submit_cl@bad-multisync-pad.html

  * igt@v3d/v3d_submit_cl@single-in-sync:
    - shard-dg1:          NOTRUN -> [SKIP][307] ([i915#2575]) +13 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-14/igt@v3d/v3d_submit_cl@single-in-sync.html

  * igt@v3d/v3d_submit_cl@valid-submission:
    - shard-tglu:         NOTRUN -> [SKIP][308] ([i915#2575]) +7 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-8/igt@v3d/v3d_submit_cl@valid-submission.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-rkl:          NOTRUN -> [SKIP][309] ([i915#7711]) +6 other tests skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_perfmon@create-perfmon-exceed:
    - shard-mtlp:         NOTRUN -> [SKIP][310] ([i915#7711]) +6 other tests skip
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-6/igt@vc4/vc4_perfmon@create-perfmon-exceed.html

  * igt@vc4/vc4_tiling@get-bad-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][311] ([i915#7711]) +7 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@vc4/vc4_tiling@get-bad-modifier.html

  * igt@vc4/vc4_wait_bo@unused-bo-0ns:
    - shard-dg1:          NOTRUN -> [SKIP][312] ([i915#7711]) +8 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@vc4/vc4_wait_bo@unused-bo-0ns.html

  
#### Possible fixes ####

  * igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_clear:
    - shard-dg2:          [ABORT][313] -> [PASS][314]
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_clear.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_clear.html

  * igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_range_bias:
    - shard-dg2:          [DMESG-FAIL][315] -> [PASS][316]
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_range_bias.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-8/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_range_bias.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-rkl:          [FAIL][317] ([i915#6268]) -> [PASS][318]
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          [FAIL][319] ([i915#5784]) -> [PASS][320] +1 other test pass
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-16/igt@gem_eio@unwedge-stress.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-16/igt@gem_eio@unwedge-stress.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
    - shard-dg2:          [FAIL][321] ([i915#10378]) -> [PASS][322]
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-mtlp:         [ABORT][323] ([i915#10131] / [i915#9697]) -> [PASS][324]
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live@hangcheck:
    - shard-dg2:          [INCOMPLETE][325] -> [PASS][326]
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-8/igt@i915_selftest@live@hangcheck.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-2/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [INCOMPLETE][327] ([i915#4817]) -> [PASS][328]
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][329] ([i915#2346]) -> [PASS][330]
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
    - shard-snb:          [FAIL][331] ([i915#2122]) -> [PASS][332]
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-dg2:          [FAIL][333] ([i915#6880]) -> [PASS][334]
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][335] ([i915#9295]) -> [PASS][336]
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][337] ([i915#9519]) -> [PASS][338]
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [SKIP][339] ([i915#9519]) -> [PASS][340] +1 other test pass
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [FAIL][341] ([i915#9196]) -> [PASS][342]
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * igt@perf_pmu@busy-double-start@ccs0:
    - shard-mtlp:         [FAIL][343] ([i915#4349]) -> [PASS][344]
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-mtlp-5/igt@perf_pmu@busy-double-start@ccs0.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-mtlp-5/igt@perf_pmu@busy-double-start@ccs0.html

  
#### Warnings ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-tglu:         [INCOMPLETE][345] ([i915#10047]) -> [INCOMPLETE][346] ([i915#10047] / [i915#9820])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg2:          [ABORT][347] ([i915#9820]) -> [INCOMPLETE][348] ([i915#1982] / [i915#9820] / [i915#9849])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_color@deep-color:
    - shard-dg1:          [SKIP][349] ([i915#3555]) -> [SKIP][350] ([i915#3555] / [i915#4423])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-13/igt@kms_color@deep-color.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_color@deep-color.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][351] ([i915#3458]) -> [SKIP][352] ([i915#10433] / [i915#3458]) +4 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          [SKIP][353] ([i915#10433] / [i915#3458]) -> [SKIP][354] ([i915#3458]) +3 other tests skip
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg1:          [SKIP][355] -> [SKIP][356] ([i915#4423])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][357] ([i915#9295]) -> [SKIP][358] ([i915#3361])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_prime@basic-crc-vgem:
    - shard-dg1:          [SKIP][359] ([i915#6524]) -> [SKIP][360] ([i915#4423] / [i915#6524])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg1-18/igt@kms_prime@basic-crc-vgem.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg1-18/igt@kms_prime@basic-crc-vgem.html

  * igt@kms_psr@fbc-pr-primary-page-flip:
    - shard-dg2:          [SKIP][361] ([i915#1072] / [i915#9732]) -> [SKIP][362] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-7/igt@kms_psr@fbc-pr-primary-page-flip.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-11/igt@kms_psr@fbc-pr-primary-page-flip.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-dg2:          [SKIP][363] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][364] ([i915#1072] / [i915#9732]) +9 other tests skip
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14780/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/shard-dg2-3/igt@kms_psr@fbc-psr-cursor-plane-move.html

  
  [i915#10030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10030
  [i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10105]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10105
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10380]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10380
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
  [i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
  [i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
  [i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
  [i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9301
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9697
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
  [i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7860 -> IGTPW_11155
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_14780: 8ef53c10d150679e3ff5db00d128417dfffb7798 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11155: 11155
  IGT_7860: 05b3f5540c6dcaacdf2169dc730c126df9ffd7e2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11155/index.html

[-- Attachment #2: Type: text/html, Size: 122020 bytes --]

Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Matthew Brost]

On Fri, May 17, 2024 at 05:16:48PM +0530, Bommu Krishnaiah wrote:
> Introduce helper functions for object creation, binding, submission,
> and destruction, applicable for SVM and other tests
> 
> xe-basic test is validating the helper function introduced in 'lib/xe/xe_util: helper function'
> 
> svm test cases:
> svm-basic-malloc
> svm-basic-mmap
> svm-random-access
> svm-huge-page
> svm-atomic-access
> svm-atomic-access
> svm_invalid_va
> svm-mprotect
> svm-benchmark
> svm-sparse-access
> 

There's a lot here I dislike. Let me be direct.

Firstly, this isn't an SVM test; it explicitly binds userptrs and BOs. So using
SVM prefixes in the test names doesn't make sense. And having RBs with those
names makes even less sense. With that; This email is directed at EVERYONE
replying to this series.

At a high level, I've expressed my views on generic helpers hindering the
ability to create truly powerful tests that provide the necessary coverage for a
complex driver. See my thoughts here [1] [2]. I don't see anything here that
comes close to addressing my concerns. These tests are so simple they won't find
any bugs in the KMD beyond the implementation being completely broken.

This is what I think an SVM test should look like [3] (for the record, I have
shared an eariler baseline of this code too). While it has some complex coding
patterns, once understood by a developer, it's quite easy to extend for a new
test case. Let me give an example...

Take a look at this diff [4]. It's a few lines of code that add HUGE_TLB
testing. This simple change spawns over 100 tests of various varieties (e.g., a
single exec with HUGE_TLB, two execs, many execs, multi-threaded versions,
multi-process versions, etc...).

Before change:
./build/tests/xe_exec_system_allocator --l | wc
    938     938   32872

After change:
./build/tests/xe_exec_system_allocator --l | wc
   1070    1070   37852

Being extendable like this ultimately reduces maintenance costs over time.

The test I've shared creates true coverage and is just a starting point. It will
need to become more complex over time as the SVM uAPI grows.

I suggest investing the time to learn how the code I've shared works and develop
within that framework. If the same level of coverage/extendability can be
achieved with helpers, great. Anything less, in either area, I don't think is
acceptable.

Matt

I can't find PW links for [1][2] so instead have shared the email thread subject
lines. Everyone on this email was on those chains as well.

[1] [PATCH RFC i-g-t 0/2] helper function
[2] [PATCH] lib/xe/xe_util: Creating the helper functions
[3] https://patchwork.freedesktop.org/patch/594807/?series=133846&rev=1
[4] https://pastebin.com/jUN5BwUy
 
> svm kernel implimentation:
> https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
> branch: origin/drm-xe-next-svm-unify-userptr
> 
> v2 igt patch: https://patchwork.freedesktop.org/series/133096/
> 
> Note: xe-basic test is validated without SVM. Remaining tests are not validated because the SVM driver code is still under development
> 
> Bommu Krishnaiah (10):
>   lib/xe/xe_util: Introduce helper functions for buffer creation and
>     command submission etc
>   tests/intel/xe_svm: basic xe-basic test
>   tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
>   tests/intel/xe_svm: add random access test for SVM
>   tests/intel/xe_svm: add huge page access test for SVM
>   tests/intel/xe_svm: Add support for GPU atomic access test for svm
>   tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
>     functionality with invalid address access
>   tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance
>     with a simple benchmark
>   tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality
>     with read-only memory access
>   tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
>     accessing two memory locations with SVM
> 
>  include/drm-uapi/xe_drm.h |   1 +
>  lib/xe/xe_util.c          | 214 +++++++++++++++++
>  lib/xe/xe_util.h          |  40 ++++
>  tests/intel/xe_svm.c      | 476 ++++++++++++++++++++++++++++++++++++++
>  tests/meson.build         |   1 +
>  5 files changed, 732 insertions(+)
>  create mode 100644 tests/intel/xe_svm.c
> 
> -- 
> 2.25.1
> 

Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Matthew Brost]

On Wed, May 22, 2024 at 11:38:18AM +0000, Matthew Brost wrote:
> On Fri, May 17, 2024 at 05:16:48PM +0530, Bommu Krishnaiah wrote:
> > Introduce helper functions for object creation, binding, submission,
> > and destruction, applicable for SVM and other tests
> > 
> > xe-basic test is validating the helper function introduced in 'lib/xe/xe_util: helper function'
> > 
> > svm test cases:
> > svm-basic-malloc
> > svm-basic-mmap
> > svm-random-access
> > svm-huge-page
> > svm-atomic-access
> > svm-atomic-access
> > svm_invalid_va
> > svm-mprotect
> > svm-benchmark
> > svm-sparse-access
> > 
> 
> There's a lot here I dislike. Let me be direct.
> 
> Firstly, this isn't an SVM test; it explicitly binds userptrs and BOs. So using
> SVM prefixes in the test names doesn't make sense. And having RBs with those
> names makes even less sense. With that; This email is directed at EVERYONE
> replying to this series.
> 

Didn't send everyone, CCing interested parties.

> At a high level, I've expressed my views on generic helpers hindering the
> ability to create truly powerful tests that provide the necessary coverage for a
> complex driver. See my thoughts here [1] [2]. I don't see anything here that
> comes close to addressing my concerns. These tests are so simple they won't find
> any bugs in the KMD beyond the implementation being completely broken.
> 
> This is what I think an SVM test should look like [3] (for the record, I have
> shared an eariler baseline of this code too). While it has some complex coding
> patterns, once understood by a developer, it's quite easy to extend for a new
> test case. Let me give an example...
> 
> Take a look at this diff [4]. It's a few lines of code that add HUGE_TLB
> testing. This simple change spawns over 100 tests of various varieties (e.g., a
> single exec with HUGE_TLB, two execs, many execs, multi-threaded versions,
> multi-process versions, etc...).
> 
> Before change:
> ./build/tests/xe_exec_system_allocator --l | wc
>     938     938   32872
> 
> After change:
> ./build/tests/xe_exec_system_allocator --l | wc
>    1070    1070   37852
> 
> Being extendable like this ultimately reduces maintenance costs over time.
> 
> The test I've shared creates true coverage and is just a starting point. It will
> need to become more complex over time as the SVM uAPI grows.
> 
> I suggest investing the time to learn how the code I've shared works and develop
> within that framework. If the same level of coverage/extendability can be
> achieved with helpers, great. Anything less, in either area, I don't think is
> acceptable.
> 
> Matt
> 
> I can't find PW links for [1][2] so instead have shared the email thread subject
> lines. Everyone on this email was on those chains as well.
> 
> [1] [PATCH RFC i-g-t 0/2] helper function
> [2] [PATCH] lib/xe/xe_util: Creating the helper functions
> [3] https://patchwork.freedesktop.org/patch/594807/?series=133846&rev=1
> [4] https://pastebin.com/jUN5BwUy
>  
> > svm kernel implimentation:
> > https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
> > branch: origin/drm-xe-next-svm-unify-userptr
> > 
> > v2 igt patch: https://patchwork.freedesktop.org/series/133096/
> > 
> > Note: xe-basic test is validated without SVM. Remaining tests are not validated because the SVM driver code is still under development
> > 
> > Bommu Krishnaiah (10):
> >   lib/xe/xe_util: Introduce helper functions for buffer creation and
> >     command submission etc
> >   tests/intel/xe_svm: basic xe-basic test
> >   tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
> >   tests/intel/xe_svm: add random access test for SVM
> >   tests/intel/xe_svm: add huge page access test for SVM
> >   tests/intel/xe_svm: Add support for GPU atomic access test for svm
> >   tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
> >     functionality with invalid address access
> >   tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance
> >     with a simple benchmark
> >   tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality
> >     with read-only memory access
> >   tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
> >     accessing two memory locations with SVM
> > 
> >  include/drm-uapi/xe_drm.h |   1 +
> >  lib/xe/xe_util.c          | 214 +++++++++++++++++
> >  lib/xe/xe_util.h          |  40 ++++
> >  tests/intel/xe_svm.c      | 476 ++++++++++++++++++++++++++++++++++++++
> >  tests/meson.build         |   1 +
> >  5 files changed, 732 insertions(+)
> >  create mode 100644 tests/intel/xe_svm.c
> > 
> > -- 
> > 2.25.1
> > 

RE: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Zeng, Oak]

Hi Matt,

We will investigate your tests and see whether we can achieve the same coverage with our approach.

See also comments inline.

> -----Original Message-----
> From: Brost, Matthew <matthew.brost@intel.com>
> Sent: Wednesday, May 22, 2024 7:42 AM
> To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: igt-dev@lists.freedesktop.org; Brost, Matthew
> <matthew.brost@intel.com>; intel-xe@lists.freedesktop.org; Zeng, Oak
> <oak.zeng@intel.com>
> Subject: Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared
> Virtual Memory (SVM)
> 
> On Wed, May 22, 2024 at 11:38:18AM +0000, Matthew Brost wrote:
> > On Fri, May 17, 2024 at 05:16:48PM +0530, Bommu Krishnaiah wrote:
> > > Introduce helper functions for object creation, binding, submission,
> > > and destruction, applicable for SVM and other tests
> > >
> > > xe-basic test is validating the helper function introduced in 'lib/xe/xe_util:
> helper function'
> > >
> > > svm test cases:
> > > svm-basic-malloc
> > > svm-basic-mmap
> > > svm-random-access
> > > svm-huge-page
> > > svm-atomic-access
> > > svm-atomic-access
> > > svm_invalid_va
> > > svm-mprotect
> > > svm-benchmark
> > > svm-sparse-access
> > >
> >
> > There's a lot here I dislike. Let me be direct.
> >
> > Firstly, this isn't an SVM test; it explicitly binds userptrs and BOs. So using
> > SVM prefixes in the test names doesn't make sense. 

It is SVM test. Those test use BO for command (batch) buffer. But the buffer GPU read/write is malloc'ed or mmap'ed. So it does test SVM/system allocator functionality.

Malloc'ed and mmap'ed memory can also be used for command buffer. We can add a test case. 


And having RBs with
> those
> > names makes even less sense. With that; This email is directed at
> EVERYONE
> > replying to this series.
> >
> 
> Didn't send everyone, CCing interested parties.
> 
> > At a high level, I've expressed my views on generic helpers hindering the
> > ability to create truly powerful tests that provide the necessary coverage
> for a
> > complex driver. See my thoughts here [1] [2]. I don't see anything here
> that
> > comes close to addressing my concerns. 

I replied again to [1] with more details. Please take a look.


These tests are so simple they
> won't find
> > any bugs in the KMD beyond the implementation being completely broken.
> >

Agree those tests in this series are simple. But this is just a start. We plan to do more complex tests which are documented in https://jira.devtools.intel.com/browse/VLK-59767

We will also look at your series to see whether we can have the same coverage.


> > This is what I think an SVM test should look like [3] (for the record, I have
> > shared an eariler baseline of this code too). While it has some complex
> coding
> > patterns, once understood by a developer, it's quite easy to extend for a
> new
> > test case. Let me give an example...
> >
> > Take a look at this diff [4]. It's a few lines of code that add HUGE_TLB
> > testing. This simple change spawns over 100 tests of various varieties (e.g.,
> a
> > single exec with HUGE_TLB, two execs, many execs, multi-threaded
> versions,
> > multi-process versions, etc...).
> >
> > Before change:
> > ./build/tests/xe_exec_system_allocator --l | wc
> >     938     938   32872
> >
> > After change:
> > ./build/tests/xe_exec_system_allocator --l | wc
> >    1070    1070   37852
> >
> > Being extendable like this ultimately reduces maintenance costs over time.
> >
> > The test I've shared creates true coverage and is just a starting point. It will
> > need to become more complex over time as the SVM uAPI grows.
> >
> > I suggest investing the time to learn how the code I've shared works and
> develop
> > within that framework. If the same level of coverage/extendability can be
> > achieved with helpers, great. Anything less, in either area, I don't think is
> > acceptable.

There are two fundamental design difference b/t your approach and the approach we applied here:

1) Whether to create/use helper functions:

Our helper functions created concept of xe-buffer, xe-command-buffer. I still think with helper functions, we can simply test writing.

2) use one big test to test many functionalities vs many small tests, each test one functionality

It is obvious, our approach is much easier to maintain and understand.

So the key is, whether we can achieve the same coverage as your series. As said, we will take a closer look of your series and give it a try.

Oak

> >
> > Matt
> >
> > I can't find PW links for [1][2] so instead have shared the email thread
> subject
> > lines. Everyone on this email was on those chains as well.
> >
> > [1] [PATCH RFC i-g-t 0/2] helper function
> > [2] [PATCH] lib/xe/xe_util: Creating the helper functions
> > [3]
> https://patchwork.freedesktop.org/patch/594807/?series=133846&rev=1
> > [4] https://pastebin.com/jUN5BwUy
> >
> > > svm kernel implimentation:
> > > https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
> > > branch: origin/drm-xe-next-svm-unify-userptr
> > >
> > > v2 igt patch: https://patchwork.freedesktop.org/series/133096/
> > >
> > > Note: xe-basic test is validated without SVM. Remaining tests are not
> validated because the SVM driver code is still under development
> > >
> > > Bommu Krishnaiah (10):
> > >   lib/xe/xe_util: Introduce helper functions for buffer creation and
> > >     command submission etc
> > >   tests/intel/xe_svm: basic xe-basic test
> > >   tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
> > >   tests/intel/xe_svm: add random access test for SVM
> > >   tests/intel/xe_svm: add huge page access test for SVM
> > >   tests/intel/xe_svm: Add support for GPU atomic access test for svm
> > >   tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
> > >     functionality with invalid address access
> > >   tests/intel/xe_svm: Add svm-benchmark test to measure SVM
> performance
> > >     with a simple benchmark
> > >   tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality
> > >     with read-only memory access
> > >   tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
> > >     accessing two memory locations with SVM
> > >
> > >  include/drm-uapi/xe_drm.h |   1 +
> > >  lib/xe/xe_util.c          | 214 +++++++++++++++++
> > >  lib/xe/xe_util.h          |  40 ++++
> > >  tests/intel/xe_svm.c      | 476
> ++++++++++++++++++++++++++++++++++++++
> > >  tests/meson.build         |   1 +
> > >  5 files changed, 732 insertions(+)
> > >  create mode 100644 tests/intel/xe_svm.c
> > >
> > > --
> > > 2.25.1
> > >

Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Matthew Brost]

On Wed, May 22, 2024 at 10:53:05AM -0600, Zeng, Oak wrote:
> Hi Matt,
> 
> We will investigate your tests and see whether we can achieve the same coverage with our approach.
> 
> See also comments inline.
> 
> > -----Original Message-----
> > From: Brost, Matthew <matthew.brost@intel.com>
> > Sent: Wednesday, May 22, 2024 7:42 AM
> > To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: igt-dev@lists.freedesktop.org; Brost, Matthew
> > <matthew.brost@intel.com>; intel-xe@lists.freedesktop.org; Zeng, Oak
> > <oak.zeng@intel.com>
> > Subject: Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared
> > Virtual Memory (SVM)
> > 
> > On Wed, May 22, 2024 at 11:38:18AM +0000, Matthew Brost wrote:
> > > On Fri, May 17, 2024 at 05:16:48PM +0530, Bommu Krishnaiah wrote:
> > > > Introduce helper functions for object creation, binding, submission,
> > > > and destruction, applicable for SVM and other tests
> > > >
> > > > xe-basic test is validating the helper function introduced in 'lib/xe/xe_util:
> > helper function'
> > > >
> > > > svm test cases:
> > > > svm-basic-malloc
> > > > svm-basic-mmap
> > > > svm-random-access
> > > > svm-huge-page
> > > > svm-atomic-access
> > > > svm-atomic-access
> > > > svm_invalid_va
> > > > svm-mprotect
> > > > svm-benchmark
> > > > svm-sparse-access
> > > >
> > >
> > > There's a lot here I dislike. Let me be direct.
> > >
> > > Firstly, this isn't an SVM test; it explicitly binds userptrs and BOs. So using
> > > SVM prefixes in the test names doesn't make sense. 
> 
> It is SVM test. Those test use BO for command (batch) buffer. But the buffer GPU read/write is malloc'ed or mmap'ed. So it does test SVM/system allocator functionality.
> 

I did miss that read/write addresses are malloc'd or mmap'd.

However, I don't see a huge bind anywhere in the series. Buffer Objects
(BOs) are only unmapped, not returned to the system allocator bindings,
creating holes in the system allocator space. Additionally, BO addresses
are statically assigned, which does not align with the system allocator
design of calling malloc to reserve address space. This was the source
of my confusion.

> Malloc'ed and mmap'ed memory can also be used for command buffer. We can add a test case. 
> 
> 
> And having RBs with
> > those
> > > names makes even less sense. With that; This email is directed at
> > EVERYONE
> > > replying to this series.
> > >
> > 
> > Didn't send everyone, CCing interested parties.
> > 
> > > At a high level, I've expressed my views on generic helpers hindering the
> > > ability to create truly powerful tests that provide the necessary coverage
> > for a
> > > complex driver. See my thoughts here [1] [2]. I don't see anything here
> > that
> > > comes close to addressing my concerns. 
> 
> I replied again to [1] with more details. Please take a look.
> 
> 
> These tests are so simple they
> > won't find
> > > any bugs in the KMD beyond the implementation being completely broken.
> > >
> 
> Agree those tests in this series are simple. But this is just a start. We plan to do more complex tests which are documented in https://jira.devtools.intel.com/browse/VLK-59767
> 

So we agree that my concerns raised in [1] [2] about only being able to
build simple tests with this design were not addressed.

Having plans is not the same as addressing concerns. If you believe you
can build complex tests achieving good coverage using this design,
great. Please post that. Until then, I remain unconvinced.

I briefly read the Jira; a lot of it is covered by the code shared. What
is not can likely be added in a similar way to the HUGE_TLB example I
shared in the previous email.

One thing I noticed in Jira is that it's written basically as unit tests
(e.g., test feature A, test feature B). Unit tests are okay, but truly
powerful tests do a lot of things all at the same time, in parallel.
This is the advantage of the style of tests I write. Six lines of code
in my example (data path code, that is; tables and documents added more)
spawned over 100 tests doing this in the aforementioned way.

> We will also look at your series to see whether we can have the same coverage.
>
> 
> > > This is what I think an SVM test should look like [3] (for the record, I have
> > > shared an eariler baseline of this code too). While it has some complex
> > coding
> > > patterns, once understood by a developer, it's quite easy to extend for a
> > new
> > > test case. Let me give an example...
> > >
> > > Take a look at this diff [4]. It's a few lines of code that add HUGE_TLB
> > > testing. This simple change spawns over 100 tests of various varieties (e.g.,
> > a
> > > single exec with HUGE_TLB, two execs, many execs, multi-threaded
> > versions,
> > > multi-process versions, etc...).
> > >
> > > Before change:
> > > ./build/tests/xe_exec_system_allocator --l | wc
> > >     938     938   32872
> > >
> > > After change:
> > > ./build/tests/xe_exec_system_allocator --l | wc
> > >    1070    1070   37852
> > >
> > > Being extendable like this ultimately reduces maintenance costs over time.
> > >
> > > The test I've shared creates true coverage and is just a starting point. It will
> > > need to become more complex over time as the SVM uAPI grows.
> > >
> > > I suggest investing the time to learn how the code I've shared works and
> > develop
> > > within that framework. If the same level of coverage/extendability can be
> > > achieved with helpers, great. Anything less, in either area, I don't think is
> > > acceptable.
> 
> There are two fundamental design difference b/t your approach and the approach we applied here:
> 
> 1) Whether to create/use helper functions:
> 
> Our helper functions created concept of xe-buffer, xe-command-buffer. I still think with helper functions, we can simply test writing.
> 
> 2) use one big test to test many functionalities vs many small tests, each test one functionality
> 
> It is obvious, our approach is much easier to maintain and understand.
>

This is an opinion, disrespectful, and rude.

I've provided a concrete example of how the style of tests I've written
in Xe are quite powerful in this email thread. In my opinion, it has
been responded to with speculative arguments and opinions rather than
code.

I have very, very valid reasons for being concerned about testing. This
series [5] was posted in a completely non-functional, untested state. As
reminding and to record this publicly, this was developed off a basline
which was tested with userptr SVM faulting working. I provided the
working baseline and a flavor of the test I have shared.

Going from a tested working KMD with an IGT to untested broken KMD
plus a promise of 'obvious, our approach is much easier to maintain and
understand', well I'll let everyone decide how that looks.

[5] https://patchwork.freedesktop.org/series/132229/

> So the key is, whether we can achieve the same coverage as your series. As said, we will take a closer look of your series and give it a try.
>

I highly suggest you study the code that I shared.

Matt

> Oak
> 
> > >
> > > Matt
> > >
> > > I can't find PW links for [1][2] so instead have shared the email thread
> > subject
> > > lines. Everyone on this email was on those chains as well.
> > >
> > > [1] [PATCH RFC i-g-t 0/2] helper function
> > > [2] [PATCH] lib/xe/xe_util: Creating the helper functions
> > > [3]
> > https://patchwork.freedesktop.org/patch/594807/?series=133846&rev=1
> > > [4] https://pastebin.com/jUN5BwUy
> > >
> > > > svm kernel implimentation:
> > > > https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
> > > > branch: origin/drm-xe-next-svm-unify-userptr
> > > >
> > > > v2 igt patch: https://patchwork.freedesktop.org/series/133096/
> > > >
> > > > Note: xe-basic test is validated without SVM. Remaining tests are not
> > validated because the SVM driver code is still under development
> > > >
> > > > Bommu Krishnaiah (10):
> > > >   lib/xe/xe_util: Introduce helper functions for buffer creation and
> > > >     command submission etc
> > > >   tests/intel/xe_svm: basic xe-basic test
> > > >   tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
> > > >   tests/intel/xe_svm: add random access test for SVM
> > > >   tests/intel/xe_svm: add huge page access test for SVM
> > > >   tests/intel/xe_svm: Add support for GPU atomic access test for svm
> > > >   tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
> > > >     functionality with invalid address access
> > > >   tests/intel/xe_svm: Add svm-benchmark test to measure SVM
> > performance
> > > >     with a simple benchmark
> > > >   tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality
> > > >     with read-only memory access
> > > >   tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
> > > >     accessing two memory locations with SVM
> > > >
> > > >  include/drm-uapi/xe_drm.h |   1 +
> > > >  lib/xe/xe_util.c          | 214 +++++++++++++++++
> > > >  lib/xe/xe_util.h          |  40 ++++
> > > >  tests/intel/xe_svm.c      | 476
> > ++++++++++++++++++++++++++++++++++++++
> > > >  tests/meson.build         |   1 +
> > > >  5 files changed, 732 insertions(+)
> > > >  create mode 100644 tests/intel/xe_svm.c
> > > >
> > > > --
> > > > 2.25.1
> > > >

RE: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM)

[Zeng, Oak]

Hi Matt,

> -----Original Message-----
> From: Brost, Matthew <matthew.brost@intel.com>
> Sent: Thursday, May 23, 2024 1:27 PM
> To: Zeng, Oak <oak.zeng@intel.com>
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; igt-
> dev@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared
> Virtual Memory (SVM)
> 
> On Wed, May 22, 2024 at 10:53:05AM -0600, Zeng, Oak wrote:
> > Hi Matt,
> >
> > We will investigate your tests and see whether we can achieve the same
> coverage with our approach.
> >
> > See also comments inline.
> >
> > > -----Original Message-----
> > > From: Brost, Matthew <matthew.brost@intel.com>
> > > Sent: Wednesday, May 22, 2024 7:42 AM
> > > To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
> > > Cc: igt-dev@lists.freedesktop.org; Brost, Matthew
> > > <matthew.brost@intel.com>; intel-xe@lists.freedesktop.org; Zeng, Oak
> > > <oak.zeng@intel.com>
> > > Subject: Re: [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for
> Shared
> > > Virtual Memory (SVM)
> > >
> > > On Wed, May 22, 2024 at 11:38:18AM +0000, Matthew Brost wrote:
> > > > On Fri, May 17, 2024 at 05:16:48PM +0530, Bommu Krishnaiah wrote:
> > > > > Introduce helper functions for object creation, binding, submission,
> > > > > and destruction, applicable for SVM and other tests
> > > > >
> > > > > xe-basic test is validating the helper function introduced in
> 'lib/xe/xe_util:
> > > helper function'
> > > > >
> > > > > svm test cases:
> > > > > svm-basic-malloc
> > > > > svm-basic-mmap
> > > > > svm-random-access
> > > > > svm-huge-page
> > > > > svm-atomic-access
> > > > > svm-atomic-access
> > > > > svm_invalid_va
> > > > > svm-mprotect
> > > > > svm-benchmark
> > > > > svm-sparse-access
> > > > >
> > > >
> > > > There's a lot here I dislike. Let me be direct.
> > > >
> > > > Firstly, this isn't an SVM test; it explicitly binds userptrs and BOs. So
> using
> > > > SVM prefixes in the test names doesn't make sense.
> >
> > It is SVM test. Those test use BO for command (batch) buffer. But the
> buffer GPU read/write is malloc'ed or mmap'ed. So it does test SVM/system
> allocator functionality.
> >
> 
> I did miss that read/write addresses are malloc'd or mmap'd.
> 
> However, I don't see a huge bind anywhere in the series. 

Yes, I pointed out the same in the code review. We need to fix it.

Buffer Objects
> (BOs) are only unmapped, not returned to the system allocator bindings,
> creating holes in the system allocator space. Additionally, BO addresses
> are statically assigned, which does not align with the system allocator
> design of calling malloc to reserve address space. This was the source
> of my confusion.

Good points. We need to fix the issues.

> 
> > Malloc'ed and mmap'ed memory can also be used for command buffer. We
> can add a test case.
> >
> >
> > And having RBs with
> > > those
> > > > names makes even less sense. With that; This email is directed at
> > > EVERYONE
> > > > replying to this series.
> > > >
> > >
> > > Didn't send everyone, CCing interested parties.
> > >
> > > > At a high level, I've expressed my views on generic helpers hindering
> the
> > > > ability to create truly powerful tests that provide the necessary
> coverage
> > > for a
> > > > complex driver. See my thoughts here [1] [2]. I don't see anything here
> > > that
> > > > comes close to addressing my concerns.
> >
> > I replied again to [1] with more details. Please take a look.
> >
> >
> > These tests are so simple they
> > > won't find
> > > > any bugs in the KMD beyond the implementation being completely
> broken.
> > > >
> >
> > Agree those tests in this series are simple. But this is just a start. We plan to
> do more complex tests which are documented in
> https://jira.devtools.intel.com/browse/VLK-59767
> >
> 
> So we agree that my concerns raised in [1] [2] about only being able to
> build simple tests with this design were not addressed.
> 
> Having plans is not the same as addressing concerns. If you believe you
> can build complex tests achieving good coverage using this design,
> great. Please post that. Until then, I remain unconvinced.
> 
> I briefly read the Jira; a lot of it is covered by the code shared. What
> is not can likely be added in a similar way to the HUGE_TLB example I
> shared in the previous email.
> 
> One thing I noticed in Jira is that it's written basically as unit tests
> (e.g., test feature A, test feature B). Unit tests are okay, but truly
> powerful tests do a lot of things all at the same time, in parallel.
> This is the advantage of the style of tests I write. Six lines of code
> in my example (data path code, that is; tables and documents added more)
> spawned over 100 tests doing this in the aforementioned way.

Yes, I had the same thoughts. 

They are basically two categories of tests:

unit tests. We will try to cover as much as possible in the simple unit test.

integrated test or stress test. 

I tend to think we want to have both. Of course we might have some duplications, such as some functions are tested from both categories. Hopefully this is still acceptable. 

> 
> > We will also look at your series to see whether we can have the same
> coverage.
> >
> >
> > > > This is what I think an SVM test should look like [3] (for the record, I
> have
> > > > shared an eariler baseline of this code too). While it has some complex
> > > coding
> > > > patterns, once understood by a developer, it's quite easy to extend for
> a
> > > new
> > > > test case. Let me give an example...
> > > >
> > > > Take a look at this diff [4]. It's a few lines of code that add HUGE_TLB
> > > > testing. This simple change spawns over 100 tests of various varieties
> (e.g.,
> > > a
> > > > single exec with HUGE_TLB, two execs, many execs, multi-threaded
> > > versions,
> > > > multi-process versions, etc...).
> > > >
> > > > Before change:
> > > > ./build/tests/xe_exec_system_allocator --l | wc
> > > >     938     938   32872
> > > >
> > > > After change:
> > > > ./build/tests/xe_exec_system_allocator --l | wc
> > > >    1070    1070   37852
> > > >
> > > > Being extendable like this ultimately reduces maintenance costs over
> time.
> > > >
> > > > The test I've shared creates true coverage and is just a starting point. It
> will
> > > > need to become more complex over time as the SVM uAPI grows.
> > > >
> > > > I suggest investing the time to learn how the code I've shared works
> and
> > > develop
> > > > within that framework. If the same level of coverage/extendability can
> be
> > > > achieved with helpers, great. Anything less, in either area, I don't think
> is
> > > > acceptable.
> >
> > There are two fundamental design difference b/t your approach and the
> approach we applied here:
> >
> > 1) Whether to create/use helper functions:
> >
> > Our helper functions created concept of xe-buffer, xe-command-buffer. I
> still think with helper functions, we can simply test writing.
> >
> > 2) use one big test to test many functionalities vs many small tests, each
> test one functionality
> >
> > It is obvious, our approach is much easier to maintain and understand.
> >
> 
> This is an opinion, disrespectful, and rude.

I sincerely apologize if those words hurt you. It is not intended to.

> 
> I've provided a concrete example of how the style of tests I've written
> in Xe are quite powerful in this email thread. In my opinion, it has
> been responded to with speculative arguments and opinions rather than
> code.
> 
> I have very, very valid reasons for being concerned about testing. This
> series [5] was posted in a completely non-functional, untested state. As
> reminding and to record this publicly, this was developed off a basline
> which was tested with userptr SVM faulting working. I provided the
> working baseline and a flavor of the test I have shared.
> 
> Going from a tested working KMD with an IGT to untested broken KMD
> plus a promise of 'obvious, our approach is much easier to maintain and
> understand', well I'll let everyone decide how that looks.
> 
> [5] https://patchwork.freedesktop.org/series/132229/
> 
> > So the key is, whether we can achieve the same coverage as your series. As
> said, we will take a closer look of your series and give it a try.
> >
> 
> I highly suggest you study the code that I shared.

Yes, will do. Let's see what we can come up.

Oak
> 
> Matt
> 
> > Oak
> >
> > > >
> > > > Matt
> > > >
> > > > I can't find PW links for [1][2] so instead have shared the email thread
> > > subject
> > > > lines. Everyone on this email was on those chains as well.
> > > >
> > > > [1] [PATCH RFC i-g-t 0/2] helper function
> > > > [2] [PATCH] lib/xe/xe_util: Creating the helper functions
> > > > [3]
> > >
> https://patchwork.freedesktop.org/patch/594807/?series=133846&rev=1
> > > > [4] https://pastebin.com/jUN5BwUy
> > > >
> > > > > svm kernel implimentation:
> > > > > https://gitlab.freedesktop.org/oak/xe-kernel-driver-svm.git
> > > > > branch: origin/drm-xe-next-svm-unify-userptr
> > > > >
> > > > > v2 igt patch: https://patchwork.freedesktop.org/series/133096/
> > > > >
> > > > > Note: xe-basic test is validated without SVM. Remaining tests are not
> > > validated because the SVM driver code is still under development
> > > > >
> > > > > Bommu Krishnaiah (10):
> > > > >   lib/xe/xe_util: Introduce helper functions for buffer creation and
> > > > >     command submission etc
> > > > >   tests/intel/xe_svm: basic xe-basic test
> > > > >   tests/intel/xe_svm: Add SVM basic tests using malloc and mmap
> > > > >   tests/intel/xe_svm: add random access test for SVM
> > > > >   tests/intel/xe_svm: add huge page access test for SVM
> > > > >   tests/intel/xe_svm: Add support for GPU atomic access test for svm
> > > > >   tests/intel/xe_svm: Add svm-invalid-va test to verify SVM
> > > > >     functionality with invalid address access
> > > > >   tests/intel/xe_svm: Add svm-benchmark test to measure SVM
> > > performance
> > > > >     with a simple benchmark
> > > > >   tests/intel/xe_svm: Add svm-mprotect test to verify SVM
> functionality
> > > > >     with read-only memory access
> > > > >   tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely
> > > > >     accessing two memory locations with SVM
> > > > >
> > > > >  include/drm-uapi/xe_drm.h |   1 +
> > > > >  lib/xe/xe_util.c          | 214 +++++++++++++++++
> > > > >  lib/xe/xe_util.h          |  40 ++++
> > > > >  tests/intel/xe_svm.c      | 476
> > > ++++++++++++++++++++++++++++++++++++++
> > > > >  tests/meson.build         |   1 +
> > > > >  5 files changed, 732 insertions(+)
> > > > >  create mode 100644 tests/intel/xe_svm.c
> > > > >
> > > > > --
> > > > > 2.25.1
> > > > >