* [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format
@ 2026-04-15 21:52 Ashutosh Dixit
2026-04-16 4:31 ` Shekhar Chauhan
0 siblings, 1 reply; 8+ messages in thread
From: Ashutosh Dixit @ 2026-04-15 21:52 UTC (permalink / raw)
To: igt-dev; +Cc: Shekhar Chauhan
Support for CRI 192B_MPEC8LL_NOA16 OAM format was previously missed
out. Add it.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
lib/xe/oa-configs/oa-metricset-codegen.py | 13 +++++++++++-
lib/xe/xe_oa.c | 24 +++++++++++++++++++++++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/lib/xe/oa-configs/oa-metricset-codegen.py b/lib/xe/oa-configs/oa-metricset-codegen.py
index c5c7a2c8d4..b44d4d73af 100644
--- a/lib/xe/oa-configs/oa-metricset-codegen.py
+++ b/lib/xe/oa-configs/oa-metricset-codegen.py
@@ -139,7 +139,7 @@ def generate_metric_sets(args, gen):
metric_set->perfcnt_offset = metric_set->c_offset + 8;
"""))
elif gen.chipset == "lnl" or gen.chipset == "bmg" or gen.chipset == "ptl" or gen.chipset == "cri":
- # See intel_xe_perf_accumulate_reports for the offsets
+ # See intel_xe_perf_accumulate_reports for the offsets (value of idx variable)
if set.oa_format == "128B_MPEC8_NOA16" or set.oa_format == "128B_MERT_PEC8":
c(textwrap.dedent("""\
metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u32_B8_C8;
@@ -151,6 +151,17 @@ def generate_metric_sets(args, gen):
metric_set->b_offset = metric_set->pec_offset + 8;
metric_set->c_offset = metric_set->b_offset + 8;
"""))
+ elif set.oa_format == "192B_MPEC8LL_NOA16":
+ c(textwrap.dedent("""\
+ metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u64_B8_C8;
+
+ metric_set->perf_raw_size = 192;
+ metric_set->gpu_time_offset = 0;
+ metric_set->gpu_clock_offset = 1;
+ metric_set->pec_offset = 2;
+ metric_set->b_offset = metric_set->pec_offset + 8;
+ metric_set->c_offset = metric_set->b_offset + 8;
+ """))
else:
c(textwrap.dedent("""\
metric_set->perf_oa_format = XE_OA_FORMAT_PEC64u64;
diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
index b2f447c944..d1a382bdd1 100644
--- a/lib/xe/xe_oa.c
+++ b/lib/xe/xe_oa.c
@@ -875,6 +875,30 @@ void intel_xe_perf_accumulate_reports(struct intel_xe_perf_accumulator *acc,
break;
+ case XE_OAM_FORMAT_MPEC8u64_B8_C8:
+ /* 64 bit timestamp */
+ if (perf->devinfo.oa_timestamp_shift >= 0)
+ deltas[idx++] += (end64[1] - start64[1]) << perf->devinfo.oa_timestamp_shift;
+ else
+ deltas[idx++] += (end64[1] - start64[1]) >> (-perf->devinfo.oa_timestamp_shift);
+
+ /* 64 bit clock */
+ deltas[idx++] += end64[3] - start64[3];
+
+ /* 8x 64bit MPEC counters */
+ for (i = 0; i < 8; i++)
+ deltas[idx++] += end64[4 + i] - start64[4 + i];
+
+ /* 8x 32bit B counters */
+ for (i = 0; i < 8; i++)
+ accumulate_uint32(start + 16 + i, end + 16 + i, deltas + idx++);
+
+ /* 8x 32bit C counters */
+ for (i = 0; i < 8; i++)
+ accumulate_uint32(start + 24 + i, end + 24 + i, deltas + idx++);
+
+ break;
+
case XE_OA_FORMAT_PEC64u64:
/* 64 bit timestamp */
if (perf->devinfo.oa_timestamp_shift >= 0)
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format
2026-04-15 21:52 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
@ 2026-04-16 4:31 ` Shekhar Chauhan
2026-04-16 18:50 ` Dixit, Ashutosh
0 siblings, 1 reply; 8+ messages in thread
From: Shekhar Chauhan @ 2026-04-16 4:31 UTC (permalink / raw)
To: Ashutosh Dixit, igt-dev
On 4/16/2026 3:22, Ashutosh Dixit wrote:
> Support for CRI 192B_MPEC8LL_NOA16 OAM format was previously missed
> out. Add it.
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
> lib/xe/oa-configs/oa-metricset-codegen.py | 13 +++++++++++-
> lib/xe/xe_oa.c | 24 +++++++++++++++++++++++
> 2 files changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/lib/xe/oa-configs/oa-metricset-codegen.py b/lib/xe/oa-configs/oa-metricset-codegen.py
> index c5c7a2c8d4..b44d4d73af 100644
> --- a/lib/xe/oa-configs/oa-metricset-codegen.py
> +++ b/lib/xe/oa-configs/oa-metricset-codegen.py
> @@ -139,7 +139,7 @@ def generate_metric_sets(args, gen):
> metric_set->perfcnt_offset = metric_set->c_offset + 8;
> """))
> elif gen.chipset == "lnl" or gen.chipset == "bmg" or gen.chipset == "ptl" or gen.chipset == "cri":
> - # See intel_xe_perf_accumulate_reports for the offsets
> + # See intel_xe_perf_accumulate_reports for the offsets (value of idx variable)
> if set.oa_format == "128B_MPEC8_NOA16" or set.oa_format == "128B_MERT_PEC8":
> c(textwrap.dedent("""\
> metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u32_B8_C8;
> @@ -151,6 +151,17 @@ def generate_metric_sets(args, gen):
> metric_set->b_offset = metric_set->pec_offset + 8;
> metric_set->c_offset = metric_set->b_offset + 8;
> """))
> + elif set.oa_format == "192B_MPEC8LL_NOA16":
> + c(textwrap.dedent("""\
> + metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u64_B8_C8;
> +
> + metric_set->perf_raw_size = 192;
> + metric_set->gpu_time_offset = 0;
> + metric_set->gpu_clock_offset = 1;
> + metric_set->pec_offset = 2;
> + metric_set->b_offset = metric_set->pec_offset + 8;
> + metric_set->c_offset = metric_set->b_offset + 8;
> + """))
> else:
> c(textwrap.dedent("""\
> metric_set->perf_oa_format = XE_OA_FORMAT_PEC64u64;
> diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
> index b2f447c944..d1a382bdd1 100644
> --- a/lib/xe/xe_oa.c
> +++ b/lib/xe/xe_oa.c
> @@ -875,6 +875,30 @@ void intel_xe_perf_accumulate_reports(struct intel_xe_perf_accumulator *acc,
>
> break;
>
> + case XE_OAM_FORMAT_MPEC8u64_B8_C8:
> + /* 64 bit timestamp */
> + if (perf->devinfo.oa_timestamp_shift >= 0)
> + deltas[idx++] += (end64[1] - start64[1]) << perf->devinfo.oa_timestamp_shift;
> + else
> + deltas[idx++] += (end64[1] - start64[1]) >> (-perf->devinfo.oa_timestamp_shift);
> +
> + /* 64 bit clock */
> + deltas[idx++] += end64[3] - start64[3];
> +
> + /* 8x 64bit MPEC counters */
> + for (i = 0; i < 8; i++)
> + deltas[idx++] += end64[4 + i] - start64[4 + i];
> +
> +
I feel the below increments are wrong. The added format is of 64bit.
> /* 8x 32bit B counters */
> + for (i = 0; i < 8; i++)
> + accumulate_uint32(start + 16 + i, end + 16 + i, deltas + idx++);
This should be "accumulate_uint32(start + 24 + i, end + 24 + i, deltas +
idx++);"
> +
> + /* 8x 32bit C counters */
> + for (i = 0; i < 8; i++)
> + accumulate_uint32(start + 24 + i, end + 24 + i, deltas + idx++);
And this, "accumulate_uint32(start + 32 + i, end + 32 + i, deltas + idx++);"
I'm still new to this, so I can be wrong. Maybe help me understand.
Other than this, patch looks fine to me.
-shekhar
> +
> + break;
> +
> case XE_OA_FORMAT_PEC64u64:
> /* 64 bit timestamp */
> if (perf->devinfo.oa_timestamp_shift >= 0)
--
Shekhar Chauhan
Linux Graphics Software Engineer
Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format
2026-04-16 4:31 ` Shekhar Chauhan
@ 2026-04-16 18:50 ` Dixit, Ashutosh
0 siblings, 0 replies; 8+ messages in thread
From: Dixit, Ashutosh @ 2026-04-16 18:50 UTC (permalink / raw)
To: Shekhar Chauhan; +Cc: igt-dev
On Wed, 15 Apr 2026 21:31:23 -0700, Shekhar Chauhan wrote:
>
> > @@ -875,6 +875,30 @@ void intel_xe_perf_accumulate_reports(struct intel_xe_perf_accumulator *acc,
> > break;
> > + case XE_OAM_FORMAT_MPEC8u64_B8_C8:
> > + /* 64 bit timestamp */
> > + if (perf->devinfo.oa_timestamp_shift >= 0)
> > + deltas[idx++] += (end64[1] - start64[1]) << perf->devinfo.oa_timestamp_shift;
> > + else
> > + deltas[idx++] += (end64[1] - start64[1]) >> (-perf->devinfo.oa_timestamp_shift);
> > +
> > + /* 64 bit clock */
> > + deltas[idx++] += end64[3] - start64[3];
> > +
> > + /* 8x 64bit MPEC counters */
> > + for (i = 0; i < 8; i++)
> > + deltas[idx++] += end64[4 + i] - start64[4 + i];
> > +
> > +
> I feel the below increments are wrong. The added format is of 64bit.
> > /* 8x 32bit B counters */
> > + for (i = 0; i < 8; i++)
> > + accumulate_uint32(start + 16 + i, end + 16 + i, deltas + idx++);
> This should be "accumulate_uint32(start + 24 + i, end + 24 + i, deltas +
> idx++);"
> > +
> > + /* 8x 32bit C counters */
> > + for (i = 0; i < 8; i++)
> > + accumulate_uint32(start + 24 + i, end + 24 + i, deltas + idx++);
>
> And this, "accumulate_uint32(start + 32 + i, end + 32 + i, deltas + idx++);"
>
> I'm still new to this, so I can be wrong. Maybe help me understand. Other
> than this, patch looks fine to me.
Good catch, fixed in v2. Thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format
@ 2026-04-17 3:33 Ashutosh Dixit
2026-04-17 4:16 ` ✓ Xe.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Ashutosh Dixit @ 2026-04-17 3:33 UTC (permalink / raw)
To: igt-dev; +Cc: Shekhar Chauhan
Support for CRI 192B_MPEC8LL_NOA16 OAM format was previously missed
out. Add it.
v2: Fix B/C counter accumulation (Shekhar C)
v3: Fix other places where 192B_MPEC8LL_NOA16 OAM format is used (Shekhar C)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
lib/xe/oa-configs/oa-metricset-codegen.py | 13 +++++++++++-
lib/xe/xe_oa.c | 26 +++++++++++++++++++++++
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/lib/xe/oa-configs/oa-metricset-codegen.py b/lib/xe/oa-configs/oa-metricset-codegen.py
index c5c7a2c8d4..b44d4d73af 100644
--- a/lib/xe/oa-configs/oa-metricset-codegen.py
+++ b/lib/xe/oa-configs/oa-metricset-codegen.py
@@ -139,7 +139,7 @@ def generate_metric_sets(args, gen):
metric_set->perfcnt_offset = metric_set->c_offset + 8;
"""))
elif gen.chipset == "lnl" or gen.chipset == "bmg" or gen.chipset == "ptl" or gen.chipset == "cri":
- # See intel_xe_perf_accumulate_reports for the offsets
+ # See intel_xe_perf_accumulate_reports for the offsets (value of idx variable)
if set.oa_format == "128B_MPEC8_NOA16" or set.oa_format == "128B_MERT_PEC8":
c(textwrap.dedent("""\
metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u32_B8_C8;
@@ -151,6 +151,17 @@ def generate_metric_sets(args, gen):
metric_set->b_offset = metric_set->pec_offset + 8;
metric_set->c_offset = metric_set->b_offset + 8;
"""))
+ elif set.oa_format == "192B_MPEC8LL_NOA16":
+ c(textwrap.dedent("""\
+ metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u64_B8_C8;
+
+ metric_set->perf_raw_size = 192;
+ metric_set->gpu_time_offset = 0;
+ metric_set->gpu_clock_offset = 1;
+ metric_set->pec_offset = 2;
+ metric_set->b_offset = metric_set->pec_offset + 8;
+ metric_set->c_offset = metric_set->b_offset + 8;
+ """))
else:
c(textwrap.dedent("""\
metric_set->perf_oa_format = XE_OA_FORMAT_PEC64u64;
diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
index b2f447c944..891f4868a5 100644
--- a/lib/xe/xe_oa.c
+++ b/lib/xe/xe_oa.c
@@ -875,6 +875,30 @@ void intel_xe_perf_accumulate_reports(struct intel_xe_perf_accumulator *acc,
break;
+ case XE_OAM_FORMAT_MPEC8u64_B8_C8:
+ /* 64 bit timestamp */
+ if (perf->devinfo.oa_timestamp_shift >= 0)
+ deltas[idx++] += (end64[1] - start64[1]) << perf->devinfo.oa_timestamp_shift;
+ else
+ deltas[idx++] += (end64[1] - start64[1]) >> (-perf->devinfo.oa_timestamp_shift);
+
+ /* 64 bit clock */
+ deltas[idx++] += end64[3] - start64[3];
+
+ /* 8x 64bit MPEC counters */
+ for (i = 0; i < 8; i++)
+ deltas[idx++] += end64[4 + i] - start64[4 + i];
+
+ /* 8x 32bit B counters */
+ for (i = 0; i < 8; i++)
+ accumulate_uint32(start + 24 + i, end + 24 + i, deltas + idx++);
+
+ /* 8x 32bit C counters */
+ for (i = 0; i < 8; i++)
+ accumulate_uint32(start + 32 + i, end + 32 + i, deltas + idx++);
+
+ break;
+
case XE_OA_FORMAT_PEC64u64:
/* 64 bit timestamp */
if (perf->devinfo.oa_timestamp_shift >= 0)
@@ -910,6 +934,7 @@ uint64_t intel_xe_perf_read_record_timestamp(const struct intel_xe_perf *perf,
ts = report32[1];
break;
+ case XE_OAM_FORMAT_MPEC8u64_B8_C8:
case XE_OAM_FORMAT_MPEC8u32_B8_C8:
case XE_OA_FORMAT_PEC64u64:
ts = report64[1];
@@ -941,6 +966,7 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per
ts = report32[1];
break;
+ case XE_OAM_FORMAT_MPEC8u64_B8_C8:
case XE_OAM_FORMAT_MPEC8u32_B8_C8:
case XE_OA_FORMAT_PEC64u64:
ts = report64[1];
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Xe.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
2026-04-17 3:33 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
@ 2026-04-17 4:16 ` Patchwork
2026-04-17 4:18 ` ✓ i915.CI.BAT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-04-17 4:16 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1179 bytes --]
== Series Details ==
Series: lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
URL : https://patchwork.freedesktop.org/series/164949/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8863_BAT -> XEIGTPW_15006_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8863 -> IGTPW_15006
* Linux: xe-4917-ff84b38d86b994ebb03d940be1c73a63e231f454 -> xe-4919-3b9ca4c40814c96c38986ae2ba6651e43757ca5f
IGTPW_15006: 9854ea8994244d65a9dcb98222429fcd3521856e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8863: 5b279a8b71dc1672099205a1a9e8135c7c7fadb5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4917-ff84b38d86b994ebb03d940be1c73a63e231f454: ff84b38d86b994ebb03d940be1c73a63e231f454
xe-4919-3b9ca4c40814c96c38986ae2ba6651e43757ca5f: 3b9ca4c40814c96c38986ae2ba6651e43757ca5f
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/index.html
[-- Attachment #2: Type: text/html, Size: 1738 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ i915.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
2026-04-17 3:33 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
2026-04-17 4:16 ` ✓ Xe.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
@ 2026-04-17 4:18 ` Patchwork
2026-04-17 5:35 ` [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Shekhar Chauhan
2026-04-17 6:30 ` ✗ Xe.CI.FULL: failure for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-04-17 4:18 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4937 bytes --]
== Series Details ==
Series: lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
URL : https://patchwork.freedesktop.org/series/164949/
State : success
== Summary ==
CI Bug Log - changes from IGT_8863 -> IGTPW_15006
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/index.html
Participating hosts (42 -> 40)
------------------------------
Missing (2): bat-dg2-13 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_15006 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests:
- fi-skl-6600u: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-skl-6600u/igt@dmabuf@all-tests.html
* igt@i915_selftest@live:
- bat-mtlp-8: [PASS][2] -> [DMESG-FAIL][3] ([i915#12061]) +1 other test dmesg-fail
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/bat-mtlp-8/igt@i915_selftest@live.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/bat-mtlp-8/igt@i915_selftest@live.html
- bat-dg2-8: [PASS][4] -> [DMESG-FAIL][5] ([i915#12061]) +1 other test dmesg-fail
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/bat-dg2-8/igt@i915_selftest@live.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/bat-dg2-8/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-14: [PASS][6] -> [DMESG-FAIL][7] ([i915#12061]) +1 other test dmesg-fail
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/bat-dg2-14/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_selftest@live:
- fi-skl-6600u: [INCOMPLETE][8] ([i915#15859]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/fi-skl-6600u/igt@i915_selftest@live.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-skl-6600u/igt@i915_selftest@live.html
* igt@i915_selftest@live@gtt:
- fi-skl-6600u: [INCOMPLETE][10] -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/fi-skl-6600u/igt@i915_selftest@live@gtt.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-skl-6600u/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@sanitycheck:
- fi-kbl-7567u: [DMESG-WARN][12] ([i915#13735]) -> [PASS][13] +79 other tests pass
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
* igt@i915_selftest@live@workarounds:
- bat-arls-6: [DMESG-FAIL][14] ([i915#12061]) -> [PASS][15] +1 other test pass
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/bat-arls-6/igt@i915_selftest@live@workarounds.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/bat-arls-6/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- fi-kbl-7567u: [DMESG-WARN][16] ([i915#13735] / [i915#180]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/fi-kbl-7567u/igt@kms_busy@basic@flip.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-kbl-7567u/igt@kms_busy@basic@flip.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-kbl-7567u: [DMESG-WARN][18] ([i915#13735] / [i915#15673] / [i915#180]) -> [PASS][19] +52 other tests pass
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8863/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
[i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673
[i915#15859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15859
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8863 -> IGTPW_15006
* Linux: CI_DRM_18347 -> CI_DRM_18348
CI-20190529: 20190529
CI_DRM_18347: 2a1c604bebed8cbbe6aea00f761777eed424dc55 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_18348: 3b9ca4c40814c96c38986ae2ba6651e43757ca5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_15006: 9854ea8994244d65a9dcb98222429fcd3521856e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8863: 5b279a8b71dc1672099205a1a9e8135c7c7fadb5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15006/index.html
[-- Attachment #2: Type: text/html, Size: 6223 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format
2026-04-17 3:33 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
2026-04-17 4:16 ` ✓ Xe.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
2026-04-17 4:18 ` ✓ i915.CI.BAT: " Patchwork
@ 2026-04-17 5:35 ` Shekhar Chauhan
2026-04-17 6:30 ` ✗ Xe.CI.FULL: failure for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Shekhar Chauhan @ 2026-04-17 5:35 UTC (permalink / raw)
To: Ashutosh Dixit, igt-dev
On 4/17/2026 9:03, Ashutosh Dixit wrote:
> Support for CRI 192B_MPEC8LL_NOA16 OAM format was previously missed
> out. Add it.
>
> v2: Fix B/C counter accumulation (Shekhar C)
> v3: Fix other places where 192B_MPEC8LL_NOA16 OAM format is used (Shekhar C)
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
> lib/xe/oa-configs/oa-metricset-codegen.py | 13 +++++++++++-
> lib/xe/xe_oa.c | 26 +++++++++++++++++++++++
> 2 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/lib/xe/oa-configs/oa-metricset-codegen.py b/lib/xe/oa-configs/oa-metricset-codegen.py
> index c5c7a2c8d4..b44d4d73af 100644
> --- a/lib/xe/oa-configs/oa-metricset-codegen.py
> +++ b/lib/xe/oa-configs/oa-metricset-codegen.py
> @@ -139,7 +139,7 @@ def generate_metric_sets(args, gen):
> metric_set->perfcnt_offset = metric_set->c_offset + 8;
> """))
> elif gen.chipset == "lnl" or gen.chipset == "bmg" or gen.chipset == "ptl" or gen.chipset == "cri":
> - # See intel_xe_perf_accumulate_reports for the offsets
> + # See intel_xe_perf_accumulate_reports for the offsets (value of idx variable)
> if set.oa_format == "128B_MPEC8_NOA16" or set.oa_format == "128B_MERT_PEC8":
> c(textwrap.dedent("""\
> metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u32_B8_C8;
> @@ -151,6 +151,17 @@ def generate_metric_sets(args, gen):
> metric_set->b_offset = metric_set->pec_offset + 8;
> metric_set->c_offset = metric_set->b_offset + 8;
> """))
> + elif set.oa_format == "192B_MPEC8LL_NOA16":
> + c(textwrap.dedent("""\
> + metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u64_B8_C8;
> +
> + metric_set->perf_raw_size = 192;
> + metric_set->gpu_time_offset = 0;
> + metric_set->gpu_clock_offset = 1;
> + metric_set->pec_offset = 2;
> + metric_set->b_offset = metric_set->pec_offset + 8;
> + metric_set->c_offset = metric_set->b_offset + 8;
> + """))
> else:
> c(textwrap.dedent("""\
> metric_set->perf_oa_format = XE_OA_FORMAT_PEC64u64;
> diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
> index b2f447c944..891f4868a5 100644
> --- a/lib/xe/xe_oa.c
> +++ b/lib/xe/xe_oa.c
> @@ -875,6 +875,30 @@ void intel_xe_perf_accumulate_reports(struct intel_xe_perf_accumulator *acc,
>
> break;
>
> + case XE_OAM_FORMAT_MPEC8u64_B8_C8:
> + /* 64 bit timestamp */
> + if (perf->devinfo.oa_timestamp_shift >= 0)
> + deltas[idx++] += (end64[1] - start64[1]) << perf->devinfo.oa_timestamp_shift;
> + else
> + deltas[idx++] += (end64[1] - start64[1]) >> (-perf->devinfo.oa_timestamp_shift);
> +
> + /* 64 bit clock */
> + deltas[idx++] += end64[3] - start64[3];
> +
> + /* 8x 64bit MPEC counters */
> + for (i = 0; i < 8; i++)
> + deltas[idx++] += end64[4 + i] - start64[4 + i];
> +
> + /* 8x 32bit B counters */
> + for (i = 0; i < 8; i++)
> + accumulate_uint32(start + 24 + i, end + 24 + i, deltas + idx++);
> +
> + /* 8x 32bit C counters */
> + for (i = 0; i < 8; i++)
> + accumulate_uint32(start + 32 + i, end + 32 + i, deltas + idx++);
> +
> + break;
> +
> case XE_OA_FORMAT_PEC64u64:
> /* 64 bit timestamp */
> if (perf->devinfo.oa_timestamp_shift >= 0)
> @@ -910,6 +934,7 @@ uint64_t intel_xe_perf_read_record_timestamp(const struct intel_xe_perf *perf,
> ts = report32[1];
> break;
>
> + case XE_OAM_FORMAT_MPEC8u64_B8_C8:
> case XE_OAM_FORMAT_MPEC8u32_B8_C8:
> case XE_OA_FORMAT_PEC64u64:
> ts = report64[1];
> @@ -941,6 +966,7 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per
> ts = report32[1];
> break;
>
> + case XE_OAM_FORMAT_MPEC8u64_B8_C8:
> case XE_OAM_FORMAT_MPEC8u32_B8_C8:
> case XE_OA_FORMAT_PEC64u64:
> ts = report64[1];
--
Shekhar Chauhan
Linux Graphics Software Engineer
Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Xe.CI.FULL: failure for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
2026-04-17 3:33 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
` (2 preceding siblings ...)
2026-04-17 5:35 ` [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Shekhar Chauhan
@ 2026-04-17 6:30 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-04-17 6:30 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 14872 bytes --]
== Series Details ==
Series: lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3)
URL : https://patchwork.freedesktop.org/series/164949/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_8863_FULL -> XEIGTPW_15006_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_15006_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_15006_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_15006_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pm_rpm@i2c:
- shard-bmg: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-2/igt@kms_pm_rpm@i2c.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-2/igt@kms_pm_rpm@i2c.html
* igt@xe_pat@pt-caching-update-pat-and-pte:
- shard-bmg: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@xe_pat@pt-caching-update-pat-and-pte.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-5/igt@xe_pat@pt-caching-update-pat-and-pte.html
Known issues
------------
Here are the changes found in XEIGTPW_15006_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2327])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-7/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#6974])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-5/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2311])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_psr@fbc-psr2-primary-blt:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#2234] / [Intel XE#2850])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-9/igt@kms_psr@fbc-psr2-primary-blt.html
* igt@kms_vrr@flip-dpms:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#1499])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-10/igt@kms_vrr@flip-dpms.html
#### Possible fixes ####
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [FAIL][10] ([Intel XE#7445]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@intel_hwmon@hwmon-write.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-5/igt@intel_hwmon@hwmon-write.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
- shard-bmg: [FAIL][12] ([Intel XE#3321]) -> [PASS][13] +1 other test pass
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][14] ([Intel XE#6321]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_system_allocator@many-large-execqueues-new-busy-nomemset:
- shard-bmg: [DMESG-WARN][16] ([Intel XE#7725]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-3/igt@xe_exec_system_allocator@many-large-execqueues-new-busy-nomemset.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-8/igt@xe_exec_system_allocator@many-large-execqueues-new-busy-nomemset.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][18], [PASS][19], [PASS][20], [SKIP][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43]) ([Intel XE#378] / [Intel XE#7405]) -> ([PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-7/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-1/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-4/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-7/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-8/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-6/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-3/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-6/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-8/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-3/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-7/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-8/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-4/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-1/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-2/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-2/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-2/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-7/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-7/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-1/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-4/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-3/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-5/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-5/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-6/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-lnl-5/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-4/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-6/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-1/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-2/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-7/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-8/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-5/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-lnl-3/igt@xe_module_load@load.html
- shard-bmg: ([PASS][52], [PASS][53], [PASS][54], [PASS][55], [SKIP][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-8/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-2/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-3/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-3/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-4/igt@xe_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@xe_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-2/igt@xe_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-5/igt@xe_module_load@load.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-7/igt@xe_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-8/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-5/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-8/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-6/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-6/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-7/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-4/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-1/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-9/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-4/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-9/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-4/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-3/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-2/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-1/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-10/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-2/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-8/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-10/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-1/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-5/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-7/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-3/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-9/igt@xe_module_load@load.html
#### Warnings ####
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][86] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][87] ([Intel XE#2426] / [Intel XE#5848])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8863/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7445]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7445
[Intel XE#7725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7725
Build changes
-------------
* IGT: IGT_8863 -> IGTPW_15006
* Linux: xe-4917-ff84b38d86b994ebb03d940be1c73a63e231f454 -> xe-4919-3b9ca4c40814c96c38986ae2ba6651e43757ca5f
IGTPW_15006: 9854ea8994244d65a9dcb98222429fcd3521856e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8863: 5b279a8b71dc1672099205a1a9e8135c7c7fadb5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4917-ff84b38d86b994ebb03d940be1c73a63e231f454: ff84b38d86b994ebb03d940be1c73a63e231f454
xe-4919-3b9ca4c40814c96c38986ae2ba6651e43757ca5f: 3b9ca4c40814c96c38986ae2ba6651e43757ca5f
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15006/index.html
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2026-04-17 3:33 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
2026-04-17 4:16 ` ✓ Xe.CI.BAT: success for lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format (rev3) Patchwork
2026-04-17 4:18 ` ✓ i915.CI.BAT: " Patchwork
2026-04-17 5:35 ` [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Shekhar Chauhan
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2026-04-15 21:52 [PATCH i-g-t] lib/xe/oa: Add support for 192B_MPEC8LL_NOA16 OAM format Ashutosh Dixit
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