* [PATCH v2 01/18] arm64: dts: ti: k3-{j721e/j721s2}-main: Fix indentation in CSI2RX node
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA Yemike Abhilash Chandra
` (16 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Fix a few minor indentation errors in the cdns csi2rx clocks and
clock-names properties.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++--
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index d5fd30a01032..5a8414fc5751 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -612,9 +612,9 @@ cdns_csi2rx0: csi-bridge@4504000 {
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error_irq", "irq";
clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
- <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
+ <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1228ac5711bf..5cac119e4292 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1251,9 +1251,9 @@ cdns_csi2rx0: csi-bridge@4504000 {
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error_irq", "irq";
clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
- <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
+ <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
@@ -1307,9 +1307,9 @@ cdns_csi2rx1: csi-bridge@4514000 {
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error_irq", "irq";
clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
- <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
+ <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy1>;
phy-names = "dphy";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 01/18] arm64: dts: ti: k3-{j721e/j721s2}-main: Fix indentation in CSI2RX node Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:47 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: " Yemike Abhilash Chandra
` (15 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts. Add
additional DMA channels to enable multistream support for CSI2RX.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 5a8414fc5751..b1988437f52d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -600,8 +600,14 @@ ti_csi2rx0: ticsi2rx@4500000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_udmap 0x4940>;
- dma-names = "rx0";
+ dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
+ <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
+ <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
+ <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
+ <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
+ <&main_udmap 0x494f>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+ "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
@@ -656,8 +662,14 @@ ti_csi2rx1: ticsi2rx@4510000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_udmap 0x4960>;
- dma-names = "rx0";
+ dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
+ <&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
+ <&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
+ <&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
+ <&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
+ <&main_udmap 0x496f>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+ "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 ` [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA Yemike Abhilash Chandra
@ 2026-07-13 11:47 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:47 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: imx, robh, devicetree, conor+dt, Frank.Li
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
Pre-existing issues:
- [High] The driver unregisters contexts before unregistering the async and PM notifiers in remove(), leading to Use-After-Free and data corruption.
- [High] The driver permanently leaks all requested DMA channels during probe failures and device removal because DMA channel release incorrectly relies on the PM runtime status.
- [High] ti_csi2rx_runtime_resume() leaks successfully requested DMA channels when failing to initialize a subsequent context.
- [High] Missing pm_runtime_disable() on probe error paths after pm_runtime_enable() was called.
--
--- Patch [2]: [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA ---
commit 9792c8b4a6bb16010ee3d8cdeef37baa49738183
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts. Add
additional DMA channels to enable multistream support for CSI2RX.
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 5a8414fc57519..b1988437f52dc 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -600,8 +600,14 @@ ti_csi2rx0: ticsi2rx@4500000 {
> ranges;
> #address-cells = <2>;
> #size-cells = <2>;
> - dmas = <&main_udmap 0x4940>;
> - dma-names = "rx0";
> + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
> + <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
> + <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
> + <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
> + <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
> + <&main_udmap 0x494f>;
> + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
> + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
[Severity: High]
This is a pre-existing issue, but does increasing the number of DMA channels
here make a leak in the driver's resume path more likely to occur?
Looking at drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c,
ti_csi2rx_runtime_resume() loops over all contexts:
for (unsigned int i = 0; i < csi->num_ctx; i++) {
ret = ti_csi2rx_init_dma(&csi->ctx[i]);
if (ret)
return ret;
}
If initialization fails for a subsequent context, does it return immediately
without releasing the successfully requested channels from prior iterations?
[Severity: High]
This isn't a bug introduced by this patch, but do the DMA channels get
permanently leaked on probe failures or driver unbind?
In drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:
ti_csi2rx_cleanup_ctx() checks the runtime status:
if (!pm_runtime_status_suspended(ctx->csi->dev))
dma_release_channel(ctx->dma.chan);
During probe, DMA channels are requested before PM runtime is activated.
If probe fails, pm_runtime_status_suspended() returns true, causing the
cleanup to skip releasing the channels.
Similarly, in ti_csi2rx_remove():
if (!pm_runtime_status_suspended(&pdev->dev))
pm_runtime_set_suspended(&pdev->dev);
Since the driver forcefully sets the suspended state without invoking the
runtime suspend callback, will ti_csi2rx_cleanup_ctx() again skip releasing
the channels?
[Severity: High]
This is a pre-existing issue, but is there a use-after-free risk during
driver unbind?
In drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_remove(),
the contexts are cleaned up before the notifiers are unregistered:
for (unsigned int i = 0; i < csi->num_ctx; i++)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
ti_csi2rx_cleanup_notifier(csi);
unregister_pm_notifier(&csi->pm_notifier);
If a system suspend or async notifier completion happens concurrently during
unbind, could it trigger callbacks that access the already destroyed
ctx->mutex or unregistered video_device?
[Severity: High]
This isn't a bug introduced by this patch, but does the probe error path
leave the device with an unbalanced PM runtime enable count?
In drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_probe(),
PM runtime is enabled:
pm_runtime_enable(csi->dev);
ret = ti_csi2rx_notifier_register(csi);
if (ret)
goto err_ctx;
Should the error paths (err_notifier, err_ctx) call pm_runtime_disable() to
clean up the enable count properly?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=2
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 01/18] arm64: dts: ti: k3-{j721e/j721s2}-main: Fix indentation in CSI2RX node Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 02/18] arm64: dts: ti: k3-j721e-main: Add multiple channels for CSI2RX DMA Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:48 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: " Yemike Abhilash Chandra
` (14 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts. Add
additional DMA channels to enable multistream support for CSI2RX.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 5cac119e4292..f4b8713873b1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1239,8 +1239,11 @@ ti_csi2rx0: ticsi2rx@4500000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x4940 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
+ <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
+ <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
+ <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
@@ -1295,8 +1298,11 @@ ti_csi2rx1: ticsi2rx@4510000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x4960 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>,
+ <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>,
+ <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>,
+ <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 ` [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: " Yemike Abhilash Chandra
@ 2026-07-13 11:48 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:48 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: devicetree, conor+dt, imx, Frank.Li, robh
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
Pre-existing issues:
- [High] Leakage of allocated DMA channels during driver probe error paths due to flawed PM runtime status check.
- [High] Missing `pm_runtime_disable()` in the `ti_csi2rx_probe` error path.
- [High] Leakage of successfully requested DMA channels on partial `runtime_resume` failures.
- [High] Unreachable stream validation error check silently ignores missing streams.
--
--- Patch [3]: [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: Add multiple channels for CSI2RX DMA ---
commit aa226bddd4872f73702e34f1bec61a88480652a0
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-j721s2-main: Add multiple channels for CSI2RX DMA
This commit adds additional DMA channels to the J721E CSI2RX SHIM layer
device tree node. It enables multistream support by expanding the dmas
and dma-names properties to handle up to 8 channels per node.
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 5cac119e4292a..f4b8713873b17 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -1239,8 +1239,11 @@ ti_csi2rx0: ticsi2rx@4500000 {
> ranges;
> #address-cells = <2>;
> #size-cells = <2>;
> - dmas = <&main_bcdma_csi 0 0x4940 0>;
> - dma-names = "rx0";
> + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
> + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
> + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
> + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
> + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
[Severity: High]
This isn't a bug introduced by this patch, but scaling up the number of
channels in the device tree makes a DMA channel leak regression worse on
probe errors in the driver.
If ti_csi2rx_probe() in drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
fails midway through initializing these new contexts, it cleans up here:
err_ctx:
while (i--)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
However, ti_csi2rx_cleanup_ctx() has this check:
if (!pm_runtime_status_suspended(ctx->csi->dev))
dma_release_channel(ctx->dma.chan);
Since pm_runtime_set_active() hasn't been called yet during early probe,
the device is still in its default RPM_SUSPENDED state. Will this cause
the DMA channels to be permanently leaked when probe fails?
[Severity: High]
This is another pre-existing issue, but the addition of multiple DMA channels
also increases the impact of a leak during runtime resume:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_runtime_resume()
for (unsigned int i = 0; i < csi->num_ctx; i++) {
ret = ti_csi2rx_init_dma(&csi->ctx[i]);
if (ret)
return ret;
}
If ti_csi2rx_init_dma() fails for a later channel (e.g., rx4), the function
returns immediately without an error unwind path. Do the channels
successfully requested in earlier iterations get stranded indefinitely since
runtime_suspend won't be called?
[Severity: High]
This is a pre-existing issue in the probe error path that leaves a dangling
PM configuration:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_probe()
err_notifier:
ti_csi2rx_cleanup_notifier(csi);
err_ctx:
while (i--)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
ti_csi2rx_cleanup_v4l2(csi);
err_dma_chan:
dma_free_coherent(csi->dev, csi->drain.len, csi->drain.vaddr,
csi->drain.paddr);
return ret;
This path executes after pm_runtime_enable(csi->dev) has been called. Should
pm_runtime_disable() be called here before returning to unroll the PM
enablement?
[Severity: High]
This is a pre-existing issue, but it breaks stream validation for multistream
setups.
In ti_csi2rx_get_vc_and_dt(), the loop searches for a matching stream:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_get_vc_and_dt()
for (j = 0; j < fd.num_entries; j++) {
...
/* Return error if no matching stream found */
if (j == fd.num_entries)
return -EINVAL;
}
Since the if statement is completely inside the for-loop where
j < fd.num_entries, it is mathematically impossible for the condition to
evaluate to true. Could the driver silently proceed with incorrect
hardware configurations if a requested stream is missing?
> power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
> status = "disabled";
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=3
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (2 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 03/18] arm64: dts: ti: k3-j721s2-main: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:50 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: " Yemike Abhilash Chandra
` (13 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts,
Add additional DMA channels to enable multistream support for CSI2RX.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
.../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 21 +++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18..4b4545a5af19 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -811,8 +811,11 @@ ti_csi2rx0: ticsi2rx@4500000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x4940 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
+ <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
+ <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
+ <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
@@ -867,8 +870,11 @@ ti_csi2rx1: ticsi2rx@4510000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x4960 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>,
+ <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>,
+ <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>,
+ <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
@@ -922,8 +928,11 @@ ti_csi2rx2: ticsi2rx@4520000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x4980 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x4980 0>, <&main_bcdma_csi 0 0x4981 0>,
+ <&main_bcdma_csi 0 0x4982 0>, <&main_bcdma_csi 0 0x4983 0>,
+ <&main_bcdma_csi 0 0x4984 0>, <&main_bcdma_csi 0 0x4985 0>,
+ <&main_bcdma_csi 0 0x4986 0>, <&main_bcdma_csi 0 0x4987 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 ` [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: " Yemike Abhilash Chandra
@ 2026-07-13 11:50 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:50 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: conor+dt, robh, devicetree, Frank.Li, imx
Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
Pre-existing issues:
- [High] DMA channel leak on probe failure due to incorrect PM status check.
- [High] DMA channels are leaked on module removal if the device is active.
- [High] Missing pm_runtime_disable() on probe error paths.
- [High] DMA channel leak on error path in ti_csi2rx_runtime_resume().
- [High] DMA drain transaction is instantly aborted during system suspend.
--
--- Patch [4]: [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add multiple channels for CSI2RX DMA ---
commit ebceec6da92de871c7ab51be87cc009f8c4d7c16
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-j784s4-j742s2-main-common: Add multiple channels for CSI2RX DMA
This commit expands the CSI2RX SHIM layer configuration in the device tree
to support up to 8 DMA channel contexts. This change enables multistream
support for CSI2RX by adding the necessary DMA mappings.
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index c2636e624f18b..4b4545a5af192 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -811,8 +811,11 @@ ti_csi2rx0: ticsi2rx@4500000 {
> ranges;
> #address-cells = <2>;
> #size-cells = <2>;
> - dmas = <&main_bcdma_csi 0 0x4940 0>;
> - dma-names = "rx0";
> + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
> + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
> + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
> + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
> + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
[Severity: High]
This is a pre-existing issue, but expanding the channel count makes a
multi-iteration failure during initialization more likely.
If ti_csi2rx_init_ctx() fails for a later context in ti_csi2rx_probe(), it
jumps to err_ctx to clean up previously successful contexts. However,
pm_runtime_set_active() has not been called yet, so the device is
considered suspended:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_cleanup_ctx() {
...
if (!pm_runtime_status_suspended(ctx->csi->dev))
dma_release_channel(ctx->dma.chan);
...
}
Will this skip the DMA release and leak the successfully requested channels?
[Severity: High]
This is a pre-existing issue, but does a partial failure during runtime
resume also cause a permanent leak of previously allocated DMA channels?
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_runtime_resume() {
...
for (unsigned int i = 0; i < csi->num_ctx; i++) {
ret = ti_csi2rx_init_dma(&csi->ctx[i]);
if (ret)
return ret;
}
...
}
If ti_csi2rx_init_dma() fails for a later context, it returns immediately
without freeing the channels allocated for previous contexts. Since the next
resume attempt will re-allocate new channels, do the old channels become
permanently leaked?
[Severity: High]
This is a pre-existing issue, but does module removal also leak all 8
channels if the device is active?
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_remove() {
...
if (!pm_runtime_status_suspended(&pdev->dev))
pm_runtime_set_suspended(&pdev->dev);
...
}
This forcefully manipulates the internal PM state to suspended without
invoking the runtime_suspend callback. When ti_csi2rx_cleanup_ctx() is
called immediately afterward, it sees the newly set suspended state and
skips calling dma_release_channel(). Can this be avoided so channels are
properly released?
[Severity: High]
This is a pre-existing issue, but do the probe error paths leave the PM
state unbalanced?
pm_runtime_enable() is called earlier in probe, but pm_runtime_disable()
appears to be missing on the error paths:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_probe() {
...
err_notifier:
ti_csi2rx_cleanup_notifier(csi);
err_ctx:
while (i--)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
...
}
If ti_csi2rx_notifier_register() or subsequent initialization steps fail,
the driver returns an error but leaves the device improperly registered with
the PM framework. Should a pm_runtime_disable() be added here?
[Severity: High]
This is a pre-existing issue, but is the asynchronous DMA drain transaction
instantly aborted during system suspend?
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_suspend() {
...
/* Drain DMA */
ti_csi2rx_drain_dma(ctx);
/* Terminate DMA */
ret = dmaengine_terminate_sync(ctx->dma.chan);
...
}
The driver submits an asynchronous DMA drain transaction via
ti_csi2rx_drain_dma(), but immediately calls dmaengine_terminate_sync()
without waiting for it to complete. Does this synchronously terminate the
drain transfer before it can execute, potentially leaving stale data in the
hardware FIFO?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (3 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 04/18] arm64: dts: ti: k3-j784s4-j742s2-main-common: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:49 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 06/18] arm64: dts: ti: k3-j722s-main: " Yemike Abhilash Chandra
` (12 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts,
Add additional DMA channels to enable multistream support for CSI2RX.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index f130c7cb998d..ecb537b96fca 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1053,8 +1053,10 @@ ti_csi2rx0: ticsi2rx@30102000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x5000 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>,
+ <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>,
+ <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 ` [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: " Yemike Abhilash Chandra
@ 2026-07-13 11:49 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:49 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: robh, devicetree, conor+dt, imx, Frank.Li
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Medium] Incomplete multistream implementation for J722S SoC: missing DMA channels for CSI2RX instances 1, 2, and 3.
Pre-existing issues:
- [High] The driver j721e-csi2rx.c leaks DMA channels on probe error, remove, and runtime_resume.
--
--- Patch [5]: [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: Add multiple channels for CSI2RX DMA ---
commit 57c14c001a8a9799dd013f93cc44d67678cdb58d
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-am62p-j722s: Add multiple channels for CSI2RX DMA
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts. This patch
adds additional DMA channels to enable multistream support for CSI2RX.
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> index f130c7cb998d7..ecb537b96fcaa 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> @@ -1053,8 +1053,10 @@ ti_csi2rx0: ticsi2rx@30102000 {
> ranges;
> #address-cells = <2>;
> #size-cells = <2>;
> - dmas = <&main_bcdma_csi 0 0x5000 0>;
> - dma-names = "rx0";
> + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>,
> + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>,
> + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>;
> + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5";
[Severity: High]
This isn't a bug introduced by this patch, but increasing the number of DMA
channels here heavily amplifies a channel leak in the j721e-csi2rx.c driver.
When probe fails after channels are requested, ti_csi2rx_cleanup_ctx() checks
the PM runtime status:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_cleanup_ctx() {
if (!pm_runtime_status_suspended(ctx->csi->dev))
dma_release_channel(ctx->dma.chan);
}
Since the PM status is default suspended during a probe failure, the channels
are never released.
Similarly, during driver removal, the driver calls pm_runtime_set_suspended()
before cleaning up contexts, causing the same leak for active devices:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_remove() {
if (!pm_runtime_status_suspended(&pdev->dev))
pm_runtime_set_suspended(&pdev->dev);
for (unsigned int i = 0; i < csi->num_ctx; i++)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
}
Finally, by increasing the context count to 6 here, this activates a mid-loop
failure path in ti_csi2rx_runtime_resume() that was impossible with 1 channel:
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:ti_csi2rx_runtime_resume() {
for (unsigned int i = 0; i < csi->num_ctx; i++) {
ret = ti_csi2rx_init_dma(&csi->ctx[i]);
if (ret)
return ret;
}
}
If ti_csi2rx_init_dma() fails at i=1, does this return without releasing the
channel successfully requested at i=0? Would it be possible to address these
leaks in the driver prior to or alongside expanding the channel counts in
the DT?
[Severity: Medium]
Are there missing multistream DMA channel definitions for the other CSI2RX
instances?
The J722S SoC has four identical instances (ti_csi2rx0 through ti_csi2rx3).
While this updates ti_csi2rx0 in k3-am62p-j722s-common-main.dtsi, the other
instances in k3-j722s-main.dtsi appear to still only have one DMA context:
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi:ti_csi2rx1() {
...
dmas = <&main_bcdma_csi 0 0x5100 0>;
dma-names = "rx0";
...
}
If a user connects a multistream camera to CSI ports 1, 2, or 3, will they
be prevented from using multistream capture because rx1 through rx5 are not
defined? Should instances 1 through 3 be updated to match ti_csi2rx0?
> power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
> status = "disabled";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=5
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 06/18] arm64: dts: ti: k3-j722s-main: Add multiple channels for CSI2RX DMA
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (4 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 05/18] arm64: dts: ti: k3-am62p-j722s: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 07/18] arm64: dts: ti: k3-j721e: Add overlay for fusion application daughter board Yemike Abhilash Chandra
` (11 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J721E CSI2RX SHIM layer can support up to 32 DMA channel contexts,
Add additional DMA channels to enable multistream support for CSI2RX.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Tested-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 5a5b9a1bfd9e..199c8652bcde 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -173,8 +173,9 @@ ti_csi2rx1: ticsi2rx@30122000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x5100 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x5100 0>, <&main_bcdma_csi 0 0x5101 0>,
+ <&main_bcdma_csi 0 0x5102 0>, <&main_bcdma_csi 0 0x5103 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3";
power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
@@ -230,8 +231,9 @@ ti_csi2rx2: ticsi2rx@30142000 {
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
- dmas = <&main_bcdma_csi 0 0x5200 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x5200 0>, <&main_bcdma_csi 0 0x5201 0>,
+ <&main_bcdma_csi 0 0x5202 0>, <&main_bcdma_csi 0 0x5203 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3";
status = "disabled";
cdns_csi2rx2: csi-bridge@30141000 {
@@ -285,8 +287,9 @@ ti_csi2rx3: ticsi2rx@30162000 {
ranges;
#address-cells = <2>;
#size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x5300 0>;
- dma-names = "rx0";
+ dmas = <&main_bcdma_csi 0 0x5300 0>, <&main_bcdma_csi 0 0x5301 0>,
+ <&main_bcdma_csi 0 0x5302 0>, <&main_bcdma_csi 0 0x5303 0>;
+ dma-names = "rx0", "rx1", "rx2", "rx3";
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 07/18] arm64: dts: ti: k3-j721e: Add overlay for fusion application daughter board
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (5 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 06/18] arm64: dts: ti: k3-j722s-main: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 08/18] arm64: dts: ti: k3-j721s2: " Yemike Abhilash Chandra
` (10 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Fusion application daughter board [1] can be used to connect multiple
FPDLink-III based sensors to TI EVMs. The board has two DS90UB960
deserializers, each of which aggregates input from up to 4x FPDLink-III
sensors. Up to 8x sensors can simultaneously stream over the two CSI RX
ports on J721E.
[1]: https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy0 endpoint for cdns_csi2rx0 (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../boot/dts/ti/k3-j721e-evm-fusion.dtso | 190 ++++++++++++++++++
2 files changed, 194 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 371f9a043fe5..350a8b5ad275 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -159,6 +159,7 @@ k3-j721e-evm-gesi-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-gesi-exp-b
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
@@ -314,6 +315,8 @@ k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
k3-j7200-evm-pcie1-ep.dtbo
k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-common-proc-board-infotainment.dtbo
+k3-j721e-evm-fpdlink-fusion-dtbs := k3-j721e-evm.dtb \
+ k3-j721e-evm-fusion.dtbo
k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie0-ep.dtbo
k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
@@ -393,6 +396,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am69-sk-pcie0-ep.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
+ k3-j721e-evm-fpdlink-fusion.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso
new file mode 100644
index 000000000000..c9d8d8718891
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Fusion (FPD-Link III) board on J721E EVM
+ * https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&main_i2c6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ deser@3d {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@36 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x36>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 08/18] arm64: dts: ti: k3-j721s2: Add overlay for fusion application daughter board
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (6 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 07/18] arm64: dts: ti: k3-j721e: Add overlay for fusion application daughter board Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 09/18] arm64: dts: ti: k3-j721e-sk: " Yemike Abhilash Chandra
` (9 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Fusion application daughter board [1] can be used to connect multiple
FPDLink-III based sensors to TI EVMs. The board has two DS90UB960
deserializers, each of which aggregates input from up to 4x FPDLink-III
sensors. Up to 8x sensors can simultaneously stream over the two CSI RX
ports on J721S2.
CSI2RX connectivity on J784S4 and J742S2 is the same as that of J721S2,
hence the same overlay can be reused.
[1]: https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy0 endpoint for cdns_csi2rx0 (sashiko)
- Add missing build targets in Makefile (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 10 +
.../boot/dts/ti/k3-j721s2-evm-fusion.dtso | 190 ++++++++++++++++++
2 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 350a8b5ad275..893cdd31209a 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -178,6 +178,7 @@ k3-am68-phyboard-izar-peb-av-15-dtbs := k3-am68-phyboard-izar.dtb \
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
@@ -323,6 +324,8 @@ k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie1-ep.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
+k3-j721s2-evm-fpdlink-fusion-dtbs := k3-j721s2-evm.dtb \
+ k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -331,8 +334,12 @@ k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
+k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
+ k3-j721s2-evm-fusion.dtbo
k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
k3-j784s4-j742s2-evm-usb0-type-a.dtbo
+k3-j784s4-evm-fpdlink-fusion-dtbs := k3-j784s4-evm.dtb \
+ k3-j721s2-evm-fusion.dtbo
k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtbo
k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
@@ -400,11 +407,14 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
+ k3-j721s2-evm-fpdlink-fusion.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
+ k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
+ k3-j784s4-evm-fpdlink-fusion.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtb \
k3-j784s4-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso
new file mode 100644
index 000000000000..9bd4b86cb879
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Fusion (FPD-Link III) board on J721S2, J784S4 and J742S2 EVM
+ * https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&main_i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ deser@3d {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@36 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x36>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 09/18] arm64: dts: ti: k3-j721e-sk: Add overlay for fusion application daughter board
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (7 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 08/18] arm64: dts: ti: k3-j721s2: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 10/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
` (8 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Fusion application daughter board [1] can be used to connect multiple
FPDLink-III based sensors to TI EVMs. The board has two DS90UB960
deserializers, each of which aggregates input from up to 4x FPDLink-III
sensors. Up to 8x sensors can simultaneously stream over the two CSI RX
ports on J721E SK.
CSI2RX connectivity on AM68-SK and AM69-SK is the same as that of J721E-SK,
hence the same overlay can be reused.
[1]: https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy0 endpoint for cdns_csi2rx0 (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 10 +
.../dts/ti/k3-j721e-sk-fpdlink-fusion.dtso | 190 ++++++++++++++++++
2 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 893cdd31209a..804f041ba408 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-fpdlink-fusion.dtbo
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar.dtb
@@ -308,8 +309,12 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \
k3-am68-sk-base-board-pcie1-ep.dtbo
+k3-am68-sk-fpdlink-fusion-dtbs := k3-am68-sk-base-board.dtb \
+ k3-j721e-sk-fpdlink-fusion.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
+k3-am69-sk-fpdlink-fusion-dtbs := k3-am69-sk.dtb \
+ k3-j721e-sk-fpdlink-fusion.dtbo
k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \
k3-am69-sk-pcie0-ep.dtbo
k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
@@ -324,6 +329,8 @@ k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie1-ep.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
+k3-j721e-sk-fpdlink-fusion-dtbs := k3-j721e-sk.dtb \
+ k3-j721e-sk-fpdlink-fusion.dtbo
k3-j721s2-evm-fpdlink-fusion-dtbs := k3-j721s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -399,7 +406,9 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am68-phyboard-izar-peb-av-15.dtb \
k3-am68-sk-base-board-csi2-dual-imx219.dtb \
k3-am68-sk-base-board-pcie1-ep.dtb \
+ k3-am68-sk-fpdlink-fusion.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
+ k3-am69-sk-fpdlink-fusion.dtb \
k3-am69-sk-pcie0-ep.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
@@ -407,6 +416,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
+ k3-j721e-sk-fpdlink-fusion.dtb \
k3-j721s2-evm-fpdlink-fusion.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso
new file mode 100644
index 000000000000..d9c2f83e80b6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Fusion (FPD-Link III) board on J721E SK,
+ * AM68 SK and AM69 SK.
+ * https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&cam0_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deser@3d {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX*/
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@36 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x36>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX*/
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 10/18] arm64: dts: ti: k3-j722s-evm: Add overlay for fusion application daughter board
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (8 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 09/18] arm64: dts: ti: k3-j721e-sk: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion Yemike Abhilash Chandra
` (7 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Fusion application daughter board [1] can be used to connect multiple
FPDLink-III based sensors to TI EVMs. The board has two DS90UB960
deserializers, each of which aggregates input from up to 4x FPDLink-III
sensors. Up to 8x sensors can simultaneously stream over the two CSI RX
ports on J722S EVM.
[1]: https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in both csi2_phy endpoints (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../dts/ti/k3-j722s-evm-fpdlink-fusion.dtso | 196 ++++++++++++++++++
2 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 804f041ba408..1d876abb0585 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -191,6 +191,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb
@@ -341,6 +342,8 @@ k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
+k3-j722s-evm-fpdlink-fusion-dtbs := k3-j722s-evm.dtb \
+ k3-j722s-evm-fpdlink-fusion.dtbo
k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
@@ -422,6 +425,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
+ k3-j722s-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
k3-j784s4-evm-fpdlink-fusion.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso
new file mode 100644
index 000000000000..3b2601443290
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Fusion (FPD-Link III) board on J722S EVM
+ * https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&pca9543_0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deser@3d {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ ds90ub960_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ ds90ub960_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@36 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x36>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ ds90ub960_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ ds90ub960_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (9 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 10/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:47 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
` (6 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Arducam's V3Link mini fusion board [1] has a single DS90UB960
deserializer which can aggregate input from up to 4x V3Link (and
FPD-Link III) based cameras over a single 22-pin FFC (4-lane) CSI-2
connector. Add an overlay supporting two such boards, each connected to
one of the two CSI RX inputs on AM68-SK.
The same overlay can be reused on AM69-SK and J721E-SK.
[1] https://www.arducam.com/downloads/datasheet/Arducam_V3Link_Datasheet.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h and pinctrl.h headers (sashiko)
arch/arm64/boot/dts/ti/Makefile | 10 +
.../boot/dts/ti/k3-am68-sk-v3link-fusion.dtso | 200 ++++++++++++++++++
2 files changed, 210 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 1d876abb0585..fdd94cb7667e 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -178,6 +178,7 @@ k3-am68-phyboard-izar-peb-av-15-dtbs := k3-am68-phyboard-izar.dtb \
k3-am68-phyboard-izar-peb-av-15.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-v3link-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
@@ -312,12 +313,16 @@ k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \
k3-am68-sk-base-board-pcie1-ep.dtbo
k3-am68-sk-fpdlink-fusion-dtbs := k3-am68-sk-base-board.dtb \
k3-j721e-sk-fpdlink-fusion.dtbo
+k3-am68-sk-v3link-fusion-dtbs := k3-am68-sk-base-board.dtb \
+ k3-am68-sk-v3link-fusion.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am69-sk-fpdlink-fusion-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-fpdlink-fusion.dtbo
k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \
k3-am69-sk-pcie0-ep.dtbo
+k3-am69-sk-v3link-fusion-dtbs := k3-am69-sk.dtb \
+ k3-am68-sk-v3link-fusion.dtbo
k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
k3-j7200-evm-pcie1-ep.dtbo
k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
@@ -332,6 +337,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721e-sk-fpdlink-fusion-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-fpdlink-fusion.dtbo
+k3-j721e-sk-v3link-fusion-dtbs := k3-j721e-sk.dtb \
+ k3-am68-sk-v3link-fusion.dtbo
k3-j721s2-evm-fpdlink-fusion-dtbs := k3-j721s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -410,9 +417,11 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am68-sk-base-board-csi2-dual-imx219.dtb \
k3-am68-sk-base-board-pcie1-ep.dtb \
k3-am68-sk-fpdlink-fusion.dtb \
+ k3-am68-sk-v3link-fusion.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
k3-am69-sk-fpdlink-fusion.dtb \
k3-am69-sk-pcie0-ep.dtb \
+ k3-am69-sk-v3link-fusion.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
k3-j721e-evm-fpdlink-fusion.dtb \
@@ -420,6 +429,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
k3-j721e-sk-fpdlink-fusion.dtb \
+ k3-j721e-sk-v3link-fusion.dtb \
k3-j721s2-evm-fpdlink-fusion.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso b/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso
new file mode 100644
index 000000000000..b293deede638
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Arducam V3Link UC-A09 board
+ * https://www.arducam.com/fpd-link-3-cameras/
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&csi_mux {
+ idle-state = <1>;
+};
+
+&cam0_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deser@30 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x30>;
+
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cam1_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deser@30 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x30>;
+
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg= <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion
2026-07-13 11:34 ` [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion Yemike Abhilash Chandra
@ 2026-07-13 11:47 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:47 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: imx, Frank.Li, conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing space around '=' in property assignment.
--
--- Patch [11]: [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion ---
commit f16de548646cfb8ded4d412b513b2b6f314dbb9d
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion
This commit adds a device tree overlay supporting two Arducam V3Link mini
fusion boards, each connected to one of the two CSI RX inputs on the AM68-SK.
The overlay configures the DS90UB960 deserializers to aggregate inputs from
up to four cameras over a single CSI-2 connector.
Link: https://www.arducam.com/downloads/datasheet/Arducam_V3Link_Datasheet.pdf
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso b/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso
> new file mode 100644
> index 0000000000000..b293deede6380
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso
[ ... ]
> +&cam1_i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + deser@30 {
> + compatible = "ti,ds90ub960-q1";
> + reg = <0x30>;
[ ... ]
> + deserializer_1_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + port@1 {
> + reg= <1>;
[Severity: Low]
This isn't a bug, but there is a missing space before the equals sign here.
The v2 changelog mentions fixing minor DTS styling and whitespace
inconsistencies in port definitions, so was this one missed?
> + status = "disabled";
> + };
> +
> + port@2 {
> + reg = <2>;
> + status = "disabled";
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=11
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: Add overlay for dual Arducam V3link fusion
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (10 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 11/18] arm64: dts: ti: k3-am68-sk: Add overlay for dual Arducam V3link fusion Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:45 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2 Yemike Abhilash Chandra
` (5 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
Arducam's V3Link mini fusion board [1] has a single DS90UB960
deserializer which can aggregate input from up to 4x V3Link (and
FPD-Link III) based cameras over a single 22-pin FFC (4-lane) CSI-2
connector. Add an overlay supporting two such boards, each connected to
one of the two CSI RX inputs on J722S.
[1] https://www.arducam.com/downloads/datasheet/Arducam_V3Link_Datasheet.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in both csi2_phy endpoints (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../dts/ti/k3-j722s-evm-v3link-fusion.dtso | 213 ++++++++++++++++++
2 files changed, 217 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index fdd94cb7667e..a9ee359f2604 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb
@@ -351,6 +352,8 @@ k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
k3-j722s-evm-fpdlink-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-fpdlink-fusion.dtbo
+k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \
+ k3-j722s-evm-v3link-fusion.dtbo
k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
@@ -436,6 +439,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
k3-j722s-evm-fpdlink-fusion.dtb \
+ k3-j722s-evm-v3link-fusion.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
k3-j784s4-evm-fpdlink-fusion.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso
new file mode 100644
index 000000000000..b27c53015e6c
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Arducam V3Link UC-A09 board
+ * https://www.arducam.com/fpd-link-3-cameras/
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&csi01_mux {
+ idle-state = <1>;
+};
+
+&csi23_mux {
+ idle-state = <1>;
+};
+
+&pca9543_0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* CAM0 I2C */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deser@30 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x30>;
+
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_0_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ /* CAM1 I2C */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ deser@30 {
+ compatible = "ti,ds90ub960-q1";
+ reg = <0x30>;
+
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub960_1_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub960_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: Add overlay for dual Arducam V3link fusion
2026-07-13 11:34 ` [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
@ 2026-07-13 11:45 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:45 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: conor+dt, devicetree, robh, Frank.Li, imx
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The v2 changelog claims to 'Fix minor DTS styling and whitespace inconsistencies in port definitions', but an improperly indented closing bracket remains.
--
--- Patch [12]: [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: Add overlay for dual Arducam V3link fusion ---
commit aaa6a2127a8b86a7d8034ebb013436530699b645
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-j722s-evm: Add overlay for dual Arducam V3link fusion
This commit adds a device tree overlay for two Arducam V3Link mini fusion
boards, connecting them to the two CSI RX inputs on the J722S EVM. Each
board features a single DS90UB960 deserializer capable of aggregating input
from up to four cameras.
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso
> new file mode 100644
> index 0000000000000..b27c53015e6ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso
[ ... ]
> + /* CAM1 I2C */
> + i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + deser@30 {
> + compatible = "ti,ds90ub960-q1";
> + reg = <0x30>;
> +
> + clock-names = "refclk";
> + clocks = <&clk_fusion_25M_fixed>;
> +
> + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
> +
> + deserializer_1_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + status = "disabled";
> + };
[Severity: Low]
This isn't a functional bug, but the v2 changelog claims to "Fix minor DTS
styling and whitespace inconsistencies in port definitions". Was this extra
indentation on the closing bracket for port@0 missed during that cleanup?
> +
> + port@1 {
> + reg = <1>;
> + status = "disabled";
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=12
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (11 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 12/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:45 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
` (4 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Vaishnav Achath <vaishnav.a@ti.com>
J7EXPA01EVM Fusion2 serial capture expansion board features 3 UB9702
deserializers, each capable of aggregating data from up to 4x cameras
over the FPDLink-IV interface. Add support for the same on J784S4-EVM.
EVM schematics and design files : https://www.ti.com/tool/J7EXPA01EVM
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso | 282 ++++++++++++++++++
2 files changed, 286 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index a9ee359f2604..2dc4f9043258 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -201,6 +201,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-fpdlink-iv-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
@@ -360,6 +361,8 @@ k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
k3-j784s4-j742s2-evm-usb0-type-a.dtbo
k3-j784s4-evm-fpdlink-fusion-dtbs := k3-j784s4-evm.dtb \
k3-j721s2-evm-fusion.dtbo
+k3-j784s4-evm-fpdlink-iv-fusion-dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-fpdlink-iv-fusion.dtbo
k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtbo
k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
@@ -443,6 +446,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
k3-j784s4-evm-fpdlink-fusion.dtb \
+ k3-j784s4-evm-fpdlink-iv-fusion.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtb \
k3-j784s4-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso
new file mode 100644
index 000000000000..0f95d19ebd17
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * DT Overlay for FPDLink IV UB9702 Deserializer on J784S4 EVM
+ * https://www.ti.com/tool/J7EXPA01EVM
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&exp5 {
+ p0-hog{
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CSI2_EXP_RSTZ";
+ };
+};
+
+&main_i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ deser@3d {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_0_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@30 {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x30>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_1_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@32 {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x32>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>;
+
+ deserializer_2_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0{
+ reg= <0>;
+ status = "disabled";
+ };
+
+ port@1{
+ reg= <1>;
+ status = "disabled";
+ };
+
+ port@2{
+ reg= <2>;
+ status = "disabled";
+ };
+
+ port@3{
+ reg= <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_2_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy2>;
+ };
+ };
+
+ port@5{
+ reg= <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_2_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub970_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub970_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy2: endpoint {
+ remote-endpoint = <&ds90ub970_2_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&ti_csi2rx2 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
+
+&dphy2 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2
2026-07-13 11:34 ` [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2 Yemike Abhilash Chandra
@ 2026-07-13 11:45 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:45 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: robh, devicetree, imx, Frank.Li, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit message claims to have fixed DTS styling and whitespace inconsistencies in port definitions, but these fixes were not applied to the third deserializer ('deser@32').
--
--- Patch [13]: [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2 ---
commit c8270b1db48b4db03ed35600960afc0c87b8b5ff
Author: Vaishnav Achath <vaishnav.a@ti.com>
arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2
This commit adds a device tree overlay to support the J7EXPA01EVM Fusion2
serial capture expansion board on the J784S4-EVM. The board features three
UB9702 deserializers aggregating data over the FPDLink-IV interface.
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso
> new file mode 100644
> index 0000000000000..0f95d19ebd175
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso
[ ... ]
> + deser@32 {
> + compatible = "ti,ds90ub9702-q1";
> + reg = <0x32>;
> + clocks = <&clk_fusion_25M_fixed>;
> + clock-names = "refclk";
> + i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>;
> +
> + deserializer_2_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0{
> + reg= <0>;
> + status = "disabled";
> + };
[Severity: Low]
This isn't a bug, but the v2 changelog mentions fixing DTS styling and
whitespace inconsistencies in the port definitions. Did these fixes get
missed for the third deserializer (deser@32)?
The first two deserializers correctly use "port@0 {" and "reg = <0>;", while
these nodes still have missing spaces around the curly braces and equals sign.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=13
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: Add overlay for J7EXPA01EVM Fusion2
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (12 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 13/18] arm64: dts: ti: k3-j784s4-evm: Add overlay for J7EXPA01EVM Fusion2 Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:47 ` sashiko-bot
2026-07-13 11:34 ` [PATCH v2 15/18] arm64: dts: ti: k3-j721s2: Add overlay for DS90UB954-Q1EVM Yemike Abhilash Chandra
` (3 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
J7EXPA01EVM Fusion2 serial capture expansion board features 3 UB9702
deserializers, each capable of aggregating data from up to 4x cameras
over the FPDLink-IV interface. Add support for the same on J722S-EVM.
EVM schematics and design files : https://www.ti.com/tool/J7EXPA01EVM
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy endpoints (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../ti/k3-j722s-evm-fpdlink-iv-fusion.dtso | 299 ++++++++++++++++++
2 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 2dc4f9043258..6b1e15855b97 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-iv-fusion.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo
# Boards with J784s4 SoC
@@ -353,6 +354,8 @@ k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
k3-j722s-evm-fpdlink-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-fpdlink-fusion.dtbo
+k3-j722s-evm-fpdlink-iv-fusion-dtbs := k3-j722s-evm.dtb \
+ k3-j722s-evm-fpdlink-iv-fusion.dtbo
k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-v3link-fusion.dtbo
k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
@@ -442,6 +445,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
k3-j722s-evm-fpdlink-fusion.dtb \
+ k3-j722s-evm-fpdlink-iv-fusion.dtb \
k3-j722s-evm-v3link-fusion.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso
new file mode 100644
index 000000000000..ed8fdfa65005
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * DT Overlay for FPDLink IV UB9702 Deserializer on J722S
+ * https://www.ti.com/tool/J7EXPA01EVM
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&main_pmx0 {
+ csi_expansion_interface_reset: csi-expansion-interface-reset-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x114, PIN_OUTPUT, 7) /* (G26) GPIO0_68 */
+ >;
+ };
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_expansion_interface_reset>;
+
+ line68-hog{
+ gpio-hog;
+ gpios = <68 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CSI2_EXP_RSTZ";
+ };
+};
+
+&pca9543_0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deser@3d {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x3d>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0{
+ reg= <0>;
+ status = "disabled";
+ };
+
+ port@1{
+ reg= <1>;
+ status = "disabled";
+ };
+
+ port@2{
+ reg= <2>;
+ status = "disabled";
+ };
+
+ port@3{
+ reg= <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_0_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+
+ port@5{
+ reg= <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@30 {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x30>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;
+
+ deserializer_1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_1_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_1_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ deser@32 {
+ compatible = "ti,ds90ub9702-q1";
+ reg = <0x32>;
+ clocks = <&clk_fusion_25M_fixed>;
+ clock-names = "refclk";
+ i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>;
+
+ deserializer_2_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@4 {
+ reg = <4>;
+ ds90ub970_2_csi_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy2>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ deserializer_2_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub970_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy1: endpoint {
+ remote-endpoint = <&ds90ub970_1_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy2: endpoint {
+ remote-endpoint = <&ds90ub970_2_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
+
+&dphy1 {
+ status = "okay";
+};
+
+&ti_csi2rx2 {
+ status = "okay";
+};
+
+&dphy2 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: Add overlay for J7EXPA01EVM Fusion2
2026-07-13 11:34 ` [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
@ 2026-07-13 11:47 ` sashiko-bot
0 siblings, 0 replies; 27+ messages in thread
From: sashiko-bot @ 2026-07-13 11:47 UTC (permalink / raw)
To: Yemike Abhilash Chandra; +Cc: Frank.Li, imx, conor+dt, robh, devicetree
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Incomplete fix of whitespace and styling inconsistencies despite commit message claims.
- [Low] Assigning `pinctrl-0` directly to the shared `&main_gpio0` controller makes the overlay fragile and prone to silent conflicts.
--
--- Patch [14]: [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: Add overlay for J7EXPA01EVM Fusion2 ---
commit f6225e8592b3763543d75d2b7569bdc1e8dfb921
Author: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
arm64: dts: ti: k3-j722s-evm: Add overlay for J7EXPA01EVM Fusion2
This commit adds a device tree overlay to support the J7EXPA01EVM Fusion2
serial capture expansion board on the J722S-EVM. It defines configurations
for 3 UB9702 deserializers aggregating data over the FPDLink-IV interface.
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso
> new file mode 100644
> index 0000000000000..ed8fdfa65005e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso
[ ... ]
> +&main_gpio0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&csi_expansion_interface_reset>;
[Severity: Low]
Is it safe to assign pinctrl-0 directly to the shared &main_gpio0 controller
in an overlay?
Since DT overlays overwrite target properties, if another overlay also
relies on main_gpio0 and sets pinctrl-0, wouldn't they unconditionally
clobber each other's pinmux configurations? Should this be scoped strictly
to the localized line68-hog node instead?
Also, this isn't a bug, but there appear to be 8 spaces used for indentation
here rather than tabs. The v2 changelog mentioned fixing whitespace
inconsistencies, was this one missed?
> +
> + line68-hog{
[Severity: Low]
This isn't a bug, but there is a missing space before the brace here.
> + gpio-hog;
> + gpios = <68 GPIO_ACTIVE_HIGH>;
[ ... ]
> + deser@3d {
> + compatible = "ti,ds90ub9702-q1";
> + reg = <0x3d>;
> + clocks = <&clk_fusion_25M_fixed>;
> + clock-names = "refclk";
> + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
> +
> + deserializer_0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0{
> + reg= <0>;
> + status = "disabled";
> + };
[Severity: Low]
This isn't a bug, but the v2 changelog claims to fix DTS styling and
whitespace inconsistencies in port definitions.
It looks like there are still missing spaces before the braces and
after the equal sign for reg in the deser@3d port definitions.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713113423.2310443-1-y-abhilashchandra@ti.com?part=14
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 15/18] arm64: dts: ti: k3-j721s2: Add overlay for DS90UB954-Q1EVM
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (13 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 14/18] arm64: dts: ti: k3-j722s-evm: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 16/18] arm64: dts: ti: k3-j721e: " Yemike Abhilash Chandra
` (2 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
DS90UB954-Q1EVM consists of a DS90UB954 deserializer which aggregates
data from up to 2x cameras over the FPDLink-III interface, and can be
used to connect FPDLink-III based sensors to TI EVMs.
Add an overlay to support it on J721S2-EVM. CSI2RX connectivity on
J784S4 and J742S2 is the same as that of J721S2, hence the same overlay
can be reused.
Link: https://www.ti.com/tool/DS90UB954-Q1EVM
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy0 endpoint for cdns_csi2rx0 (sashiko)
- Add missing build targets in Makefile (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 10 ++
.../boot/dts/ti/k3-j721s2-evm-ub954.dtso | 92 +++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6b1e15855b97..529d85a0809c 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-ub954.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo
# Boards with J722s SoC
@@ -346,6 +347,8 @@ k3-j721s2-evm-fpdlink-fusion-dtbs := k3-j721s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
+k3-j721s2-evm-ub954-dtbs := k3-j721s2-evm.dtb \
+ k3-j721s2-evm-ub954.dtbo
k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-usb0-type-a.dtbo
k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \
@@ -360,6 +363,8 @@ k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-v3link-fusion.dtbo
k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
+k3-j742s2-evm-ub954-dtbs := k3-j742s2-evm.dtb \
+ k3-j721s2-evm-ub954.dtbo
k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
k3-j784s4-j742s2-evm-usb0-type-a.dtbo
k3-j784s4-evm-fpdlink-fusion-dtbs := k3-j784s4-evm.dtb \
@@ -370,6 +375,8 @@ k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtbo
k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtbo
+k3-j784s4-evm-ub954-dtbs := k3-j784s4-evm.dtb \
+ k3-j721s2-evm-ub954.dtbo
k3-j784s4-evm-usb0-type-a-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-j742s2-evm-usb0-type-a.dtbo
k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \
@@ -441,6 +448,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-sk-v3link-fusion.dtb \
k3-j721s2-evm-fpdlink-fusion.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
+ k3-j721s2-evm-ub954.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
@@ -448,11 +456,13 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j722s-evm-fpdlink-iv-fusion.dtb \
k3-j722s-evm-v3link-fusion.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
+ k3-j742s2-evm-ub954.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
k3-j784s4-evm-fpdlink-fusion.dtb \
k3-j784s4-evm-fpdlink-iv-fusion.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtb \
+ k3-j784s4-evm-ub954.dtb \
k3-j784s4-evm-usb0-type-a.dtb \
k3-j784s4-evm-usxgmii-exp1-exp2.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso
new file mode 100644
index 000000000000..3c87d0386496
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on J721S2, J784S4 and J742S2 EVM
+ * https://www.ti.com/tool/DS90UB954-Q1EVM
+ *
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&main_i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ deser@3d {
+ compatible = "ti,ds90ub954-q1";
+ reg = <0x3d>;
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@2 {
+ reg = <2>;
+ ds90ub960_0_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 16/18] arm64: dts: ti: k3-j721e: Add overlay for DS90UB954-Q1EVM
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (14 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 15/18] arm64: dts: ti: k3-j721s2: Add overlay for DS90UB954-Q1EVM Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 17/18] arm64: dts: ti: k3-v3link: Add overlay for IMX219+UB953 serializer Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 18/18] arm64: defconfig: Enable DS90UB960 deserializer and DS90UB953 serializer Yemike Abhilash Chandra
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
DS90UB954-Q1EVM consists of a DS90UB954 deserializer which aggregates
data from up to 2x cameras over the FPDLink-III interface, and can be
used to connect FPDLink-III based sensors to TI EVMs.
Add an overlay to support it on J721E-EVM.
Link: https://www.ti.com/tool/DS90UB954-Q1EVM
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add missing bus-type property in csi2_phy0 endpoint for cdns_csi2rx0 (sashiko)
- Add missing build targets in Makefile (sashiko)
- Fix minor DTS styling and whitespace inconsistencies in port definitions (sashiko)
- Remove unused gpio.h header (sashiko)
arch/arm64/boot/dts/ti/Makefile | 4 +
.../arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso | 92 +++++++++++++++++++
2 files changed, 96 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 529d85a0809c..c47c96ab5735 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -164,6 +164,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-ub954.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-fpdlink-fusion.dtbo
@@ -337,6 +338,8 @@ k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie0-ep.dtbo
k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie1-ep.dtbo
+k3-j721e-evm-ub954-dtbs := k3-j721e-common-proc-board.dtb \
+ k3-j721e-evm-ub954.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721e-sk-fpdlink-fusion-dtbs := k3-j721e-sk.dtb \
@@ -443,6 +446,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-fpdlink-fusion.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
+ k3-j721e-evm-ub954.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
k3-j721e-sk-fpdlink-fusion.dtb \
k3-j721e-sk-v3link-fusion.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso
new file mode 100644
index 000000000000..30b7bd90bb2b
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on J721E EVM
+ * https://www.ti.com/tool/DS90UB954-Q1EVM
+ *
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ clk_fusion_25M_fixed: fixed-clock-25M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+
+&main_i2c6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ deser@3d {
+ compatible = "ti,ds90ub954-q1";
+ reg = <0x3d>;
+ clock-names = "refclk";
+ clocks = <&clk_fusion_25M_fixed>;
+ i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+ deserializer_0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ /* CSI-2 TX */
+ port@2 {
+ reg = <2>;
+ ds90ub960_0_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ remote-endpoint = <&csi2_phy0>;
+ };
+ };
+ };
+
+ deserializer_0_links: links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2_phy0: endpoint {
+ remote-endpoint = <&ds90ub960_0_csi_out>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ link-frequencies = /bits/ 64 <800000000>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 17/18] arm64: dts: ti: k3-v3link: Add overlay for IMX219+UB953 serializer
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (15 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 16/18] arm64: dts: ti: k3-j721e: " Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
2026-07-13 11:34 ` [PATCH v2 18/18] arm64: defconfig: Enable DS90UB960 deserializer and DS90UB953 serializer Yemike Abhilash Chandra
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
From: Jianzhong Xu <xuj@ti.com>
Arducam V3Link camera solution is shipped with an UB953 serializer
and an IMX219 sensor[1]. Add an overlay for interfacing the UB953
serilaizer and IMX219 sensor with the RX0 port on the UB960 deserializer.
This overlay can be used to interface an IMX219 sensor on any platform
that supports the V3Link fusion board.
[1]: https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/
Signed-off-by: Jianzhong Xu <xuj@ti.com>
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Don't replacing generic V3Link fusion board DTB targets instead append new build
targets for v3link + IMX219 (sashiko)
- Add status = "okay" property in port 0 of deserializer ports (sashiko)
- Add port-specific suffixes to avoid naming collisions (sashiko)
arch/arm64/boot/dts/ti/Makefile | 19 +++
.../boot/dts/ti/k3-v3link-imx219-0-0.dtso | 128 ++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index c47c96ab5735..819e8a8c5c84 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -213,6 +213,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-j742s2-evm-usb0-type-a.dtbo
# Boards with J742S2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-j742s2-evm.dtb
+# IMX219 FPDLink Sensors
+dtb-$(CONFIG_ARCH_K3) += k3-v3link-imx219-0-0.dtbo
+
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
k3-am625-beagleplay-csi2-ov5640.dtbo
@@ -320,6 +323,9 @@ k3-am68-sk-fpdlink-fusion-dtbs := k3-am68-sk-base-board.dtb \
k3-j721e-sk-fpdlink-fusion.dtbo
k3-am68-sk-v3link-fusion-dtbs := k3-am68-sk-base-board.dtb \
k3-am68-sk-v3link-fusion.dtbo
+k3-am68-sk-v3link-fusion-imx219-dtbs := k3-am68-sk-base-board.dtb \
+ k3-am68-sk-v3link-fusion.dtbo \
+ k3-v3link-imx219-0-0.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am69-sk-fpdlink-fusion-dtbs := k3-am69-sk.dtb \
@@ -328,6 +334,9 @@ k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \
k3-am69-sk-pcie0-ep.dtbo
k3-am69-sk-v3link-fusion-dtbs := k3-am69-sk.dtb \
k3-am68-sk-v3link-fusion.dtbo
+k3-am69-sk-v3link-fusion-imx219-dtbs := k3-am69-sk.dtb \
+ k3-am68-sk-v3link-fusion.dtbo \
+ k3-v3link-imx219-0-0.dtbo
k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
k3-j7200-evm-pcie1-ep.dtbo
k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
@@ -346,6 +355,9 @@ k3-j721e-sk-fpdlink-fusion-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-fpdlink-fusion.dtbo
k3-j721e-sk-v3link-fusion-dtbs := k3-j721e-sk.dtb \
k3-am68-sk-v3link-fusion.dtbo
+k3-j721e-sk-v3link-fusion-imx219-dtbs := k3-j721e-sk.dtb \
+ k3-am68-sk-v3link-fusion.dtbo \
+ k3-v3link-imx219-0-0.dtbo
k3-j721s2-evm-fpdlink-fusion-dtbs := k3-j721s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -364,6 +376,9 @@ k3-j722s-evm-fpdlink-iv-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-fpdlink-iv-fusion.dtbo
k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \
k3-j722s-evm-v3link-fusion.dtbo
+k3-j722s-evm-v3link-fusion-imx219-dtbs := k3-j722s-evm.dtb \
+ k3-j722s-evm-v3link-fusion.dtbo \
+ k3-v3link-imx219-0-0.dtbo
k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \
k3-j721s2-evm-fusion.dtbo
k3-j742s2-evm-ub954-dtbs := k3-j742s2-evm.dtb \
@@ -437,10 +452,12 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am68-sk-base-board-pcie1-ep.dtb \
k3-am68-sk-fpdlink-fusion.dtb \
k3-am68-sk-v3link-fusion.dtb \
+ k3-am68-sk-v3link-fusion-imx219.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
k3-am69-sk-fpdlink-fusion.dtb \
k3-am69-sk-pcie0-ep.dtb \
k3-am69-sk-v3link-fusion.dtb \
+ k3-am69-sk-v3link-fusion-imx219.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
k3-j721e-evm-fpdlink-fusion.dtb \
@@ -450,6 +467,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
k3-j721e-sk-fpdlink-fusion.dtb \
k3-j721e-sk-v3link-fusion.dtb \
+ k3-j721e-sk-v3link-fusion-imx219.dtb \
k3-j721s2-evm-fpdlink-fusion.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j721s2-evm-ub954.dtb \
@@ -459,6 +477,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j722s-evm-fpdlink-fusion.dtb \
k3-j722s-evm-fpdlink-iv-fusion.dtb \
k3-j722s-evm-v3link-fusion.dtb \
+ k3-j722s-evm-v3link-fusion-imx219.dtb \
k3-j742s2-evm-fpdlink-fusion.dtb \
k3-j742s2-evm-ub954.dtb \
k3-j742s2-evm-usb0-type-a.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso b/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso
new file mode 100644
index 000000000000..c813cec6678f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IMX219 Camera Module for V3-Link d-ch Adapter Board
+ * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/
+ *
+ * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_imx219_fixed_00: imx219-xclk-00 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ reg_2p8v_00: regulator-2p8v_00 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ reg_1p8v_00: regulator-1p8v_00 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_1p2v_00: regulator-1p2v_00 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+};
+
+&deserializer_0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* FPDLink RX 0 */
+ port@0 {
+ reg = <0>;
+ status = "okay";
+
+ ub960_fpd3_1_in: endpoint {
+ remote-endpoint = <&ub953_1_out>;
+ };
+ };
+};
+
+&deserializer_0_links {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ link@0 {
+ reg = <0>;
+ i2c-alias = <0x44>;
+
+ ti,rx-mode = <3>;
+
+ serializer: serializer {
+ compatible = "ti,ds90ub953-q1";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ub953_1_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&sensor_1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ub953_1_out: endpoint {
+ remote-endpoint = <&ub960_fpd3_1_in>;
+ };
+ };
+ };
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_imx219_fixed_00>;
+
+ VANA-supply = <®_2p8v_00>;
+ VDIG-supply = <®_1p8v_00>;
+ VDDL-supply = <®_1p2v_00>;
+
+ reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>;
+
+ port {
+ sensor_1_out: endpoint {
+ remote-endpoint = <&ub953_1_in>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 18/18] arm64: defconfig: Enable DS90UB960 deserializer and DS90UB953 serializer
2026-07-13 11:34 [PATCH v2 00/18] Add DT support for CSI2RX multi-stream Yemike Abhilash Chandra
` (16 preceding siblings ...)
2026-07-13 11:34 ` [PATCH v2 17/18] arm64: dts: ti: k3-v3link: Add overlay for IMX219+UB953 serializer Yemike Abhilash Chandra
@ 2026-07-13 11:34 ` Yemike Abhilash Chandra
17 siblings, 0 replies; 27+ messages in thread
From: Yemike Abhilash Chandra @ 2026-07-13 11:34 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: Frank.Li, s.hauer, kernel, festevam, andersson, geert,
dmitry.baryshkov, arnd, ebiggers, luca.weiss, michal.simek, sven,
linux-arm-kernel, devicetree, linux-kernel, imx, r-donadkar,
devarsht, u-kumar1
The DS90UB960 deserializer and DS90UB953 serialzer facilite capturing
through multiple camera sensors on J7x and AM6x platforms. Some of the
supported platforms in upstream are J784S4-EVM[1], J722S-EVM[2], etc.
Hence enable building Texas Instruments DS90UB960 deserializer and
DS90UB953 serializer drivers as modules.
[1]: https://www.ti.com/lit/zip/sprr458
[2]: https://www.ti.com/lit/zip/sprr495
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
---
Changelog:
Changes in v2:
- Add reason in the commit message on why we want the DS90UB960 deserializer and DS90UB953
serializer drivers to be enabled in defconfig (Krzysztof)
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6f633d4dfc64..efe76f2bfe9b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -917,6 +917,8 @@ CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_AMPHION_VPU=m
CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_DS90UB960=m
+CONFIG_VIDEO_DS90UB953=m
CONFIG_VIDEO_WAVE_VPU=m
CONFIG_VIDEO_E5010_JPEG_ENC=m
CONFIG_VIDEO_MEDIATEK_JPEG=m
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread