From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw
Date: Fri, 28 Apr 2023 11:54:11 +0000 [thread overview]
Message-ID: <034b5a28dad5966423c82e5bb0bc1d77541eae3c.camel@intel.com> (raw)
In-Reply-To: <ZEuv1DAk5V7Ffswo@intel.com>
On Fri, 2023-04-28 at 14:36 +0300, Ville Syrjälä wrote:
> On Fri, Apr 28, 2023 at 11:19:39AM +0000, Hogander, Jouni wrote:
> > On Fri, 2023-04-21 at 15:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > All known issues fixed now, so re-enable PSR1 on hsw/bdw.
> >
> > Please note s/hdw/hsw/ in subject.
> >
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index 272a8ba37b64..923e24044967 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -562,6 +562,8 @@ static const struct intel_device_info
> > > vlv_info =
> > > {
> > > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> > > .display.has_ddi = 1, \
> > > .display.has_fpga_dbg = 1, \
> > > + .display.has_psr = 1, \
> > > + .display.has_psr_hw_tracking = 1, \
> >
> > Isn't this has_psr_hw_tracking about PSR2 with hw tracking
> > mechanism in
> > e.g. ICL? See Bspec: 4289. More recent platforms have manual
> > tracking
> > mechanism. In TGL there were both.
>
> I have no idea what people meant by hw tracking in this context.
> psr_force_hw_tracking_exit() is the thing that does the
> CURSURFLIVE write to force PSR exit/etc. and that is used for
> PSR1 and PSR2. So someone should properly document what this is
> supposed to indicate, and rename either that function or this
> flag to refelct reality.
Ok, anyways this variable seems to be taken into account only in PSR2
context so this should not cause any problems either.
>
> >
> > > .display.has_dp_mst = 1, \
> > > .has_rc6p = 0 /* RC6p removed-by HSW */, \
> > > HSW_PIPE_OFFSETS, \
> > > @@ -665,8 +667,6 @@ static const struct intel_device_info
> > > chv_info =
> > > {
> > > .has_gt_uc = 1, \
> > > .__runtime.has_hdcp = 1, \
> > > .display.has_ipc = 1, \
> > > - .display.has_psr = 1, \
> > > - .display.has_psr_hw_tracking = 1, \
> > > .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path
> > > allocation */ \
> > > .display.dbuf.slice_mask = BIT(DBUF_S1)
> > >
> >
> > BR,
> >
> > Jouni Högander
>
next prev parent reply other threads:[~2023-04-28 11:54 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 12:02 [Intel-gfx] [PATCH 00/13] drm/i915/psr: Restore HSW/BDW PSR1 Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 01/13] drm/i915: Re-init clock gating on coming out of PC8+ Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 02/13] drm/i915/psr: Fix BDW PSR AUX CH data register offsets Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 03/13] drm/i915/psr: Wrap PSR1 register with functions Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 04/13] drm/i915/psr: Reintroduce HSW PSR1 registers Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 05/13] drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup Ville Syrjala
2023-04-28 10:18 ` Hogander, Jouni
2023-04-28 11:03 ` Ville Syrjälä
2023-04-28 11:31 ` Hogander, Jouni
2023-04-21 12:03 ` [Intel-gfx] [PATCH 06/13] drm/i915/psr: HSW/BDW have no PSR2 Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 07/13] drm/i915/psr: Restore PSR interrupt handler for HSW Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 08/13] drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw Ville Syrjala
2023-04-28 10:36 ` Hogander, Jouni
2023-04-28 10:55 ` Ville Syrjälä
2023-04-28 11:29 ` Hogander, Jouni
2023-04-21 12:03 ` [Intel-gfx] [PATCH 09/13] drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 10/13] drm/i915/psr: Do no mask display register writes on hsw/bdw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 11/13] drm/i915/psr: Don't skip both TP1 and TP2/3 " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 12/13] drm/i915/psr: Allow PSR with sprite enabled " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw Ville Syrjala
2023-04-28 11:19 ` Hogander, Jouni
2023-04-28 11:36 ` Ville Syrjälä
2023-04-28 11:54 ` Hogander, Jouni [this message]
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Restore HSW/BDW PSR1 Patchwork
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-21 14:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-21 23:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=034b5a28dad5966423c82e5bb0bc1d77541eae3c.camel@intel.com \
--to=jouni.hogander@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox