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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 08/13] drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw
Date: Fri, 28 Apr 2023 11:29:21 +0000	[thread overview]
Message-ID: <e25fd258879b5cf6b5d4d53e64ec5f0685a60d5d.camel@intel.com> (raw)
In-Reply-To: <ZEumCGCTAQnoRF8A@intel.com>

On Fri, 2023-04-28 at 13:55 +0300, Ville Syrjälä wrote:
> On Fri, Apr 28, 2023 at 10:36:17AM +0000, Hogander, Jouni wrote:
> > On Fri, 2023-04-21 at 15:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware
> > > generate the extra vblank between link training and first frame
> > > being transmitted. This is the same thing that's controlled by
> > > TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering
> > > it's effectively always at the rest value after DC5 exit). So
> > > for consistent behaviour we want every platform to generate said
> > > vblank. BDW is already setting this up correctly.
> > 
> > I couldn't find this from Bspec. I'll guess you have some offline
> > documentation? WaPsrDPRSUnmaskVBlankInSRD seems to be in Bspec.
> 
> Bspec has lost the human readable name at some point.
> It's still there though as w/a #0503.

Ok, found it now. Thank you for pointing it out.

> 
> > 
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_clock_gating.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
> > > b/drivers/gpu/drm/i915/intel_clock_gating.c
> > > index a27600bc5976..9682323510cd 100644
> > > --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> > > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> > > @@ -562,6 +562,9 @@ static void hsw_init_clock_gating(struct
> > > drm_i915_private *i915)
> > >         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> > >         intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A),
> > > 0,
> > > HSW_FBCQ_DIS);
> > >  
> > > +       /* WaPsrDPAMaskVBlankInSRD:hsw */
> > > +       intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0,
> > > HSW_MASK_VBL_TO_PIPE_IN_SRD);
> > > +
> > >         /* This is required by WaCatErrorRejectionIssue:hsw */
> > >         intel_uncore_rmw(&i915->uncore,
> > > GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> > >                          0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> > 
> > BR,
> > 
> > Jouni Högander
> 


  reply	other threads:[~2023-04-28 11:29 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-21 12:02 [Intel-gfx] [PATCH 00/13] drm/i915/psr: Restore HSW/BDW PSR1 Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 01/13] drm/i915: Re-init clock gating on coming out of PC8+ Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 02/13] drm/i915/psr: Fix BDW PSR AUX CH data register offsets Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 03/13] drm/i915/psr: Wrap PSR1 register with functions Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 04/13] drm/i915/psr: Reintroduce HSW PSR1 registers Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 05/13] drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup Ville Syrjala
2023-04-28 10:18   ` Hogander, Jouni
2023-04-28 11:03     ` Ville Syrjälä
2023-04-28 11:31       ` Hogander, Jouni
2023-04-21 12:03 ` [Intel-gfx] [PATCH 06/13] drm/i915/psr: HSW/BDW have no PSR2 Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 07/13] drm/i915/psr: Restore PSR interrupt handler for HSW Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 08/13] drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw Ville Syrjala
2023-04-28 10:36   ` Hogander, Jouni
2023-04-28 10:55     ` Ville Syrjälä
2023-04-28 11:29       ` Hogander, Jouni [this message]
2023-04-21 12:03 ` [Intel-gfx] [PATCH 09/13] drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 10/13] drm/i915/psr: Do no mask display register writes on hsw/bdw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 11/13] drm/i915/psr: Don't skip both TP1 and TP2/3 " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 12/13] drm/i915/psr: Allow PSR with sprite enabled " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw Ville Syrjala
2023-04-28 11:19   ` Hogander, Jouni
2023-04-28 11:36     ` Ville Syrjälä
2023-04-28 11:54       ` Hogander, Jouni
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Restore HSW/BDW PSR1 Patchwork
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-21 14:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-21 23:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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