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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/13] drm/i915/psr: Restore PSR interrupt handler for HSW
Date: Fri, 21 Apr 2023 15:03:01 +0300	[thread overview]
Message-ID: <20230421120307.24793-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the PSR interrupt handling code back for HSW. Looks like
the removal was never completed anyway since the irq setup
code was lest untouched.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b94b8ca8ec9..e1c57ba4f80a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1781,6 +1781,20 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
 	if (de_iir & DE_ERR_INT_IVB)
 		ivb_err_int_handler(dev_priv);
 
+	if (de_iir & DE_EDP_PSR_INT_HSW) {
+		struct intel_encoder *encoder;
+
+		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+			u32 psr_iir;
+
+			psr_iir = intel_uncore_rmw(&dev_priv->uncore,
+						   EDP_PSR_IIR, 0, 0);
+			intel_psr_irq_handler(intel_dp, psr_iir);
+			break;
+		}
+	}
+
 	if (de_iir & DE_AUX_CHANNEL_A_IVB)
 		dp_aux_irq_handler(dev_priv);
 
-- 
2.39.2


  parent reply	other threads:[~2023-04-21 12:03 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-21 12:02 [Intel-gfx] [PATCH 00/13] drm/i915/psr: Restore HSW/BDW PSR1 Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 01/13] drm/i915: Re-init clock gating on coming out of PC8+ Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 02/13] drm/i915/psr: Fix BDW PSR AUX CH data register offsets Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 03/13] drm/i915/psr: Wrap PSR1 register with functions Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 04/13] drm/i915/psr: Reintroduce HSW PSR1 registers Ville Syrjala
2023-04-21 12:02 ` [Intel-gfx] [PATCH 05/13] drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup Ville Syrjala
2023-04-28 10:18   ` Hogander, Jouni
2023-04-28 11:03     ` Ville Syrjälä
2023-04-28 11:31       ` Hogander, Jouni
2023-04-21 12:03 ` [Intel-gfx] [PATCH 06/13] drm/i915/psr: HSW/BDW have no PSR2 Ville Syrjala
2023-04-21 12:03 ` Ville Syrjala [this message]
2023-04-21 12:03 ` [Intel-gfx] [PATCH 08/13] drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw Ville Syrjala
2023-04-28 10:36   ` Hogander, Jouni
2023-04-28 10:55     ` Ville Syrjälä
2023-04-28 11:29       ` Hogander, Jouni
2023-04-21 12:03 ` [Intel-gfx] [PATCH 09/13] drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 10/13] drm/i915/psr: Do no mask display register writes on hsw/bdw Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 11/13] drm/i915/psr: Don't skip both TP1 and TP2/3 " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 12/13] drm/i915/psr: Allow PSR with sprite enabled " Ville Syrjala
2023-04-21 12:03 ` [Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw Ville Syrjala
2023-04-28 11:19   ` Hogander, Jouni
2023-04-28 11:36     ` Ville Syrjälä
2023-04-28 11:54       ` Hogander, Jouni
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Restore HSW/BDW PSR1 Patchwork
2023-04-21 14:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-21 14:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-21 23:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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