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* [Intel-gfx] [PATCH 0/2] MTL Degamma implementation
@ 2023-07-25  8:30 Chaitanya Kumar Borah
  2023-07-25  8:30 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/color: Upscale degamma values for MTL Chaitanya Kumar Borah
                   ` (9 more replies)
  0 siblings, 10 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-07-25  8:30 UTC (permalink / raw)
  To: intel-gfx

MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to continue supporting degamma on MTL.

To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.

Chaitanya Kumar Borah (2):
  drm/i915/color: Upscale degamma values for MTL
  drm/i915/color: Downscale degamma lut values read from hardware

 drivers/gpu/drm/i915/display/intel_color.c | 28 +++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/2] MTL Degamma implementation
@ 2023-07-10 13:43 Chaitanya Kumar Borah
  0 siblings, 0 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-07-10 13:43 UTC (permalink / raw)
  To: intel-gfx

MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to continue supporting degamma on MTL.

To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.

Chaitanya Kumar Borah (2):
  drm/i915/color: Upscale degamma values for MTL
  drm/i915/color: Downscale degamma lut values read from hardware

 drivers/gpu/drm/i915/display/intel_color.c | 27 +++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/2] MTL Degamma implementation
@ 2023-06-26  5:54 Chaitanya Kumar Borah
  0 siblings, 0 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-06-26  5:54 UTC (permalink / raw)
  To: intel-gfx

MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to continue supporting degamma on MTL.

To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.

Chaitanya Kumar Borah (2):
  drm/i915/color: Add function to load degamma LUT in MTL
  drm/i915/color: For MTL convert 24 bit lut values to 16 bit

 drivers/gpu/drm/i915/display/intel_color.c | 50 +++++++++++++++++++++-
 1 file changed, 48 insertions(+), 2 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2023-07-27 22:15 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-25  8:30 [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Chaitanya Kumar Borah
2023-07-25  8:30 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/color: Upscale degamma values for MTL Chaitanya Kumar Borah
2023-07-27 12:00   ` Nautiyal, Ankit K
2023-07-27 12:33   ` [Intel-gfx] [PATCH v4 " Chaitanya Kumar Borah
2023-07-25  8:30 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/color: Downscale degamma lut values read from hardware Chaitanya Kumar Borah
2023-07-25  9:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for MTL Degamma implementation (rev3) Patchwork
2023-07-25 15:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-26  6:16 ` Patchwork
2023-07-26  6:31 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2023-07-27 11:57 ` [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Nautiyal, Ankit K
2023-07-27 13:06   ` Nautiyal, Ankit K
2023-07-27 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MTL Degamma implementation (rev4) Patchwork
2023-07-27 18:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-27 22:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-07-10 13:43 [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Chaitanya Kumar Borah
2023-06-26  5:54 Chaitanya Kumar Borah

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