Re: [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite plane SURFLIVE registers

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Might as well complete the SURFLIVE register definitions
> for all platforms/plane types. We are only missing the
> VLV/CHV sprite planes.

Can you please point out Bspec you used for these definitions?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index a2b4af711e6d..e908959dba4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4394,6 +4394,7 @@
>  #define   SP_CONST_ALPHA_ENABLE                REG_BIT(31)
>  #define   SP_CONST_ALPHA_MASK          REG_GENMASK(7, 0)
>  #define  
> SP_CONST_ALPHA(alpha)                REG_FIELD_PREP(SP_CONST_ALPHA_MA
> SK, (alpha))
> +#define _SPASURFLIVE           (VLV_DISPLAY_BASE + 0x721ac)
>  #define _SPACLRC0              (VLV_DISPLAY_BASE + 0x721d0)
>  #define   SP_CONTRAST_MASK             REG_GENMASK(26, 18)
>  #define  
> SP_CONTRAST(x)               REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /*
> u3.6 */
> @@ -4417,6 +4418,7 @@
>  #define _SPBKEYMAXVAL          (VLV_DISPLAY_BASE + 0x722a0)
>  #define _SPBTILEOFF            (VLV_DISPLAY_BASE + 0x722a4)
>  #define _SPBCONSTALPHA         (VLV_DISPLAY_BASE + 0x722a8)
> +#define _SPBSURFLIVE           (VLV_DISPLAY_BASE + 0x722ac)
>  #define _SPBCLRC0              (VLV_DISPLAY_BASE + 0x722d0)
>  #define _SPBCLRC1              (VLV_DISPLAY_BASE + 0x722d4)
>  #define _SPBGAMC               (VLV_DISPLAY_BASE + 0x722e0)
> @@ -4437,6 +4439,7 @@
>  #define SPKEYMAXVAL(pipe, plane_id)    _MMIO_VLV_SPR((pipe),
> (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
>  #define SPTILEOFF(pipe, plane_id)      _MMIO_VLV_SPR((pipe),
> (plane_id), _SPATILEOFF, _SPBTILEOFF)
>  #define SPCONSTALPHA(pipe, plane_id)   _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPSURFLIVE(pipe, plane_id)     _MMIO_VLV_SPR((pipe),
> (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
>  #define SPCLRC0(pipe, plane_id)                _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACLRC0, _SPBCLRC0)
>  #define SPCLRC1(pipe, plane_id)                _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACLRC1, _SPBCLRC1)
>  #define SPGAMC(pipe, plane_id, i)      _MMIO(_VLV_SPR((pipe),
> (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */

BR,

Jouni Högander