From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite plane SURFLIVE registers
Date: Tue, 14 Mar 2023 15:02:52 +0200 [thread overview]
Message-ID: <20230314130255.23273-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230314130255.23273-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Might as well complete the SURFLIVE register definitions
for all platforms/plane types. We are only missing the
VLV/CHV sprite planes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2b4af711e6d..e908959dba4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4394,6 +4394,7 @@
#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
+#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
@@ -4417,6 +4418,7 @@
#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
@@ -4437,6 +4439,7 @@
#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
--
2.39.2
next prev parent reply other threads:[~2023-03-14 13:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC* Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/ Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
2023-03-16 8:43 ` Hogander, Jouni
2023-03-16 9:44 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
2023-03-16 8:55 ` Hogander, Jouni
2023-03-16 9:40 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers Ville Syrjala
2023-03-14 13:02 ` Ville Syrjala [this message]
2023-03-16 9:12 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Hogander, Jouni
2023-03-16 9:41 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates() Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c Ville Syrjala
2023-03-14 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers Patchwork
2023-03-14 17:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-15 20:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-17 11:12 ` [Intel-gfx] [PATCH 0/9] " Hogander, Jouni
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