From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
Date: Tue, 14 Mar 2023 15:02:47 +0200 [thread overview]
Message-ID: <20230314130255.23273-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230314130255.23273-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The PIPE_MISC registers don't exist on pre-bdw hardware,
so there is no point in using pipe_offsets[] for them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9db6b3f06a74..aff3f4365b97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3519,14 +3519,14 @@
#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
-#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+#define PIPEMISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
#define _PIPE_MISC2_A 0x7002C
#define _PIPE_MISC2_B 0x7102C
#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
-#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
+#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A 0x70034
--
2.39.2
next prev parent reply other threads:[~2023-03-14 13:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
2023-03-14 13:02 ` Ville Syrjala [this message]
2023-03-14 13:02 ` [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/ Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
2023-03-16 8:43 ` Hogander, Jouni
2023-03-16 9:44 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
2023-03-16 8:55 ` Hogander, Jouni
2023-03-16 9:40 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Ville Syrjala
2023-03-16 9:12 ` Hogander, Jouni
2023-03-16 9:41 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates() Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c Ville Syrjala
2023-03-14 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers Patchwork
2023-03-14 17:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-15 20:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-17 11:12 ` [Intel-gfx] [PATCH 0/9] " Hogander, Jouni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230314130255.23273-2-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox