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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 06/26] drm/i915: interrupt bit definitions for VLV
Date: Thu, 22 Mar 2012 14:38:48 -0700	[thread overview]
Message-ID: <1332452348-8814-7-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1332452348-8814-1-git-send-email-jbarnes@virtuousgeek.org>

---
 drivers/gpu/drm/i915/i915_reg.h |   41 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 869c695..1af17e0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2435,23 +2435,30 @@
 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
 #define _PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
+#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
+#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<26)
 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
+#define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
@@ -2476,6 +2483,40 @@
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
+#define DPFLIPSTAT_VLV				0x70028
+#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
+#define   PIPEB_HLINE_INT_EN			(1<<28)
+#define   PIPEB_VBLANK_INT_EN			(1<<27)
+#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
+#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
+#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
+#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
+#define   PIPEA_HLINE_INT_EN			(1<<20)
+#define   PIPEA_VBLANK_INT_EN			(1<<19)
+#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
+#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
+#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
+
+#define DPINVGTT				0x7002c /* VLV only */
+#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
+#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
+#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
+#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
+#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
+#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
+#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
+#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
+#define   DPINVGTT_EN_MASK			0xff0000
+#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
+#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
+#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
+#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
+#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
+#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
+#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
+#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
+#define   DPINVGTT_STATUS_MASK			0xff
+
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
-- 
1.7.5.4

  parent reply	other threads:[~2012-03-22 21:39 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-22 21:38 [RFCv2] ValleyView support Jesse Barnes
2012-03-22 21:38 ` [PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c Jesse Barnes
2012-03-22 22:20   ` Ben Widawsky
2012-03-23 22:46     ` Daniel Vetter
2012-03-22 21:38 ` [PATCH 02/26] drm/i915: re-order GT IIR bit definitions Jesse Barnes
2012-03-22 22:25   ` Ben Widawsky
2012-03-23 22:46     ` Daniel Vetter
2012-03-22 21:38 ` [PATCH 03/26] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro Jesse Barnes
2012-03-22 22:31   ` Ben Widawsky
2012-03-22 21:38 ` [PATCH 04/26] drm/i915: ValleyView watermark support Jesse Barnes
2012-03-23  3:29   ` Ben Widawsky
2012-03-23  9:51     ` Daniel Vetter
2012-03-24  2:46       ` Ben Widawsky
2012-03-22 21:38 ` [PATCH 05/26] drm/i915: PLL defines for VLV Jesse Barnes
2012-03-23  3:35   ` Ben Widawsky
2012-03-22 21:38 ` Jesse Barnes [this message]
2012-03-22 21:38 ` [PATCH 07/26] drm/i915: add ValleyView clock gating init Jesse Barnes
2012-03-22 23:25   ` Ben Widawsky
2012-03-22 21:38 ` [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView Jesse Barnes
2012-03-23  4:03   ` Ben Widawsky
2012-03-23 17:29   ` Eugeni Dodonov
2012-03-22 21:38 ` [PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set Jesse Barnes
2012-03-23  4:16   ` Ben Widawsky
2012-03-23 23:00   ` Daniel Vetter
2012-03-22 21:38 ` [PATCH 10/26] drm/i915: split LVDS " Jesse Barnes
2012-03-23 23:04   ` Daniel Vetter
2012-03-22 21:38 ` [PATCH 11/26] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-03-22 21:38 ` [PATCH 12/26] drm/i915: program drain latency regs on ValleyView Jesse Barnes
2012-03-26  1:50   ` Ben Widawsky
2012-03-22 21:38 ` [PATCH 13/26] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-03-22 21:38 ` [PATCH 14/26] drm/i915: Enable HDMI on ValleyView Jesse Barnes
2012-03-22 21:38 ` [PATCH 15/26] agp/intel: map more registers for use by the GTT code Jesse Barnes
2012-03-26  2:05   ` Ben Widawsky
2012-03-26  7:06     ` Daniel Vetter
2012-03-22 21:38 ` [PATCH 16/26] agp/intel: add ValleyView AGP driver Jesse Barnes
2012-03-26  2:16   ` Ben Widawsky
2012-03-26  7:08     ` Daniel Vetter
2012-03-26 18:17       ` Ben Widawsky
2012-03-22 21:38 ` [PATCH 17/26] agp/intel: bind " Jesse Barnes
2012-03-22 21:39 ` [PATCH 18/26] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-03-23 17:11   ` Eugeni Dodonov
2012-03-22 21:39 ` [PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions Jesse Barnes
2012-03-23 17:20   ` Eugeni Dodonov
2012-03-26 18:20     ` Ben Widawsky
2012-03-22 21:39 ` [PATCH 20/26] drm/i915: ValleyView has limited cacheability Jesse Barnes
2012-03-22 23:31   ` Jesse Barnes
2012-03-26 18:34   ` Ben Widawsky
2012-03-26 18:49     ` Daniel Vetter
2012-03-28 17:43       ` Jesse Barnes
2012-03-22 21:39 ` [PATCH 21/26] drm/i915: ValleyView IRQ support Jesse Barnes
2012-03-22 21:39 ` [PATCH 22/26] drm/i915: display regs are at 0x180000 on ValleyView Jesse Barnes
2012-03-22 21:39 ` [PATCH 23/26] drm/i915: check for disabled interrupts " Jesse Barnes
2012-03-22 21:39 ` [PATCH 24/26] drm/i915: add HDMI and DP port enumeration " Jesse Barnes
2012-03-22 21:39 ` [PATCH 25/26] drm/i915: disable turbo on ValleyView for now Jesse Barnes
2012-03-23 17:04   ` Eugeni Dodonov
2012-03-22 21:39 ` [PATCH 26/26] drm/i915: bind driver to ValleyView chipsets Jesse Barnes

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