Re: [PATCH 15/26] agp/intel: map more registers for use by the GTT code

[Daniel Vetter <daniel@ffwll.ch>]

On Sun, Mar 25, 2012 at 07:05:40PM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:38:57PM -0700, Jesse Barnes wrote:
> > We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
> > register for doing so is above the range we normally map.  Map the whole
> > register space to make sure we can get it.
> > 
> > v2: only map the larger space on gen7+ (Daniel)
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/char/agp/intel-gtt.c |    6 +++++-
> >  1 files changed, 5 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> > index 5cf47ac..269cb02 100644
> > --- a/drivers/char/agp/intel-gtt.c
> > +++ b/drivers/char/agp/intel-gtt.c
> > @@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
> >  static int i9xx_setup(void)
> >  {
> >  	u32 reg_addr;
> > +	int size = KB(512);
> >  
> >  	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
> >  
> >  	reg_addr &= 0xfff80000;
> >  
> > -	intel_private.registers = ioremap(reg_addr, 128 * 4096);
> > +	if (INTEL_GTT_GEN >= 7)
> > +		size = MB(2);
> > +
> > +	intel_private.registers = ioremap(reg_addr, size);
> >  	if (!intel_private.registers)
> >  		return -ENOMEM;
> >  
> 
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Does this need to go in -fixes since it seems like a "fix" for IVB?

Afaics no, because only on vlv we need to frob one of thes high-up
registers in intel-gtt. In drm/i915 we already map the entire mmio space
(by checking the bar size, iirc).

> Also, just looking at the code, is offset still correct? Gen5, and Gen6
> have 2MB, Gen4, and default have 512kb.

Same reason as why this is not a fix, we don't need more. Imo the right
thing to do is to reap intel-gtt support for gen6+ and move it completely
into drm/i915. This won't break any used abi because we never supported
ums on these in upstream.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48