From: Eugeni Dodonov <eugeni.dodonov@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: [PATCH 12/21] drm/i915: support Haswell-style force waking
Date: Thu, 28 Jun 2012 15:55:40 -0300 [thread overview]
Message-ID: <1340909749-15249-13-git-send-email-eugeni.dodonov@intel.com> (raw)
In-Reply-To: <1340909749-15249-1-git-send-email-eugeni.dodonov@intel.com>
On Haswell, there is a different register for reading force wake ACKs, and
all the writes should go into the multi-threaded register, even for the
legacy force wake.
Also, we have a theorical possibility for the force wake sequence to
awaken the GT, but return while it hasn't finished bringing up the queue.
So we properly check those bits as well, to ensure we won't end up in
half-woken situation.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 36 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
4 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 79be879..73fd38a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -536,6 +536,39 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
return ret;
}
+static inline void __hsw_wait_gt_awake(struct drm_i915_private *dev_priv)
+{
+ int count = 0;
+
+ while (count++ < 50) {
+ u32 tmp = I915_READ_NOTRACE(FORCEWAKE_ACK_HSW);
+ if ((tmp & 1) && !(tmp & _MASKED_BIT_ENABLE(~7)))
+ break;
+ udelay(10);
+ }
+}
+
+
+void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv)
+{
+ __hsw_wait_gt_awake(dev_priv);
+
+ I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
+ POSTING_READ(FORCEWAKE_MT);
+
+ __hsw_wait_gt_awake(dev_priv);
+}
+
+void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
+
+ __hsw_wait_gt_awake(dev_priv);
+
+ /* The below doubles as a POSTING_READ */
+ gen6_gt_check_fifodbg(dev_priv);
+}
+
void vlv_force_wake_get(struct drm_i915_private *dev_priv)
{
int count;
@@ -1161,7 +1194,8 @@ MODULE_LICENSE("GPL and additional rights");
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((HAS_FORCE_WAKE((dev_priv)->dev)) && \
((reg) < 0x40000) && \
- ((reg) != FORCEWAKE))
+ ((reg) != FORCEWAKE) && \
+ ((reg) != FORCEWAKE_MT))
static bool IS_DISPLAYREG(u32 reg)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0c15ab..e4916a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1525,6 +1525,9 @@ extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
+extern void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv);
+extern void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv);
+
/* overlay */
#ifdef CONFIG_DEBUG_FS
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 284965b..2c4be2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4070,6 +4070,7 @@
#define FORCEWAKE 0xA18C
#define FORCEWAKE_VLV 0x1300b0
#define FORCEWAKE_ACK_VLV 0x1300b4
+#define FORCEWAKE_ACK_HSW 0x130044
#define FORCEWAKE_ACK 0x130090
#define FORCEWAKE_MT 0xa188 /* multi-threaded */
#define FORCEWAKE_MT_ACK 0x130040
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99bc1f3..0334e42 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3769,7 +3769,7 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
/* IVB configs may use multi-threaded forcewake */
- if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+ if (IS_IVYBRIDGE(dev)) {
u32 ecobus;
/* A small trick here - if the bios hasn't configured MT forcewake,
@@ -3842,6 +3842,8 @@ void intel_init_pm(struct drm_device *dev)
}
dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
dev_priv->display.sanitize_pm = gen6_sanitize_pm;
+ dev_priv->display.force_wake_get = hsw_gt_force_wake_get;
+ dev_priv->display.force_wake_put = hsw_gt_force_wake_put;
} else
dev_priv->display.update_wm = NULL;
} else if (IS_VALLEYVIEW(dev)) {
--
1.7.11.1
next prev parent reply other threads:[~2012-06-28 18:54 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-28 18:55 [PATCH 00/21] More Haswell patches Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 01/21] drm/i915: Move DP structs to shared location Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 02/21] drm/i915: Add support for DDI control DP outputs Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 03/21] drm/i915: Add DP Helper functions for Haswell Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 04/21] drm/i915: Haswell specific code for the DP Link Training Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 06/21] drm/i915: Hook DP init in ddi module Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume Eugeni Dodonov
2012-07-04 20:07 ` Paulo Zanoni
2012-07-04 20:35 ` Daniel Vetter
2012-07-04 23:13 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 08/21] drm/i915: simplify FDI RX check for LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 09/21] drm/i915: account for only one transcoder on LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch Eugeni Dodonov
2012-07-04 18:21 ` Paulo Zanoni
2012-07-06 20:47 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays Eugeni Dodonov
2012-07-04 21:15 ` Paulo Zanoni
2012-07-04 23:15 ` [PATCH 10/31] " Eugeni Dodonov
2012-07-05 12:58 ` Paulo Zanoni
2012-07-05 13:12 ` Daniel Vetter
2012-06-28 18:55 ` Eugeni Dodonov [this message]
2012-06-28 19:38 ` [PATCH 12/21] drm/i915: support Haswell-style force waking Daniel Vetter
2012-06-28 20:06 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 13/21] drm/i915: add RPS configuration for Haswell Eugeni Dodonov
2012-06-29 9:56 ` Daniel Vetter
2012-06-29 13:49 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 14/21] drm/i915: Add EDP Registers " Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 15/21] drm/i915: Timing initialization for eDP on HSW Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 16/21] drm/i915: Modesetting for eDP on HSw Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 17/21] drm/i915: Hook eDP initialization on DDI A Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 18/21] drm/i915: introduce haswell_init_clock_gating Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications Eugeni Dodonov
2012-06-28 19:24 ` Daniel Vetter
2012-06-28 20:11 ` Eugeni Dodonov
2012-07-04 17:41 ` Paulo Zanoni
2012-07-04 23:19 ` Eugeni Dodonov
2012-07-05 7:47 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition Eugeni Dodonov
2012-06-28 19:39 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell Eugeni Dodonov
2012-06-28 19:23 ` Daniel Vetter
2012-06-28 20:10 ` Eugeni Dodonov
2012-06-28 19:22 ` [PATCH 00/21] More Haswell patches Paulo Zanoni
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