From: Eugeni Dodonov <eugeni.dodonov@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: [PATCH 15/21] drm/i915: Timing initialization for eDP on HSW
Date: Thu, 28 Jun 2012 15:55:43 -0300 [thread overview]
Message-ID: <1340909749-15249-16-git-send-email-eugeni.dodonov@intel.com> (raw)
In-Reply-To: <1340909749-15249-1-git-send-email-eugeni.dodonov@intel.com>
From: Shobhit Kumar <shobhit.kumar@intel.com>
v2: simplify horizontal and vertical timings calculations
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++-------------
1 file changed, 42 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a695ab..0438a10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4669,6 +4669,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
unsigned int pipe_bpp;
bool dither;
bool is_cpu_edp = false, is_pch_edp = false;
+ u32 htotal, hblank, hsync, vtotal, vblank, vsync;
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
if (encoder->base.crtc != crtc)
@@ -4949,7 +4950,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
pipeconf |= PIPECONF_DITHER_EN;
pipeconf |= PIPECONF_DITHER_TYPE_SP;
}
- if (is_dp && !is_cpu_edp) {
+ if ((IS_HASWELL(dev) && is_cpu_edp) || (is_dp && !is_cpu_edp)) {
intel_dp_set_m_n(crtc, mode, adjusted_mode);
} else {
/* For non-DP output, clear any trans DP clock recovery setting.*/
@@ -4998,25 +4999,40 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(VSYNCSHIFT(pipe), 0);
}
- I915_WRITE(HTOTAL(pipe),
- (adjusted_mode->crtc_hdisplay - 1) |
- ((adjusted_mode->crtc_htotal - 1) << 16));
- I915_WRITE(HBLANK(pipe),
- (adjusted_mode->crtc_hblank_start - 1) |
- ((adjusted_mode->crtc_hblank_end - 1) << 16));
- I915_WRITE(HSYNC(pipe),
- (adjusted_mode->crtc_hsync_start - 1) |
- ((adjusted_mode->crtc_hsync_end - 1) << 16));
-
- I915_WRITE(VTOTAL(pipe),
- (adjusted_mode->crtc_vdisplay - 1) |
- ((adjusted_mode->crtc_vtotal - 1) << 16));
- I915_WRITE(VBLANK(pipe),
- (adjusted_mode->crtc_vblank_start - 1) |
- ((adjusted_mode->crtc_vblank_end - 1) << 16));
- I915_WRITE(VSYNC(pipe),
- (adjusted_mode->crtc_vsync_start - 1) |
- ((adjusted_mode->crtc_vsync_end - 1) << 16));
+ if (is_cpu_edp && IS_HASWELL(dev)) {
+ htotal = HTOTAL_EDP;
+ hblank = HBLANK_EDP;
+ hsync = HSYNC_EDP;
+ vtotal = VTOTAL_EDP;
+ vblank = VBLANK_EDP;
+ vsync = VSYNC_EDP;
+ } else {
+ htotal = HTOTAL(pipe);
+ hblank = HBLANK(pipe);
+ hsync = HSYNC(pipe);
+ vtotal = VTOTAL(pipe);
+ vblank = VBLANK(pipe);
+ vsync = VSYNC(pipe);
+ }
+ I915_WRITE(htotal,
+ (adjusted_mode->crtc_hdisplay - 1) |
+ ((adjusted_mode->crtc_htotal - 1) << 16));
+ I915_WRITE(hblank,
+ (adjusted_mode->crtc_hblank_start - 1) |
+ ((adjusted_mode->crtc_hblank_end - 1) << 16));
+ I915_WRITE(hsync,
+ (adjusted_mode->crtc_hsync_start - 1) |
+ ((adjusted_mode->crtc_hsync_end - 1) << 16));
+
+ I915_WRITE(vtotal,
+ (adjusted_mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ I915_WRITE(vblank,
+ (adjusted_mode->crtc_vblank_start - 1) |
+ ((adjusted_mode->crtc_vblank_end - 1) << 16));
+ I915_WRITE(vsync,
+ (adjusted_mode->crtc_vsync_start - 1) |
+ ((adjusted_mode->crtc_vsync_end - 1) << 16));
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
@@ -5024,10 +5040,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(PIPESRC(pipe),
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ if (!is_cpu_edp) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ }
if (is_cpu_edp)
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
--
1.7.11.1
next prev parent reply other threads:[~2012-06-28 18:54 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-28 18:55 [PATCH 00/21] More Haswell patches Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 01/21] drm/i915: Move DP structs to shared location Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 02/21] drm/i915: Add support for DDI control DP outputs Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 03/21] drm/i915: Add DP Helper functions for Haswell Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 04/21] drm/i915: Haswell specific code for the DP Link Training Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 06/21] drm/i915: Hook DP init in ddi module Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume Eugeni Dodonov
2012-07-04 20:07 ` Paulo Zanoni
2012-07-04 20:35 ` Daniel Vetter
2012-07-04 23:13 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 08/21] drm/i915: simplify FDI RX check for LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 09/21] drm/i915: account for only one transcoder on LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch Eugeni Dodonov
2012-07-04 18:21 ` Paulo Zanoni
2012-07-06 20:47 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays Eugeni Dodonov
2012-07-04 21:15 ` Paulo Zanoni
2012-07-04 23:15 ` [PATCH 10/31] " Eugeni Dodonov
2012-07-05 12:58 ` Paulo Zanoni
2012-07-05 13:12 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 12/21] drm/i915: support Haswell-style force waking Eugeni Dodonov
2012-06-28 19:38 ` Daniel Vetter
2012-06-28 20:06 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 13/21] drm/i915: add RPS configuration for Haswell Eugeni Dodonov
2012-06-29 9:56 ` Daniel Vetter
2012-06-29 13:49 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 14/21] drm/i915: Add EDP Registers " Eugeni Dodonov
2012-06-28 18:55 ` Eugeni Dodonov [this message]
2012-06-28 18:55 ` [PATCH 16/21] drm/i915: Modesetting for eDP on HSw Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 17/21] drm/i915: Hook eDP initialization on DDI A Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 18/21] drm/i915: introduce haswell_init_clock_gating Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications Eugeni Dodonov
2012-06-28 19:24 ` Daniel Vetter
2012-06-28 20:11 ` Eugeni Dodonov
2012-07-04 17:41 ` Paulo Zanoni
2012-07-04 23:19 ` Eugeni Dodonov
2012-07-05 7:47 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition Eugeni Dodonov
2012-06-28 19:39 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell Eugeni Dodonov
2012-06-28 19:23 ` Daniel Vetter
2012-06-28 20:10 ` Eugeni Dodonov
2012-06-28 19:22 ` [PATCH 00/21] More Haswell patches Paulo Zanoni
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