From: Daniel Vetter <daniel@ffwll.ch>
To: Eugeni Dodonov <eugeni.dodonov@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell
Date: Thu, 28 Jun 2012 21:23:52 +0200 [thread overview]
Message-ID: <20120628192352.GE5596@phenom.ffwll.local> (raw)
In-Reply-To: <1340909749-15249-22-git-send-email-eugeni.dodonov@intel.com>
On Thu, Jun 28, 2012 at 03:55:49PM -0300, Eugeni Dodonov wrote:
> For Haswell, on some of the early hardware revisions, it is possible to
> run into issues when RC6 state is enabled and when pipes change state.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Given that this is a w/a that only applies for early silicon, please add a
comment that this should get nuked once production stuff ships.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 78b6ba4..fd55e91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4512,4 +4512,9 @@
> #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
> #define SFUSE_STRAP_DDID_DETECTED (1<<0)
>
> +#define WM_DBG 0x45280
> +#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
> +#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
> +#define WM_DBG_DISALLOW_SPRITE (1<<2)
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0ccdb96..cc8628c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3601,6 +3601,15 @@ static void haswell_init_clock_gating(struct drm_device *dev)
> /* WaDisable4x2SubspanOptimization */
> I915_WRITE(CACHE_MODE_1,
> _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> +
> + /* Work-around rc6 issue */
> + I915_WRITE(WM_DBG,
> + I915_READ(WM_DBG) |
> + WM_DBG_DISALLOW_MULTIPLE_LP |
> + WM_DBG_DISALLOW_SPRITE |
> + WM_DBG_DISALLOW_MAXFIFO
> + );
> +
> }
>
> static void ivybridge_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-06-28 19:23 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-28 18:55 [PATCH 00/21] More Haswell patches Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 01/21] drm/i915: Move DP structs to shared location Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 02/21] drm/i915: Add support for DDI control DP outputs Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 03/21] drm/i915: Add DP Helper functions for Haswell Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 04/21] drm/i915: Haswell specific code for the DP Link Training Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 06/21] drm/i915: Hook DP init in ddi module Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume Eugeni Dodonov
2012-07-04 20:07 ` Paulo Zanoni
2012-07-04 20:35 ` Daniel Vetter
2012-07-04 23:13 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 08/21] drm/i915: simplify FDI RX check for LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 09/21] drm/i915: account for only one transcoder on LPT Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch Eugeni Dodonov
2012-07-04 18:21 ` Paulo Zanoni
2012-07-06 20:47 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays Eugeni Dodonov
2012-07-04 21:15 ` Paulo Zanoni
2012-07-04 23:15 ` [PATCH 10/31] " Eugeni Dodonov
2012-07-05 12:58 ` Paulo Zanoni
2012-07-05 13:12 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 12/21] drm/i915: support Haswell-style force waking Eugeni Dodonov
2012-06-28 19:38 ` Daniel Vetter
2012-06-28 20:06 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 13/21] drm/i915: add RPS configuration for Haswell Eugeni Dodonov
2012-06-29 9:56 ` Daniel Vetter
2012-06-29 13:49 ` Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 14/21] drm/i915: Add EDP Registers " Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 15/21] drm/i915: Timing initialization for eDP on HSW Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 16/21] drm/i915: Modesetting for eDP on HSw Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 17/21] drm/i915: Hook eDP initialization on DDI A Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 18/21] drm/i915: introduce haswell_init_clock_gating Eugeni Dodonov
2012-06-28 18:55 ` [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications Eugeni Dodonov
2012-06-28 19:24 ` Daniel Vetter
2012-06-28 20:11 ` Eugeni Dodonov
2012-07-04 17:41 ` Paulo Zanoni
2012-07-04 23:19 ` Eugeni Dodonov
2012-07-05 7:47 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition Eugeni Dodonov
2012-06-28 19:39 ` Daniel Vetter
2012-06-28 18:55 ` [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell Eugeni Dodonov
2012-06-28 19:23 ` Daniel Vetter [this message]
2012-06-28 20:10 ` Eugeni Dodonov
2012-06-28 19:22 ` [PATCH 00/21] More Haswell patches Paulo Zanoni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20120628192352.GE5596@phenom.ffwll.local \
--to=daniel@ffwll.ch \
--cc=eugeni.dodonov@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox