[PATCH 13/15] drm/i915: add INTEL_IRQ_REG_INIT16

[Paulo Zanoni <przanoni@gmail.com>]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Same thing as INTEL_IRQ_REG_INIT, but on a separate patch.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a936c59..d32042d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -102,6 +102,14 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
 	} \
 } while (0)
 
+#define INTEL_IRQ_REG_INIT16(type, do_iir, ier_val, imr_val) do { \
+	if (do_iir) \
+		I915_WRITE16(type##IR, I915_READ16(type##IR)); \
+	I915_WRITE16(type##MR, (imr_val)); \
+	I915_WRITE16(type##ER, (ier_val)); \
+	POSTING_READ16(type##ER); \
+} while (0)
+
 #define INTEL_IRQ_REG_INIT(type, do_iir, ier_val, imr_val) do { \
 	WARN(I915_READ(type##IR) != 0, "Register 0x%x is not 0\n", type##IR); \
 	I915_WRITE(type##MR, (imr_val)); \
@@ -2327,6 +2335,10 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
 static int i8xx_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	uint32_t enable_mask = (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+				I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+				I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
+				I915_USER_INTERRUPT);
 
 	I915_WRITE16(EMR,
 		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2338,14 +2350,8 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
 		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
 		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
-	I915_WRITE16(IMR, dev_priv->irq_mask);
-
-	I915_WRITE16(IER,
-		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
-		     I915_USER_INTERRUPT);
-	POSTING_READ16(IER);
+
+	INTEL_IRQ_REG_INIT16(I, false, enable_mask, dev_priv->irq_mask);
 
 	return 0;
 }
-- 
1.8.1.2