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From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value
Date: Mon, 15 Jan 2018 03:18:17 +0000 (UTC)
Date: Sun, 21 Jan 2018 03:15:05 +0530	[thread overview]
Message-ID: <1516484713-5837-8-git-send-email-vidya.srinivas@intel.com> (raw)
In-Reply-To: <1516484713-5837-1-git-send-email-vidya.srinivas@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5800b5b..9ed507a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4514,6 +4514,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
+				const struct skl_wm_level *result_prev,
 				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4579,6 +4580,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		} else {
 			res_blocks++;
 		}
+
+		/*
+		 * Make sure result blocks for higher latency levels are atleast
+		 * as high as level below.
+		 * Assumption in DDB algorithm optimization for special cases.
+		 * Also covers Display WA #1125 for RC.
+		 */
+		if (result_prev->plane_res_b > res_blocks)
+			res_blocks = result_prev->plane_res_b;
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4637,6 +4647,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
 							  &wm->wm[level];
+		struct skl_wm_level *result_prev;
+
+		if (level)
+			result_prev = plane_num ? &wm->uv_wm[level - 1] :
+						  &wm->wm[level - 1];
+		else
+			result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4644,6 +4661,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
+					   result_prev,
 					   result);
 		if (ret)
 			return ret;
-- 
2.7.4

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  parent reply	other threads:[~2018-01-15  3:20 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
2018-01-20  0:39   ` kbuild test robot
2018-01-15  3:18 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-01-17 11:43   ` Mika Kahola
2018-01-15  3:18 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-01-15  3:18 ` [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-01-15  3:18 ` Vidya Srinivas [this message]
2018-01-15  3:18 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-01-15  3:18 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-01-15  3:18 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-01-15  3:18 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-01-18 14:21   ` Maarten Lankhorst
2018-01-18 14:49     ` Maarten Lankhorst
2018-01-29 11:41   ` Maarten Lankhorst
2018-01-30  4:53     ` Srinivas, Vidya
2018-01-29 17:17   ` Maarten Lankhorst
2018-01-30  4:05     ` Srinivas, Vidya
2018-01-30  6:16       ` Kumar, Mahesh
2018-01-30  9:50         ` Maarten Lankhorst
2018-01-15  3:49 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev5) Patchwork
2018-01-15  4:55 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-15  8:47 ` ✓ Fi.CI.BAT: " Patchwork
2018-01-15 10:39   ` Saarinen, Jani
2018-01-15  9:44 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-15 12:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas

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