Re: [PATCH 3/6] drm/i915/psr: Enable Y-coordinate support in source

["Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>]

On Thu, 2018-03-15 at 17:28 -0700, Rodrigo Vivi wrote:
> drm/i915/cnl:....
> 
> On Wed, Mar 14, 2018 at 03:36:14PM -0700, José Roberto de Souza wrote:
> > We are requiring that sink requires Y-coordinate but we are not
> > sending it in the main-link.
> 
> Also add on CNL here
> 
> > Even if hardware tracking isn't good enough it will not cause
> > any more issues enabling it.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> >  drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a15db41a208a..e9fc1722c0fb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4132,6 +4132,8 @@ enum {
> >  #define EDP_PSR2_CTL			_MMIO(0x6f900)
> >  #define   EDP_PSR2_ENABLE		(1<<31)
> >  #define   EDP_SU_TRACK_ENABLE		(1<<30)
> > +#define   EDP_Y_COORDINATE_VALID	(1<<26)
> > +#define   EDP_Y_COORDINATE_ENABLE	(1<<25)
> 
> probably good add CNL_ prefix on these bits...
> 
> >  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
> >  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> >  #define   EDP_PSR2_TP2_TIME_500		(0<<8)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 62d97d5576d1..c9da1390a727 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -416,8 +416,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> >  	/* FIXME: selective update is probably totally broken because it doesn't
> >  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
> >  	 * good enough. */
> > -	val |= EDP_PSR2_ENABLE |
> > -		EDP_SU_TRACK_ENABLE;
> > +	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > +	val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
> 
> if (INTEL_GEN(dev_priv) >= 10)
> 	val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
> 
> since those bits were reserved before CNL.
> 

How does this work on pre-CNL platforms without the enable bit?

> With those changes:
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> >  
> >  	if (drm_dp_dpcd_readb(&intel_dp->aux,
> >  				DP_SYNCHRONIZATION_LATENCY_IN_SINK,
> > -- 
> > 2.16.2
> > 
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