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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/19] drm/i915/execlists: Handle copying default context state for atomic reset
Date: Thu, 17 May 2018 11:37:37 +0100	[thread overview]
Message-ID: <161a0d99-f342-b7e7-0cb1-bc2b8a9eb8cf@linux.intel.com> (raw)
In-Reply-To: <20180517074055.14638-7-chris@chris-wilson.co.uk>


On 17/05/2018 08:40, Chris Wilson wrote:
> We want to be able to reset the GPU from inside a timer callback
> (hardirq context). One step requires us to copy the default context
> state over to the guilty context, which means we need to plan in advance
> to have that object accessible from within an atomic context. The atomic
> context prevents us from pinning the object or in peeking into the
> shmemfs backing store (all may sleep), so we choose to pin the
> default_state into memory when the engine becomes active. This
> compromise allows us to swap out the default state when idle, if
> required.
> 
> References: 5692251c254a ("drm/i915/lrc: Scrub the GPU state of the guilty hanging request")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/intel_engine_cs.c  | 15 +++++++++++++++
>   drivers/gpu/drm/i915/intel_lrc.c        | 15 ++++-----------
>   drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
>   3 files changed, 20 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 333318b340e1..b1a1ca0758ce 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1082,6 +1082,11 @@ void intel_engines_park(struct drm_i915_private *i915)
>   		if (engine->park)
>   			engine->park(engine);
>   
> +		if (engine->pinned_default_state) {
> +			i915_gem_object_unpin_map(engine->default_state);
> +			engine->pinned_default_state = NULL;
> +		}
> +
>   		i915_gem_batch_pool_fini(&engine->batch_pool);
>   		engine->execlists.no_priolist = false;
>   	}
> @@ -1099,6 +1104,16 @@ void intel_engines_unpark(struct drm_i915_private *i915)
>   	enum intel_engine_id id;
>   
>   	for_each_engine(engine, i915, id) {
> +		void *map;
> +
> +		/* Pin the default state for fast resets from atomic context. */
> +		map = NULL;
> +		if (engine->default_state)
> +			map = i915_gem_object_pin_map(engine->default_state,
> +						      I915_MAP_WB);
> +		if (!IS_ERR_OR_NULL(map))
> +			engine->pinned_default_state = map;
> +
>   		if (engine->unpark)
>   			engine->unpark(engine);
>   
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index f3470b95d64e..49283b3d3ebb 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1966,17 +1966,10 @@ static void execlists_reset(struct intel_engine_cs *engine,
>   	 * to recreate its own state.
>   	 */
>   	regs = request->hw_context->lrc_reg_state;
> -	if (engine->default_state) {
> -		void *defaults;
> -
> -		defaults = i915_gem_object_pin_map(engine->default_state,
> -						   I915_MAP_WB);
> -		if (!IS_ERR(defaults)) {
> -			memcpy(regs, /* skip restoring the vanilla PPHWSP */
> -			       defaults + LRC_STATE_PN * PAGE_SIZE,
> -			       engine->context_size - PAGE_SIZE);
> -			i915_gem_object_unpin_map(engine->default_state);
> -		}
> +	if (engine->pinned_default_state) {
> +		memcpy(regs, /* skip restoring the vanilla PPHWSP */
> +		       engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
> +		       engine->context_size - PAGE_SIZE);
>   	}
>   	execlists_init_reg_state(regs,
>   				 request->gem_context, engine, request->ring);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 20c4e13efc0d..acef385c4c80 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -342,6 +342,7 @@ struct intel_engine_cs {
>   	struct i915_timeline timeline;
>   
>   	struct drm_i915_gem_object *default_state;
> +	void *pinned_default_state;
>   
>   	atomic_t irq_count;
>   	unsigned long irq_posted;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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  reply	other threads:[~2018-05-17 10:37 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-17  7:40 [PATCH 01/19] drm/i915: Move request->ctx aside Chris Wilson
2018-05-17  7:40 ` [PATCH 02/19] drm/i915: Move fiddling with engine->last_retired_context Chris Wilson
2018-05-17  7:40 ` [PATCH 03/19] drm/i915: Store a pointer to intel_context in i915_request Chris Wilson
2018-05-17  7:40 ` [PATCH 04/19] drm/i915: Pull the context->pin_count dec into the common intel_context_unpin Chris Wilson
2018-05-17 10:20   ` Tvrtko Ursulin
2018-05-17 10:35     ` Chris Wilson
2018-05-17  7:40 ` [PATCH 05/19] drm/i915: Be irqsafe inside reset Chris Wilson
2018-05-17 10:27   ` Tvrtko Ursulin
2018-05-17 10:46     ` Chris Wilson
2018-05-17  7:40 ` [PATCH 06/19] drm/i915: Make intel_engine_dump irqsafe Chris Wilson
2018-05-17 10:28   ` Tvrtko Ursulin
2018-05-17  7:40 ` [PATCH 07/19] drm/i915/execlists: Handle copying default context state for atomic reset Chris Wilson
2018-05-17 10:37   ` Tvrtko Ursulin [this message]
2018-05-17  7:40 ` [PATCH 08/19] drm/i915: Allow init_breadcrumbs to be used from irq context Chris Wilson
2018-05-17 10:40   ` Tvrtko Ursulin
2018-05-17  7:40 ` [PATCH 09/19] drm/i915/execlists: HWACK checking superseded checking port[0].count Chris Wilson
2018-05-17 10:55   ` Tvrtko Ursulin
2018-05-17 17:03     ` Chris Wilson
2018-05-17  7:40 ` [PATCH 10/19] drm/i915: Remove USES_GUC_SUBMISSION() pointer chasing from gen8_cs_irq_handler Chris Wilson
2018-05-17 10:58   ` Tvrtko Ursulin
2018-05-17 11:24     ` Chris Wilson
2018-05-17 13:13       ` Tvrtko Ursulin
2018-05-17  7:40 ` [PATCH 11/19] drm/i915/execlists: Double check rpm wakeref Chris Wilson
2018-05-17 11:04   ` Tvrtko Ursulin
2018-05-17  7:40 ` [PATCH 12/19] drm/i915: After reset on sanitization, reset the engine backends Chris Wilson
2018-05-17  7:40 ` [PATCH 13/19] drm/i915/execlists: Reset the CSB head tracking on reset/sanitization Chris Wilson
2018-05-17  7:40 ` [PATCH 14/19] drm/i915/execlists: Pull submit after dequeue under timeline lock Chris Wilson
2018-05-17  7:40 ` [PATCH 15/19] drm/i915/execlists: Process one CSB interrupt at a time Chris Wilson
2018-05-17  7:40 ` [PATCH 16/19] drm/i915/execlists: Unify CSB access pointers Chris Wilson
2018-05-17  7:40 ` [PATCH 17/19] drm/i915/execlists: Process the CSB directly from inside the irq handler Chris Wilson
2018-05-17  7:40 ` [PATCH 18/19] drm/i915/execlists: Direct submission (avoid tasklet/ksoftirqd) Chris Wilson
2018-05-17 13:13   ` Tvrtko Ursulin
2018-05-17 17:07     ` Chris Wilson
2018-05-18  8:06       ` Tvrtko Ursulin
2018-05-18  8:18         ` Chris Wilson
2018-05-18 19:36         ` Chris Wilson
2018-05-18 21:21     ` Chris Wilson
2018-05-17  7:40 ` [PATCH 19/19] drm/i915: Combine gt irq ack/handlers Chris Wilson
2018-05-17  8:01 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/19] drm/i915: Move request->ctx aside Patchwork
2018-05-17  8:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-17  8:16 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-17 11:05 ` ✗ Fi.CI.IGT: failure " Patchwork

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