[PATCH] drm/i915: disable rc6 on Cantiga and Crestline

[PATCH] drm/i915: disable rc6 on Cantiga and Crestline

[Jesse Barnes]

The Ironlake code won't work on these old chips, so disable it to avoid
hanging older systems.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   15 ++++++---------
 1 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3f73690..3a488ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6702,12 +6702,7 @@ void intel_modeset_init(struct drm_device *dev)
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_enable_drps(dev);
 		intel_init_emon(dev);
-	}
-
-	if (IS_GEN6(dev))
-		gen6_enable_rps(dev_priv);
 
-	if ((IS_GEN4(dev) || IS_GEN5(dev)) && IS_MOBILE(dev)) {
 		dev_priv->renderctx = intel_alloc_context_page(dev);
 		if (!dev_priv->renderctx)
 			goto skip_rc6;
@@ -6720,6 +6715,9 @@ void intel_modeset_init(struct drm_device *dev)
 		ironlake_enable_rc6(dev);
 	}
 
+	if (IS_GEN6(dev))
+		gen6_enable_rps(dev_priv);
+
 skip_rc6:
 	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
 	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
@@ -6752,14 +6750,13 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	if (dev_priv->display.disable_fbc)
 		dev_priv->display.disable_fbc(dev);
 
-	if (IS_IRONLAKE_M(dev))
+	if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
+		ironlake_disable_rc6(dev);
+	}
 	if (IS_GEN6(dev))
 		gen6_disable_rps(dev);
 
-	if ((IS_GEN4(dev) || IS_GEN5(dev)) && IS_MOBILE(dev))
-		ironlake_disable_rc6(dev);
-
 	mutex_unlock(&dev->struct_mutex);
 
 	/* Disable the irq before mode object teardown, for the irq might
-- 
1.7.2.3

Re: [PATCH] drm/i915: disable rc6 on Cantiga and Crestline

[Chris Wilson]

On Fri, 24 Dec 2010 20:29:34 -0800, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> The Ironlake code won't work on these old chips, so disable it to avoid
> hanging older systems.

But AFAICS, pwrctxa is enabled for crestline/cantiga. Any info on whether
that's true?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: disable rc6 on Cantiga and Crestline

[Jesse Barnes]

Yeah, we should be able to get it working, but the MI_SET_CONTEXT is failing.  I tried removing the extended save/restore and suspend flush, but things still hung at load.  We probably need to init some DRPS state as well...



"Chris Wilson" <chris@chris-wilson.co.uk> wrote:

>On Fri, 24 Dec 2010 20:29:34 -0800, Jesse Barnes
><jbarnes@virtuousgeek.org> wrote:
>> The Ironlake code won't work on these old chips, so disable it to
>avoid
>> hanging older systems.
>
>But AFAICS, pwrctxa is enabled for crestline/cantiga. Any info on
>whether
>that's true?
>-Chris
>
>-- 
>Chris Wilson, Intel Open Source Technology Centre

--
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH] drm/i915: disable rc6 on Cantiga and Crestline

[Jesse Barnes]

On Sat, 25 Dec 2010 12:37:52 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Fri, 24 Dec 2010 20:29:34 -0800, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > The Ironlake code won't work on these old chips, so disable it to avoid
> > hanging older systems.
> 
> But AFAICS, pwrctxa is enabled for crestline/cantiga. Any info on whether
> that's true?

Looking at this some more, we don't have a way of checking whether
we're in RC6 on Cantiga.  All the regs appear to be programmed
correctly to allow it, but the bits indicating current RS state on
Ironlake are undefined on Cantiga (and read as 0 on my system).

Running the MI_SET_CONTEXT code on Cantiga results in a hang.  I don't
know why though, even after removing the MI_SUSPEND_FLUSH instructions
(which is only available on ILK+) and reducing the command count it
hangs at load.

Without getting that working and measuring the before/after power, I
don't think we can safely enable RC6 on anything before Ironlake.

-- 
Jesse Barnes, Intel Open Source Technology Center