[PATCH 1/3] drm/i915: fix lost FP_CB_TUNE setting for pch plls

[PATCH 1/3] drm/i915: fix lost FP_CB_TUNE setting for pch plls

[Daniel Vetter]

commit de13a2e3f88a4da8e85063b6de37096795079e41
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Thu Sep 20 18:36:05 2012 -0300

    drm/i915: extract compute_dpll from ironlake_crtc_mode_set

missed the subtle adjustment of the FP1 register. Fix this up by
passing a pointer around instead of the value.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b2c744..f623f97 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5374,7 +5374,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
 }
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
-				      intel_clock_t *clock, u32 fp)
+				      intel_clock_t *clock, u32 *fp)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct drm_device *dev = crtc->dev;
@@ -5414,7 +5414,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 		factor = 20;
 
 	if (clock->m < factor * clock->n)
-		fp |= FP_CB_TUNE;
+		*fp |= FP_CB_TUNE;
 
 	dpll = 0;
 
@@ -5531,7 +5531,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
 			reduced_clock.m2;
 
-	dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
+	dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp);
 
 	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
 	drm_mode_debug_printmodeline(mode);
-- 
1.7.10.4

[PATCH 2/3] drm/i915: fix FP CB tuning limits for lvds

[Daniel Vetter]

Only on IBX should we set the limiting factor to 25 unconditionally
for dual-channel mode, on CPT/PPT 25 only applies when the lvds
refclock is 100MHz.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f623f97..cb3e23f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5408,7 +5408,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	if (is_lvds) {
 		if ((intel_panel_use_ssc(dev_priv) &&
 		     dev_priv->lvds_ssc_freq == 100) ||
-		    intel_is_dual_link_lvds(dev))
+		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
 			factor = 25;
 	} else if (is_sdvo && is_tv)
 		factor = 20;
-- 
1.7.10.4

[PATCH 3/3] drm/i915: set CB tuning also for the reduce clock

[Daniel Vetter]

Since the ratio is different, we also need to pass in the parameters
for the reduced clock. Might or might not reduce flicker for the
auto-downclocking on lvds/eDP.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cb3e23f..c7c135c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5374,7 +5374,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
 }
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
-				      intel_clock_t *clock, u32 *fp)
+				      intel_clock_t *clock, u32 *fp,
+				      intel_clock_t *reduced_clock, u32 *fp2)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct drm_device *dev = crtc->dev;
@@ -5416,6 +5417,9 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	if (clock->m < factor * clock->n)
 		*fp |= FP_CB_TUNE;
 
+	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
+		*fp2 |= FP_CB_TUNE;
+
 	dpll = 0;
 
 	if (is_lvds)
@@ -5531,7 +5535,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
 			reduced_clock.m2;
 
-	dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp);
+	dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
+				     has_reduced_clock ? &fp2 : NULL);
 
 	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
 	drm_mode_debug_printmodeline(mode);
-- 
1.7.10.4

Re: [PATCH 1/3] drm/i915: fix lost FP_CB_TUNE setting for pch plls

[Paulo Zanoni]

Hi

2013/4/4 Daniel Vetter <daniel.vetter@ffwll.ch>:
> commit de13a2e3f88a4da8e85063b6de37096795079e41
> Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Date:   Thu Sep 20 18:36:05 2012 -0300
>
>     drm/i915: extract compute_dpll from ironlake_crtc_mode_set
>
> missed the subtle adjustment of the FP1 register. Fix this up by
> passing a pointer around instead of the value.

We could also move the whole chunk that sets "factor" and "FP_CB_TUNE"
back to ironlake_crtc_mode_set or even to a brand new
ironlake_calculate_fp(intel_crtc, clock, has_reduced_clock,
reduced_clock, &fp, &fp2). Maybe as a follow-up patch since this
version is way much easier for -stable.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1b2c744..f623f97 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5374,7 +5374,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
>  }
>
>  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> -                                     intel_clock_t *clock, u32 fp)
> +                                     intel_clock_t *clock, u32 *fp)
>  {
>         struct drm_crtc *crtc = &intel_crtc->base;
>         struct drm_device *dev = crtc->dev;
> @@ -5414,7 +5414,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>                 factor = 20;
>
>         if (clock->m < factor * clock->n)
> -               fp |= FP_CB_TUNE;
> +               *fp |= FP_CB_TUNE;
>
>         dpll = 0;
>
> @@ -5531,7 +5531,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
>                         reduced_clock.m2;
>
> -       dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
> +       dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp);
>
>         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
>         drm_mode_debug_printmodeline(mode);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Paulo Zanoni

Re: [PATCH 2/3] drm/i915: fix FP CB tuning limits for lvds

[Paulo Zanoni]

Hi

2013/4/4 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Only on IBX should we set the limiting factor to 25 unconditionally
> for dual-channel mode, on CPT/PPT 25 only applies when the lvds
> refclock is 100MHz.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f623f97..cb3e23f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5408,7 +5408,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>         if (is_lvds) {
>                 if ((intel_panel_use_ssc(dev_priv) &&
>                      dev_priv->lvds_ssc_freq == 100) ||
> -                   intel_is_dual_link_lvds(dev))
> +                   (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
>                         factor = 25;
>         } else if (is_sdvo && is_tv)
>                 factor = 20;
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Paulo Zanoni

Re: [PATCH 3/3] drm/i915: set CB tuning also for the reduce clock

[Paulo Zanoni]

Hi

2013/4/4 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Since the ratio is different, we also need to pass in the parameters
> for the reduced clock. Might or might not reduce flicker for the
> auto-downclocking on lvds/eDP.

After this patch, my suggestion to add ironlake_calculate_fp() gets
even stronger :)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cb3e23f..c7c135c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5374,7 +5374,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
>  }
>
>  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> -                                     intel_clock_t *clock, u32 *fp)
> +                                     intel_clock_t *clock, u32 *fp,
> +                                     intel_clock_t *reduced_clock, u32 *fp2)
>  {
>         struct drm_crtc *crtc = &intel_crtc->base;
>         struct drm_device *dev = crtc->dev;
> @@ -5416,6 +5417,9 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>         if (clock->m < factor * clock->n)
>                 *fp |= FP_CB_TUNE;
>
> +       if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
> +               *fp2 |= FP_CB_TUNE;
> +
>         dpll = 0;
>
>         if (is_lvds)
> @@ -5531,7 +5535,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
>                         reduced_clock.m2;
>
> -       dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp);
> +       dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
> +                                    has_reduced_clock ? &fp2 : NULL);
>
>         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
>         drm_mode_debug_printmodeline(mode);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Paulo Zanoni

Re: [PATCH 1/3] drm/i915: fix lost FP_CB_TUNE setting for pch plls

[Daniel Vetter]

On Fri, Apr 05, 2013 at 04:52:28PM -0300, Paulo Zanoni wrote:
> Hi
> 
> 2013/4/4 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > commit de13a2e3f88a4da8e85063b6de37096795079e41
> > Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Date:   Thu Sep 20 18:36:05 2012 -0300
> >
> >     drm/i915: extract compute_dpll from ironlake_crtc_mode_set
> >
> > missed the subtle adjustment of the FP1 register. Fix this up by
> > passing a pointer around instead of the value.
> 
> We could also move the whole chunk that sets "factor" and "FP_CB_TUNE"
> back to ironlake_crtc_mode_set or even to a brand new
> ironlake_calculate_fp(intel_crtc, clock, has_reduced_clock,
> reduced_clock, &fp, &fp2). Maybe as a follow-up patch since this
> version is way much easier for -stable.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

All patches merged, thanks for the review. I didn't add a cc: stable to
this one, since no one has reported a regression yet. We can easily
backport if that changes.

I agree with your refactor idea, but until all the clock handling has
settled a bit (due to the massive pipe config reorganisation) I think we
should hold and not waste too much time with beauty-ops ;-)

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch