Re: [PATCH 3/5] drm/i915: store eLLC size

From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 3/5] drm/i915: store eLLC size
Date: Tue, 16 Jul 2013 08:02:38 +0200	[thread overview]
Message-ID: <20130716060238.GG5784@phenom.ffwll.local> (raw)
In-Reply-To: <1372960927-1112-3-git-send-email-ben@bwidawsk.net>

On Thu, Jul 04, 2013 at 11:02:05AM -0700, Ben Widawsky wrote:
> The eLLC cannot be determined by PCIID because as far as we know, even
> machines supporting eLLC may not have it enabled, or fused off or
> whatever. It's possible this isn't actually true, and at that point we
> can switch to a DEV_INFO flag instead.
> 
> I've defined everything where the docs are clear, and left the rest as
> magic.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 +++
>  drivers/gpu/drm/i915/i915_gem.c | 9 ++++++++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fd0f589..c6de881 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1187,6 +1187,9 @@ typedef struct drm_i915_private {
>  	/* Old dri1 support infrastructure, beware the dragons ya fools entering
>  	 * here! */
>  	struct i915_dri1_state dri1;
> +
> +	/* Cannot be determined by PCIID. You must always read a register. */
> +	size_t ellc_size;

Thou shalt not put useful stuff next to the dri/ums dungeons! Really,
we've tried a bit to clean up the giant mess that is our driver private
structure, I expect people to look for more than 5 secs for a suitable
place for this ;-)

Fixed while applying.
-Daniel

>  } drm_i915_private_t;
>  
>  /* Iterate over initialised rings */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index edea2cb..2df993d 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4153,8 +4153,15 @@ i915_gem_init_hw(struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
>  		return -EIO;
>  
> -	if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1))
> +	if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) {
>  		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> +		/* The docs do not explain exactly how the calculation can be
> +		 * made. It is somewhat guessable, but for now, it's always
> +		 * 128MB.
> +		 */
> +		dev_priv->ellc_size = 128;
> +		DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
> +	}
>  
>  	if (HAS_PCH_NOP(dev)) {
>  		u32 temp = I915_READ(GEN7_MSG_CTL);
> -- 
> 1.8.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch