[PATCH] drm/i915: MI_PREDICATE_RESULT_2 is HSW only

[PATCH] drm/i915: MI_PREDICATE_RESULT_2 is HSW only

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The MI_PREDICATE_RESULT_2 register exits only on HSW. On other
platforms the same offset is either reserved, or contains some
other register. So write the register only on HSW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 40d9dcf..182c521 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4442,10 +4442,9 @@ i915_gem_init_hw(struct drm_device *dev)
 	if (dev_priv->ellc_size)
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
-	if (IS_HSW_GT3(dev))
-		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
-	else
-		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
+	if (IS_HASWELL(dev))
+		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
+			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	if (HAS_PCH_NOP(dev)) {
 		u32 temp = I915_READ(GEN7_MSG_CTL);
-- 
1.8.3.2

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Re: [PATCH] drm/i915: MI_PREDICATE_RESULT_2 is HSW only

[Chris Wilson]

On Fri, Nov 29, 2013 at 02:56:12PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The MI_PREDICATE_RESULT_2 register exits only on HSW. On other
> platforms the same offset is either reserved, or contains some
> other register. So write the register only on HSW.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Couldn't find a conflict, but we all agree that writing to registers
that do not exist is just a recipe for disaster.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: MI_PREDICATE_RESULT_2 is HSW only

[Daniel Vetter]

On Fri, Nov 29, 2013 at 01:48:44PM +0000, Chris Wilson wrote:
> On Fri, Nov 29, 2013 at 02:56:12PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The MI_PREDICATE_RESULT_2 register exits only on HSW. On other
> > platforms the same offset is either reserved, or contains some
> > other register. So write the register only on HSW.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Couldn't find a conflict, but we all agree that writing to registers
> that do not exist is just a recipe for disaster.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Oops, actually merged this one but then accidentally replied to the vmap
fix. Both are now in -fixes.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch