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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/6] drm/i915: Merge TARGET_POWER_ON and PANEL_POWER_ON flag definitions
Date: Tue, 9 Aug 2016 20:51:14 +0300	[thread overview]
Message-ID: <20160809175114.GE4329@intel.com> (raw)
In-Reply-To: <1470742452-5240-3-git-send-email-imre.deak@intel.com>

On Tue, Aug 09, 2016 at 02:34:08PM +0300, Imre Deak wrote:
> These two flags mean the same thing, so remove the duplication.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 1 -
>  drivers/gpu/drm/i915/intel_dp.c   | 6 +++---
>  drivers/gpu/drm/i915/intel_lvds.c | 4 ++--
>  3 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b65fe50..889508f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3707,7 +3707,6 @@ enum {
>  #define  PANEL_POWER_RESET		(1 << 1)
>  #define  PANEL_POWER_OFF		(0 << 0)
>  #define  PANEL_POWER_ON			(1 << 0)
> -#define  POWER_TARGET_ON		(1 << 0)
>  
>  #define _PP_ON_DELAYS			0x61208
>  #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a5cef91..4796ad7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1950,7 +1950,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
>  	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
>  	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  
> -	if ((pp & POWER_TARGET_ON) == 0)
> +	if ((pp & PANEL_POWER_ON) == 0)
>  		intel_dp->panel_power_off_time = ktime_get_boottime();
>  
>  	power_domain = intel_display_port_aux_power_domain(intel_encoder);
> @@ -2037,7 +2037,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  		POSTING_READ(pp_ctrl_reg);
>  	}
>  
> -	pp |= POWER_TARGET_ON;
> +	pp |= PANEL_POWER_ON;
>  	if (!IS_GEN5(dev))
>  		pp |= PANEL_POWER_RESET;
>  
> @@ -2089,7 +2089,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
>  	pp = ironlake_get_pp_control(intel_dp);
>  	/* We need to switch off panel power _and_ force vdd, for otherwise some
>  	 * panels get very unhappy and cease to work. */
> -	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
> +	pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
>  		EDP_BLC_ENABLE);
>  
>  	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 413e729..c5739fc 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -220,7 +220,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
>  
>  	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
>  
> -	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | POWER_TARGET_ON);
> +	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
>  	POSTING_READ(lvds_encoder->reg);
>  	if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
>  		DRM_ERROR("timed out waiting for panel to power on\n");
> @@ -234,7 +234,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~POWER_TARGET_ON);
> +	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
>  	if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
>  		DRM_ERROR("timed out waiting for panel to power off\n");
>  
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-08-09 17:51 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-09 11:34 [PATCH 0/6] drm/i915: Clean up LVDS/PPS macros, suspend/resume logic Imre Deak
2016-08-09 11:34 ` [PATCH 1/6] drm/i915: Merge the PPS register definitions Imre Deak
2016-08-09 11:53   ` Ville Syrjälä
2016-08-09 13:24     ` Imre Deak
2016-08-09 17:21   ` [PATCH v2 " Imre Deak
2016-08-09 17:50     ` Ville Syrjälä
2016-08-09 11:34 ` [PATCH 2/6] drm/i915: Merge TARGET_POWER_ON and PANEL_POWER_ON flag definitions Imre Deak
2016-08-09 17:51   ` Ville Syrjälä [this message]
2016-08-09 11:34 ` [PATCH 3/6] drm/i915/lvds: Restore initial HW state during encoder enabling Imre Deak
2016-08-09 12:48   ` Ville Syrjälä
2016-08-09 14:40     ` Imre Deak
2016-08-09 14:55       ` Ville Syrjälä
2016-08-09 17:21   ` [PATCH v2 " Imre Deak
2016-08-09 17:46     ` Ville Syrjälä
2016-08-09 18:59     ` [PATCH v3 " Imre Deak
2016-08-09 11:34 ` [PATCH 4/6] drm/i915/dp: Restore PPS HW state from the encoder resume hook Imre Deak
2016-08-09 12:52   ` Ville Syrjälä
2016-08-09 15:15     ` Imre Deak
2016-08-09 17:21   ` [PATCH v2 " Imre Deak
2016-08-09 17:49     ` Ville Syrjälä
2016-08-09 11:34 ` [PATCH 5/6] drm/i915: Apply the PPS register unlock workaround more consistently Imre Deak
2016-08-09 13:01   ` Ville Syrjälä
2016-08-09 15:17     ` Imre Deak
2016-08-09 17:21   ` [PATCH v2 " Imre Deak
2016-08-09 17:46     ` Ville Syrjälä
2016-08-09 18:59     ` [PATCH v3 " Imre Deak
2016-08-09 11:34 ` [PATCH 6/6] drm/i915: Remove LVDS and PPS suspend time save/restore Imre Deak
2016-08-09 18:44   ` Ville Syrjälä
2016-08-09 12:05 ` ✓ Ro.CI.BAT: success for drm/i915: Clean up LVDS/PPS macros, suspend/resume logic Patchwork
2016-08-10  9:35 ` ✗ Ro.CI.BAT: failure for drm/i915: Clean up LVDS/PPS macros, suspend/resume logic (rev7) Patchwork

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